JP2002076613A - Method for manufacturing printed circuit board - Google Patents
Method for manufacturing printed circuit boardInfo
- Publication number
- JP2002076613A JP2002076613A JP2000257706A JP2000257706A JP2002076613A JP 2002076613 A JP2002076613 A JP 2002076613A JP 2000257706 A JP2000257706 A JP 2000257706A JP 2000257706 A JP2000257706 A JP 2000257706A JP 2002076613 A JP2002076613 A JP 2002076613A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- substrate
- copper
- conductor layer
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 48
- 238000007747 plating Methods 0.000 abstract description 39
- 239000011889 copper foil Substances 0.000 abstract description 27
- 239000011347 resin Substances 0.000 abstract description 27
- 229920005989 resin Polymers 0.000 abstract description 27
- 239000011888 foil Substances 0.000 abstract description 3
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 21
- 229910052802 copper Inorganic materials 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子部品の高密度
な実装を実現するプリント配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed wiring board for realizing high-density mounting of electronic components.
【0002】[0002]
【従来の技術】近年、ICやLSI等の集積回路部品を
実装するためのプリント配線板は、多層化やファインパ
ターン化等による高密度化が一段と進み、電子部品の高
密度実装回路板として電子機器の小型軽量化に貢献して
いる。配線パターンの高密度化を実現したプリント配線
板の一例としては例えばビルドアップ基板等が挙げられ
る。2. Description of the Related Art In recent years, printed wiring boards for mounting integrated circuit components such as ICs and LSIs have been further densified by multi-layering and fine patterning. This contributes to the reduction in size and weight of the equipment. An example of a printed wiring board that has realized a higher density of wiring patterns is, for example, a build-up board.
【0003】このビルドアップ基板は、ベースとなる内
層基板上に絶縁層と回路層とを交互に形成して行くもの
であって、例えば内層に設けられたインナービアホール
の上に、ブラインドビアホールを形成したり、さらにこ
のブラインドビアホールの上に部品実装用のパッドを設
けたりすること等で配線パターンの高密度化を図ってい
る。In this build-up substrate, an insulating layer and a circuit layer are alternately formed on an inner substrate serving as a base. For example, a blind via hole is formed on an inner via hole provided in an inner layer. In addition, the density of the wiring pattern is increased by providing a pad for mounting components on the blind via hole.
【0004】ここで、例えばベース基板の内層にインナ
ービアホールを形成し、形成されたこのインナービアホ
ールの上に部品実装用のパッドや、ブラインドビアホー
ルを形成する場合の形成方法について説明する。A method of forming an inner via hole in an inner layer of a base substrate and forming a component mounting pad or a blind via hole on the formed inner via hole will be described.
【0005】まず、両面銅張り積層板に貫通穴を形成
し、基板の両面の銅箔どうしがこの貫通穴を通じて接続
されるように、貫通穴の内壁及び基板両面の銅箔の上に
銅メッキを施す。次に、銅メッキが施された貫通穴内部
へ穴埋め樹脂を充填しこの樹脂の硬化後、貫通穴の開口
面より突出した余分な穴埋め樹脂を、機械研磨によって
除去しつつ基板表面を平坦化する。さらに、平坦化され
たビアホールの上に、いわゆる蓋メッキを施し、これを
基に部品搭載用のパッドや、さらにこのパッド上にブラ
インドビアホールを形成するという方法等が主に採用さ
れている。First, a through-hole is formed in a double-sided copper-clad laminate, and copper plating is performed on the inner wall of the through-hole and the copper foil on both sides of the substrate so that the copper foils on both sides of the substrate are connected to each other through the through-hole. Is applied. Next, a filling resin is filled into the through hole provided with the copper plating, and after the resin is cured, the excess filling resin protruding from the opening surface of the through hole is removed by mechanical polishing to flatten the substrate surface. . Further, a method of subjecting so-called lid plating to the flattened via hole, based on this, a method for forming a component mounting pad and further forming a blind via hole on the pad are mainly employed.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のプリント配線板の製造方法は、基板表面に予
め積層された銅箔の上に、さらに銅メッキが2回施され
ることになるので、導体の厚さが厚くなってしまい、近
年求められている微細なパターン形成を妨げる要因とな
る。However, in such a conventional method for manufacturing a printed wiring board, copper plating is further performed twice on a copper foil previously laminated on the substrate surface. In addition, the thickness of the conductor is increased, which is a factor that hinders the fine pattern formation required in recent years.
【0007】そこで、例えば基板に積層する銅箔厚さを
薄くすること等が考えられるが、この場合、使用可能な
銅箔が高価なものとなってしまう。また、例えば基板両
面の銅箔の接続の際のメッキ厚を薄くしようとすると、
勿論、貫通穴の内壁に形成されるメッキ厚も薄くなり、
電気的な接続信頼性の低下を招くことになり、蓋メッキ
のメッキ厚を薄くしようとすると、蓋メッキと穴埋め樹
脂との密着性が損なわれる。[0007] Therefore, for example, it is conceivable to reduce the thickness of the copper foil laminated on the substrate, but in this case, the usable copper foil becomes expensive. Also, for example, when trying to reduce the plating thickness when connecting copper foil on both sides of the board,
Of course, the plating thickness formed on the inner wall of the through hole is also reduced,
If the thickness of the lid plating is reduced, the adhesion between the lid plating and the filling resin is impaired.
【0008】本発明はこのような課題を解決するために
なされたもので、接続信頼性を低下させることなく、配
線パターンの高密度化を低コストで実現できるプリント
配線板の製造方法を提供するものである。The present invention has been made to solve such a problem, and provides a method of manufacturing a printed wiring board capable of realizing a high-density wiring pattern at a low cost without lowering connection reliability. Things.
【0009】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項1に係るプリント配線板の製造方法
は、導体層が両面に積層された基板に穴部を形成する工
程と、前記基板の各面に積層された前記導体層が接続さ
れるように前記穴部の内壁並びに前記導体層の上にさら
に導体層を形成する工程と、前記内壁に導体層が形成さ
れた前記基板の前記穴部に穴埋め材を充填する工程と、
前記穴部に前記穴埋め材が充填された前記基板上の導体
層を所定の厚さを残して除去する工程と、導体層の除去
により前記基板上より突出した前記穴埋め材を残存する
導体層とともに研磨し前記基板表面を平坦化する工程
と、前記平坦化された前記穴埋め材の上に回路パターン
を形成する工程とを有することを特徴とする。According to a first aspect of the present invention, there is provided a method for manufacturing a printed wiring board, comprising the steps of: forming a hole in a substrate having conductor layers laminated on both sides; Forming a conductor layer further on the inner wall of the hole and the conductor layer so that the conductor layer laminated on each surface of the substrate is connected, and wherein the conductor layer is formed on the inner wall. Filling the hole portion of the substrate with a filling material,
Removing the conductor layer on the substrate in which the hole portion is filled with the filling material while leaving a predetermined thickness, and removing the conductor layer together with the conductor layer that remains the filling material protruding from above the substrate. A step of polishing to flatten the substrate surface; and a step of forming a circuit pattern on the flattened hole filling material.
【0010】また、本発明の請求項2に係るプリント配
線板の製造方法は、請求項1記載のプリント配線板の製
造方法において、前記導体層の除去は、ハーフエッチン
グにより行われることを特徴とする。According to a second aspect of the present invention, in the method for manufacturing a printed wiring board according to the first aspect, the conductor layer is removed by half etching. I do.
【0011】さらに、本発明の請求項3に係るプリント
配線板の製造方法は、請求項1又は2記載のプリント配
線板の製造方法において、前記穴埋め材は、耐エッチン
グ性を有することを特徴とする。Further, a method of manufacturing a printed wiring board according to claim 3 of the present invention is characterized in that, in the method of manufacturing a printed wiring board according to claim 1 or 2, the filling material has etching resistance. I do.
【0012】上述した本発明のプリント配線板の製造方
法は、両面に導体層が積層された基板に、例えば貫通穴
や、一方の導体層に達する非貫通穴等を形成し、基板の
各面の導体層がこの穴部を通じて接続されるように、穴
部の内壁及び基板両面の導体層の上に銅メッキ等を施
し、この穴部に耐エッチング性を有するペースト等の穴
埋め印刷を行うものである。さらに、本発明のプリント
配線板の製造方法は、穴部に穴埋め樹脂等が埋設された
基板にハーフエッチング等を施して導体層の一部を厚み
方向に除去するとともに、導体層の除去により基板表面
より突出した穴埋め樹脂等を基板上に残存する導体層と
ともに研磨して基板表面を平坦化し、平坦化されたこの
穴埋め樹脂等の上に回路パターンを形成するものであ
る。In the above-described method of manufacturing a printed wiring board according to the present invention, for example, a through hole or a non-through hole reaching one conductor layer is formed on a substrate having conductor layers laminated on both sides, and each surface of the substrate is formed. In order to connect the conductive layers through the holes, the inner walls of the holes and the conductive layers on both sides of the substrate are subjected to copper plating or the like, and the holes are filled with an etching-resistant paste or the like. It is. Further, the method for manufacturing a printed wiring board of the present invention is characterized in that a half-etching or the like is performed on a substrate having a hole filled with a filling resin or the like to remove a part of the conductor layer in the thickness direction, and the substrate is removed by removing the conductor layer The filling resin or the like protruding from the surface is polished together with the conductor layer remaining on the substrate to flatten the substrate surface, and a circuit pattern is formed on the flattened filling resin or the like.
【0013】したがって、本発明のプリント配線板の製
造方法によれば、穴部内壁に形成されるメッキ厚が薄く
なってしまうことや、導体厚さを薄くするための高価な
銅箔を使用することなく、基板上に形成される回路のフ
ァインパターン化を図ることが可能なので、電気的な接
続信頼性を低下させることなく、配線パターンの高密度
化を低コストで実現することができる。Therefore, according to the method for manufacturing a printed wiring board of the present invention, the plating thickness formed on the inner wall of the hole is reduced, and an expensive copper foil for reducing the conductor thickness is used. Thus, a circuit formed on a substrate can be formed into a fine pattern without causing a decrease in electrical connection reliability, and a high-density wiring pattern can be realized at low cost.
【0014】[0014]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づき説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0015】図1は、本発明の実施形態に係るプリント
配線板のインナービアホール部分を概略的に示す図であ
る。FIG. 1 is a view schematically showing an inner via hole portion of a printed wiring board according to an embodiment of the present invention.
【0016】同図に示すように、このプリント配線板1
は、ベース基板の内層のインナービアホール16の上に
部品実装用の電極パッドを有するものであって、銅箔2
が両面に積層されているとともに貫通穴3が形成された
ベース基板としての両面銅張り積層板4と、この積層板
4の各面の銅箔2が接続されるように貫通穴3の内壁に
銅メッキを施して形成された銅メッキ層5と、銅メッキ
層5の形成とともに銅箔2の上にさらに銅メッキを施し
て形成された導体層から、所定の厚さを残して除去され
形成された導体層6と、銅メッキ層5が内壁に形成され
ている貫通穴3に充填された穴埋め樹脂7と、表面が平
坦化された穴埋め樹脂7の上面及び下面に形成されたパ
ッド(回路パターン)8とから構成されている。As shown in FIG.
Has an electrode pad for component mounting on the inner via hole 16 in the inner layer of the base substrate.
Are laminated on both sides and a double-sided copper-clad laminate 4 as a base substrate having a through-hole 3 formed therein, and the inner wall of the through-hole 3 is connected to the copper foil 2 on each side of the laminate 4. A copper plating layer 5 formed by performing copper plating and a conductor layer formed by further performing copper plating on the copper foil 2 together with the formation of the copper plating layer 5 are removed while leaving a predetermined thickness. Conductor layer 6, a filling resin 7 filling the through hole 3 in which the copper plating layer 5 is formed on the inner wall, and pads (circuits) formed on the upper and lower surfaces of the filling resin 7 having a flattened surface. 8).
【0017】次に、このように構成されたプリント配線
板1の製造方法を図2に基づき説明する。Next, a method for manufacturing the printed wiring board 1 configured as described above will be described with reference to FIG.
【0018】まず、図2(a)に示すように、両面に銅
箔2が予め形成された両面銅張り積層板4を用意し、こ
の両面銅張り積層板4に図2(b)に示すように、貫通
穴3を形成する。次に、図2(c)に示すように、貫通
穴3にスルーホールパネルメッキを施し、貫通穴3の内
壁並びに銅箔2の上に銅メッキ層5を形成する。さら
に、図2(d)に示すように、スルホールメッキの施さ
れた貫通穴3の中空部分に穴埋め樹脂7を埋め込み硬化
させた後、貫通穴3の上下の端面周辺に付着した不要な
樹脂を除去するとともに、基板の表面を平坦化する。次
いで、平坦化された基板表面の銅メッキ層5(銅箔2を
含む)を、図2(e)に示すようにハーフエッチングに
より所定の厚さを残して除去し導体層6とする。First, as shown in FIG. 2A, a double-sided copper-clad laminate 4 having copper foils 2 formed on both sides in advance is prepared, and this double-sided copper-clad laminate 4 is shown in FIG. 2B. Thus, the through hole 3 is formed. Next, as shown in FIG. 2C, through-hole panel plating is performed on the through-hole 3, and a copper plating layer 5 is formed on the inner wall of the through-hole 3 and on the copper foil 2. Further, as shown in FIG. 2D, after filling and curing a filling resin 7 in a hollow portion of the through hole 3 on which the through hole plating is performed, unnecessary resin adhering around the upper and lower end surfaces of the through hole 3 is removed. Removal and flattening of the surface of the substrate. Next, the copper plating layer 5 (including the copper foil 2) on the flattened substrate surface is removed by half etching to leave a predetermined thickness as shown in FIG.
【0019】さらに、図2(f)に示すように、ハーフ
エッチングにより両面銅張り積層板4の表面上より突出
した穴埋め樹脂7を導体層6とともに研磨し、両面銅張
り積層板4の表面を平坦化する。次に、図2(g)に示
すように、積層板4の両面に蓋メッキ9を形成し、さら
にこの蓋メッキ9をエッチングして図2(h)に示すよ
うにパッド(回路パターン)8を形成することで、ベー
ス基板の内層のインナービアホール16の上にパッド8
が積層形成されたプリント配線板1が作製される。な
お、この後、積層プレス、ブラインドビア形成、回路形
成、外形加工等の周知の製造工程を実施することで、所
望のプリント配線板を完成させることが可能となる。Further, as shown in FIG. 2 (f), the filling resin 7 projecting from the surface of the double-sided copper-clad laminate 4 is polished together with the conductor layer 6 by half-etching, and the surface of the double-sided copper-clad laminate 4 is polished. Flatten. Next, as shown in FIG. 2 (g), lid plating 9 is formed on both sides of the laminated board 4, and the lid plating 9 is etched to form pads (circuit patterns) 8 as shown in FIG. 2 (h). Forming the pad 8 on the inner via hole 16 in the inner layer of the base substrate.
The printed wiring board 1 on which is laminated is manufactured. After that, by performing well-known manufacturing processes such as lamination press, blind via formation, circuit formation, and external processing, a desired printed wiring board can be completed.
【0020】このように、本実施形態のプリント配線板
1の製造方法は、両面に銅箔2が積層された両面銅張り
積層板4に貫通穴3を形成し、積層板4の各面の銅箔2
がこの貫通穴3を通じて接続されるように、貫通穴3の
内壁及び基板両面の銅箔2の上に銅メッキ等を施し、こ
の貫通穴3の内部に耐エッチング性を有するペーストの
穴埋め印刷を行うものである。さらに、本実施形態のプ
リント配線板1の製造方法は、貫通穴3に穴埋め樹脂7
が充填された積層板4にハーフエッチングを施して導体
層の一部を厚み方向に除去するとともに、導体層の除去
により基板表面より突出した穴埋め樹脂7を基板上に残
存する導体層とともに研磨して基板表面を平坦化し、平
坦化されたこの穴埋め樹脂7の上に回路パターンを形成
するものである。As described above, in the method of manufacturing the printed wiring board 1 of the present embodiment, the through holes 3 are formed in the double-sided copper-clad laminate 4 having the copper foils 2 laminated on both sides, and Copper foil 2
The inner wall of the through-hole 3 and the copper foil 2 on both surfaces of the substrate are plated with copper or the like so as to be connected through the through-hole 3, and the inside of the through-hole 3 is filled with an etching-resistant paste. Is what you do. Further, the method of manufacturing the printed wiring board 1 of the present embodiment is a
A half-etching is performed on the laminated plate 4 filled with, and a part of the conductor layer is removed in the thickness direction, and the filling resin 7 protruding from the substrate surface by removing the conductor layer is polished together with the conductor layer remaining on the substrate. Thus, a circuit pattern is formed on the flattened filling resin 7 by flattening the substrate surface.
【0021】したがって、本実施形態のプリント配線板
1の製造方法によれば、貫通穴3の内壁に形成されるメ
ッキ厚が薄くなってしまうことや、メッキ厚等を薄くす
るための高価な銅箔を使用することなく、基板上に形成
される回路のファインパターン化を図ることが可能なの
で、電気的な接続信頼性を低下させることなく、配線パ
ターンの高密度化を低コストで実現することができる。Therefore, according to the method of manufacturing the printed wiring board 1 of the present embodiment, the plating thickness formed on the inner wall of the through hole 3 is reduced, and expensive copper for reducing the plating thickness and the like is used. Fine patterning of the circuit formed on the substrate can be achieved without using foil, so high-density wiring patterns can be realized at low cost without reducing electrical connection reliability. Can be.
【0022】以上、本発明を実施の形態により具体的に
説明したが、本発明は前記実施形態にのみ限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
である。例えば、本実施形態では、貫通穴3を基に両面
銅張り積層板4の内層のインナービアホール16の上に
パッド8を形成するものであったが、これに代えて多層
銅張り積層板の一方の内層銅箔に達する非貫通穴を形成
し、この非貫通穴に電解メッキ、樹脂穴埋め、ハーフエ
ッチング、平坦化研磨、蓋メッキを行って、ブランイン
ドビアホールを形成し、パッド8や回路パターン等を形
成するようにしてもよい。また、非貫通穴形成後、導電
性のペーストでの穴埋め、ハーフエッチング、平坦化研
磨、蓋メッキを行うようにしても良い。Although the present invention has been described in detail with reference to the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. For example, in the present embodiment, the pads 8 are formed on the inner via holes 16 in the inner layer of the double-sided copper-clad laminate 4 based on the through-holes 3. A non-through hole reaching the inner layer copper foil is formed, and the non-through hole is subjected to electrolytic plating, resin filling, half etching, flattening polishing, and lid plating to form a blind via hole, and to form a pad 8 and a circuit pattern. May be formed. After the non-through hole is formed, filling with a conductive paste, half etching, flattening polishing, and lid plating may be performed.
【0023】[0023]
【実施例】次に、本発明の実施例を図2並びに図3に基
づき説明する。この実施例では、ベース基板の内層のイ
ンナービアホール16の上にブラインドビアホールを1
3を有する4層のビルドアップ基板17の製造方法につ
いて説明する。Next, an embodiment of the present invention will be described with reference to FIGS. In this embodiment, one blind via hole is formed on the inner via hole 16 in the inner layer of the base substrate.
A method for manufacturing the four-layered build-up substrate 17 having 3 will be described.
【0024】まず、図2(a)に示すように、基材厚さ
0.6mm、銅箔2の厚さが12μmのガラスエポキシ
製の両面銅張り積層板4を用意し、図2(b)に示すよ
うに、この両面銅張り積層板4に直径0.25mmのド
リルにより貫通穴3を形成する。次に、図2(c)に示
すように、両面銅張り積層板4の両面の銅箔2が貫通穴
3を通じて接続されるように、この両面銅張り積層板4
に設定厚さ20μmの銅パネルメッキを施し、貫通穴3
の内壁並びに銅箔2の上に銅メッキ層5を形成する。さ
らに、図2(d)に示すように、スルホールメッキの施
された貫通穴3の中空部分にスクリーン印刷により永久
的に埋設されるエポキシ系の穴埋め樹脂7を充填し加熱
硬化させる。この後、セラミックロールとバフを用いた
研磨によって、貫通穴3の上下の端面周辺に付着した不
要な樹脂を除去するとともに、基板の表面を平坦化す
る。First, as shown in FIG. 2A, a double-sided copper-clad laminate 4 made of glass epoxy having a substrate thickness of 0.6 mm and a copper foil 2 having a thickness of 12 μm was prepared. As shown in (1), a through hole 3 is formed in the double-sided copper-clad laminate 4 by a drill having a diameter of 0.25 mm. Next, as shown in FIG. 2C, the copper foils 2 on both sides of the double-sided copper-clad laminate 4 are connected through the through holes 3.
Is plated with a copper panel with a set thickness of 20 μm.
A copper plating layer 5 is formed on the inner wall and the copper foil 2. Further, as shown in FIG. 2D, the hollow portion of the through hole 3 on which the through-hole plating has been performed is filled with an epoxy filling resin 7 which is permanently buried by screen printing, and is cured by heating. Thereafter, unnecessary resin adhering to the periphery of the upper and lower end surfaces of the through hole 3 is removed by polishing using a ceramic roll and a buff, and the surface of the substrate is flattened.
【0025】次いで、図2(e)に示すように、両面銅
張り積層板4上に残存する導体層の厚さが約8μmにな
るように、塩化第二銅をエッチング液としてスプレー法
によりハーフエッチングを施し導体層6を形成する。さ
らに、図2(f)に示すように、セラミックロールとバ
フを用いて、導体層6の残存厚さが5μmとなるよう
に、両面銅張り積層板4の表面上より突出した穴埋め樹
脂7を導体層6とともに研磨し、両面銅張り積層板4の
表面を平坦化する。次に、図2(g)に示すように、積
層板4の両面に設定厚さ12μmの銅パネルメッキを施
して蓋メッキ9を形成し、さらにこの蓋メッキ9をエッ
チングして図2(h)に示すように回路パターン8を形
成する。この後、図3に示すように、例えば厚さ60μ
mの絶縁層10に厚さ12μmの銅箔(銅メッキ層)1
1が積層された銅箔付きの樹脂シート12を用いて、ホ
ットプレスにより積層成形を行い、レーザ加工、銅メッ
キによるブラインドビアホール13の形成、回路パター
ン14の形成、並びにソルダーレジスト15の形成を経
て、4層のビルドアップ基板17を完成させる。Next, as shown in FIG. 2 (e), half of the conductive layer remaining on the double-sided copper-clad laminate 4 is spray-etched using cupric chloride as an etchant so that the thickness of the conductor layer becomes about 8 μm. Etching is performed to form the conductor layer 6. Further, as shown in FIG. 2 (f), using a ceramic roll and a buff, the filling resin 7 protruding from the surface of the double-sided copper-clad laminate 4 so that the remaining thickness of the conductor layer 6 becomes 5 μm. Polishing is performed together with the conductor layer 6 to flatten the surface of the double-sided copper-clad laminate 4. Next, as shown in FIG. 2 (g), a copper plating of a set thickness of 12 μm is applied to both surfaces of the laminate 4 to form a lid plating 9, and the lid plating 9 is etched to form a lid plating 9 as shown in FIG. The circuit pattern 8 is formed as shown in FIG. Thereafter, as shown in FIG.
12 μm thick copper foil (copper plated layer) 1
Using a resin sheet 12 with a copper foil on which 1 is laminated, lamination molding is performed by hot pressing, laser processing, formation of a blind via hole 13 by copper plating, formation of a circuit pattern 14, and formation of a solder resist 15 Then, a four-layer build-up substrate 17 is completed.
【0026】この結果、上記実施例により作製されたプ
リント配線板とハーフエッチングを用いない従来法によ
り作製されたプリント配線板との導体層の厚さ並びに特
性等は下記の表に示すようなものとなった。As a result, the thickness, characteristics, etc. of the conductor layers of the printed wiring board manufactured according to the above embodiment and the printed wiring board manufactured by the conventional method without using half etching are as shown in the following table. It became.
【0027】[0027]
【表1】 [Table 1]
【表2】 この結果からも明らかなように、本実施例のプリント配
線板の製造方法によれば、電気的な接続信頼性を低下さ
せることなく、基板上に形成される回路のファインパタ
ーン化を図ることが可能である。[Table 2] As is clear from these results, according to the method for manufacturing a printed wiring board of the present embodiment, it is possible to form a fine pattern of a circuit formed on a substrate without reducing electrical connection reliability. It is possible.
【0028】[0028]
【発明の効果】以上説明したように、本発明は、両面に
導体層が積層された基板に穴部を形成し、基板の各面の
導体層がこの穴部を通じて接続されるように、穴部の内
壁及び基板両面の導体層の上に銅メッキ等を施し、この
穴部に穴埋め樹脂等を埋設する。さらに、本発明は、穴
部に穴埋め樹脂等が埋設された基板にハーフエッチング
等を施して導体層の一部を厚み方向に除去するととも
に、導体層の除去により基板表面より突出した穴埋め樹
脂等を基板上に残存する導体層とともに研磨して基板表
面を平坦化し、平坦化されたこの穴埋め樹脂等の上に回
路パターンを形成するものである。As described above, according to the present invention, a hole is formed in a substrate having conductor layers laminated on both sides, and the hole is formed so that the conductor layers on each side of the substrate are connected through the hole. Copper plating or the like is applied to the inner wall of the unit and the conductor layers on both surfaces of the substrate, and a filling resin or the like is embedded in these holes. Furthermore, the present invention provides a substrate in which a hole filling resin or the like is embedded by half-etching or the like to remove a part of the conductor layer in the thickness direction, and also removes the conductor layer from the substrate surface by removing the conductor layer. Is polished together with the conductor layer remaining on the substrate to flatten the substrate surface, and a circuit pattern is formed on the flattened resin or the like.
【0029】したがって、本発明によれば、穴部内壁に
形成されるメッキ厚が薄くなってしまうことや、銅箔厚
さを薄くするための高価な銅箔を使用することなく、基
板上に形成される回路のファインパターン化を図ること
が可能なので、電気的な接続信頼性を低下させることな
く、配線パターンの高密度化を低コストで実現すること
が可能となる。Therefore, according to the present invention, the thickness of the plating formed on the inner wall of the hole is reduced, and the expensive copper foil for reducing the thickness of the copper foil is not used on the substrate. Since a circuit to be formed can be formed into a fine pattern, it is possible to realize a high-density wiring pattern at low cost without deteriorating electrical connection reliability.
【図面の簡単な説明】[Brief description of the drawings]
【図1】本発明の実施形態に係るプリント配線板を概略
的に示す図。FIG. 1 is a view schematically showing a printed wiring board according to an embodiment of the present invention.
【図2】図1のプリント配線板の製造方法を説明するた
めの図。FIG. 2 is a view for explaining a method of manufacturing the printed wiring board of FIG. 1;
【図3】図2のプリント配線板の製造方法を応用して作
製されるビルドアップ基板を概略的に示す図。FIG. 3 is a view schematically showing a build-up board manufactured by applying the method for manufacturing a printed wiring board of FIG. 2;
1…プリント配線板 2…銅箔 3…貫通穴 4…両面銅張り積層板 5…銅メッキ層 6…ハーフエッチングにより形成された導体層 7…穴埋め樹脂 8…パッド(回路パターン) 9…蓋メッキ 10…絶縁層 11…銅箔及び銅メッキ層 12…銅箔付きの樹脂シート 13…ブラインドビアホール 14…回路パターン 15…ソルダーレジスト 16…インナービアホール 17…ビルドアップ基板 DESCRIPTION OF SYMBOLS 1 ... Printed wiring board 2 ... Copper foil 3 ... Through-hole 4 ... Double-sided copper-clad laminate 5 ... Copper plating layer 6 ... Conductive layer formed by half etching 7 ... Filling resin 8 ... Pad (circuit pattern) 9 ... Lid plating DESCRIPTION OF SYMBOLS 10 ... Insulating layer 11 ... Copper foil and copper plating layer 12 ... Resin sheet with copper foil 13 ... Blind via hole 14 ... Circuit pattern 15 ... Solder resist 16 ... Inner via hole 17 ... Build-up board
Claims (3)
形成する工程と、 前記基板の各面に積層された前記導体層が接続されるよ
うに前記穴部の内壁並びに前記導体層の上にさらに導体
層を積層する工程と、 前記内壁に導体層が積層された前記基板の前記穴部に穴
埋め材を充填する工程と、 前記穴部に前記穴埋め材が充填された前記基板上の導体
層を所定の厚さを残して除去する工程と、 導体層の除去により前記基板上より突出した前記穴埋め
材を残存する導体層とともに研磨し前記基板表面を平坦
化する工程と、 前記平坦化された前記穴埋め材の上に回路パターンを形
成する工程とを有することを特徴とするプリント配線板
の製造方法。A step of forming a hole in a substrate having a conductor layer laminated on both sides thereof; and an inner wall of the hole and the conductor layer such that the conductor layers laminated on each surface of the substrate are connected. Further laminating a conductor layer on the substrate; filling the hole portion of the substrate with the conductor layer laminated on the inner wall with a filling material; and filling the hole portion with the filling material. Removing the conductor layer with a predetermined thickness, polishing the hole filling material protruding from above the substrate together with the remaining conductor layer by removing the conductor layer, and flattening the substrate surface; Forming a circuit pattern on the formed hole filling material.
法において、 前記導体層の除去は、ハーフエッチングにより行われる
ことを特徴とするプリント配線板の製造方法。2. The method for manufacturing a printed wiring board according to claim 1, wherein the removal of the conductive layer is performed by half etching.
製造方法において、前記穴埋め材は、耐エッチング性を
有することを特徴とするプリント配線板の製造方法。3. The method for manufacturing a printed wiring board according to claim 1, wherein the filling material has etching resistance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000257706A JP2002076613A (en) | 2000-08-28 | 2000-08-28 | Method for manufacturing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000257706A JP2002076613A (en) | 2000-08-28 | 2000-08-28 | Method for manufacturing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002076613A true JP2002076613A (en) | 2002-03-15 |
Family
ID=18746130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000257706A Withdrawn JP2002076613A (en) | 2000-08-28 | 2000-08-28 | Method for manufacturing printed circuit board |
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JP (1) | JP2002076613A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2022170470A (en) * | 2021-04-28 | 2022-11-10 | コイト電工株式会社 | seat rotator |
CN115442961A (en) * | 2022-09-29 | 2022-12-06 | 高德(江苏)电子科技股份有限公司 | Ultrathin random interconnection circuit board and manufacturing method thereof |
JP7502170B2 (en) | 2020-12-14 | 2024-06-18 | イビデン株式会社 | Method for manufacturing printed wiring board |
-
2000
- 2000-08-28 JP JP2000257706A patent/JP2002076613A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7502170B2 (en) | 2020-12-14 | 2024-06-18 | イビデン株式会社 | Method for manufacturing printed wiring board |
JP2022170470A (en) * | 2021-04-28 | 2022-11-10 | コイト電工株式会社 | seat rotator |
CN115442961A (en) * | 2022-09-29 | 2022-12-06 | 高德(江苏)电子科技股份有限公司 | Ultrathin random interconnection circuit board and manufacturing method thereof |
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