JP2002023344A - Scribe line arrangement method, reticle and exposure method - Google Patents

Abstract

(57) [Problem] To provide a scribe line arrangement method, a reticle, and an exposure method which can suppress generation of Al burrs on a chip side in a scribe process. A scribe line arranging method according to the present invention comprises exposing a reticle pattern 3 including a rectangular chip data area 9 and scribe line data areas 10 and 11 around the reticle pattern 3 onto a wafer, thereby exposing the wafer. This is a method of arranging scribe lines. In this method, a first scribe line data area 10 having a predetermined scribe width is arranged at a lower part and a right part of the chip data area 9, and a first scribe line data area is provided at an upper part and a left part of the chip data area 9. The second scribe line data area 11 having a width equal to or less than 1/4 of the scribe width of the area is arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for arranging scribe lines, a reticle, and an exposure method capable of suppressing generation of Al burrs on a chip side during a scribe process.

[0002]

2. Description of the Related Art FIG. 3 is a plan view for explaining a conventional exposure method.

First, a reticle (not shown) for imposing on a wafer is prepared. This reticle has a reticle pattern including a rectangular chip data area 109 and a scribe line data area 110 formed on the right and lower parts thereof. The scribe line data area 110 has a predetermined scribe width. In the scribe line data area 110, data 107, 1 such as alignment marks and test element groups are stored.
08 is arranged.

After that, a wafer having a resist film 101 applied on the Al alloy film is prepared. Next, the reticle is set in an exposure apparatus, and the reticle pattern 103 is exposed on the resist film 101 by the exposure apparatus.

Next, a reticle pattern 104 is exposed to the right of the reticle pattern 103 exposed on the resist film 101 on the wafer using the reticle. At this time, the resist film 1 is formed so that the chip data area 109 in the reticle pattern 104 does not overlap the scribe line data area 110 arranged on the right side of the chip data area 109 in the reticle pattern 103.
First, the reticle pattern 104 is exposed.

Thereafter, a reticle pattern 105 is exposed by using the reticle below the reticle pattern 103 exposed on the resist film 101 on the wafer. At this time, the resist film 1 is formed so that the chip data area 109 in the reticle pattern 105 does not overlap the scribe line data area 110 arranged below the chip data area 109 in the reticle pattern 103.
First, the reticle pattern 105 is exposed.

Next, a reticle pattern 106 is exposed to the right of the reticle pattern 105 exposed on the resist film 101 on the wafer by using the reticle. At this time, the chip data area 109 in the reticle pattern 104 should not overlap with the scribe line data area 110 arranged to the right of the chip data area 109 in the reticle pattern 105, and the chip data area In the scribe line data area 110 arranged below 109,
Chip data area 10 in reticle pattern 106
The reticle pattern 106 is exposed on the resist film 101 so that the layers 9 do not overlap.

Thereafter, by developing the resist film 101, a resist pattern (not shown) is formed on the Al alloy film. Next, by etching using this resist pattern as a mask, the Al alloy film is patterned to form an Al wiring.

Next, after a normal semiconductor device manufacturing process (wafer pre-process) is performed on the wafer, the wafer is diced along the scribe center 125. Thereby, a plurality of semiconductor chips are separated from the wafer.

[0010]

In the above-mentioned conventional exposure method, as shown in FIG. 3, since there is no scribe line data area on the upper side and the left side of the exposed reticle patterns 103 to 106, an Al wiring is formed. In the process,
The Al alloy film remains on the upper side and the left side. Therefore, when dicing the upper and left sides in the wafer dicing step, Al burrs due to the Al alloy film occur on the outer peripheral portion of the semiconductor chip. A
The burring of 1 means that when dicing the wafer, the Al alloy film cannot be completely removed by the dicing blade, and the Al pieces are near the outer periphery of the semiconductor chip (chip side).
It was left in a state of standing up. The burr of Al does not cause any problem in ordinary wire bonding, but becomes a problem when performing TAB (Tape Automated Bonding) or the like.

That is, due to recent miniaturization of packages, the distance between a semiconductor chip and a lead connecting the semiconductor chip is only about several tens μm. For this reason, when the Al burrs occur on the chip side, the Al burrs and the leads come into contact with each other to cause a short circuit in the wiring, and the semiconductor chip may be defective.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a scribe line arrangement method, a reticle, and an exposure method capable of suppressing generation of Al burrs on a chip side during a scribe process. It is to provide a method.

[0013]

In order to solve the above problems, a scribe line arranging method according to the present invention exposes a reticle pattern comprising a rectangular chip data area and a scribe line data area around the rectangular chip data area onto a wafer. A method of arranging scribe lines on the wafer, wherein scribe line data areas having a predetermined scribe width are arranged at a lower part and a right part of the chip data area, and an upper part and a left part of the chip data area are arranged. And a scribe line data area having a width equal to or less than 1/4 of the predetermined scribe width.

In the above scribe line arranging method, a scribe line data area having a width of 1/4 or less of a predetermined scribe width is arranged at an upper part and a left part of a rectangular chip data area. Therefore, when the reticle pattern is exposed on the wafer, a scribe line data area having a width of 1/4 or less of a predetermined scribe width can be formed on the upper side and the left side of the chip data area. Thus, in the step of forming the Al wiring, the Al alloy film is not left in the scribe line data regions on the upper side and the left side. Therefore, when the upper and left sides are diced in the wafer dicing step, the Al alloy film remaining in portions other than the scribe line data area on the upper and left sides can be completely cut off by a dicing blade. Therefore, it is possible to suppress the occurrence of Al burrs due to the Al alloy film on the outer peripheral portion of the semiconductor chip.

According to the method of arranging scribe lines according to the present invention, a reticle pattern including a rectangular chip data area and a scribe line data area around the rectangular chip data area is exposed on a wafer so as to be adjacent to each other. Wherein a scribe line data area having a predetermined scribe width is arranged at a lower part and a right part of the chip data area, and a scribe line data area having a predetermined scribe width is disposed at an upper part and a left part of the chip data area. When a scribe line data area having a width of 4 times or less is arranged and an adjacent reticle pattern is exposed on the wafer, the scribe line data area arranged below the chip data area in one reticle pattern is placed on the other reticle pattern. In the upper part of the chip data area While overlapping the live line data area, the scribe line data area arranged on the left side of the chip data area in the other reticle pattern is located on the scribe line data area arranged on the right side of the chip data area in the one reticle pattern. It is characterized by performing double exposure for superposition.

Further, in the scribe line arrangement method according to the present invention, at least one of the alignment mark data and the test element group data is arranged in the scribe line data area having the predetermined scribe width. Is preferred.

A reticle according to the present invention is a reticle having a reticle pattern including a rectangular chip data area and a scribe line data area formed around the rectangular chip data area. The reticle is arranged at a lower part and a right part of the chip data area. A first scribe line data area having a predetermined scribe width, and a width of 倍 times or less of the scribe width of the first scribe line data area, which is arranged above and to the left of the chip data area. And a second scribe line data area having a reticle pattern.

In the reticle according to the present invention,
It is preferable that at least one of alignment mark data and test element group data is arranged in the first scribe line data area.

An exposure method according to the present invention is directed to a reticle pattern including a rectangular chip data area and a scribe line data area surrounding the rectangular chip data area, wherein a scribe line having a predetermined scribe width is provided below and to the right of the chip data area. A data area is arranged, and one of the predetermined scribe widths is located above and to the left of the chip data area.
A step of preparing a reticle having a reticle pattern in which a scribe line data area having a width of / 4 or less is arranged; and a step of exposing the reticle pattern on a wafer.

An exposure method according to the present invention is a method of exposing a reticle pattern comprising a rectangular chip data area and a scribe line data area around the rectangular chip data area on a wafer, wherein the reticle pattern includes a lower part of the chip data area, A scribe line data area having a predetermined scribe width is arranged on the right part, and a scribe line data area having a width of 1/4 or less of the predetermined scribe width is arranged on the upper part and the left part of the chip data area. A step of preparing a reticle having a reticle pattern, a first step of exposing the reticle pattern on a wafer, and a step of exposing the reticle pattern next to the reticle pattern exposed on the wafer in the first step. In the second step, the reticle pattern exposed on the wafer in the first step is The scribe line data area arranged above the chip data area in the reticle pattern to be exposed next on the wafer is superimposed on the scribe line data area arranged below the chip data area to be exposed on the wafer. The scribe line data area arranged to the left of the chip data area in the reticle pattern to be exposed next on the wafer is superimposed on the scribe line data area arranged to the right of the chip data area in the reticle pattern exposed to light. And a second step of performing double exposure.

In the above exposure method, a scribe line data area having a width equal to or less than a quarter of a predetermined scribe width is arranged above and to the left of the chip data area in the reticle pattern. Therefore, when a plurality of reticle patterns are exposed on a wafer adjacent to each other, a scribe line data area having a width of 1/4 or less of a predetermined scribe width can be formed on the upper side and the left side of the entire transfer pattern. Thus, in the step of forming the Al wiring, the Al alloy film is not left in the scribe line data regions on the upper side and the left side. Therefore, when the upper and left sides are diced in the wafer dicing step, the Al alloy film remaining in portions other than the scribe line data area on the upper and left sides can be completely cut off by a dicing blade. Therefore, the outer peripheral portion of the semiconductor chip is
Further, in the exposure method according to the present invention, at least one of alignment mark data and test element group data is arranged in the scribe line data area having the predetermined scribe width. Is preferred.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view for explaining an exposure method according to an embodiment of the present invention. FIG. 2 is a plan view showing a reticle pattern used in the exposure method according to the embodiment of the present invention.

First, as shown in FIG. 2, a reticle for imposing on a wafer is prepared. This reticle has a reticle pattern 13 composed of a rectangular chip data area 19 and first and second scribe line data areas 20 and 21. The first scribe line data area 20 has a predetermined scribe width and is arranged below and to the right of the chip data area 19. In the first scribe line data area 20, data 17, 18 such as an alignment mark and a test element group are arranged. The second scribe line data area 21 has a width equal to or less than １ ／ of the scribe width of the first scribe line data area 20.

Thereafter, as shown in FIG. 1, a wafer having a resist film 1 applied on an Al alloy film is prepared. Next, the reticle is set in an exposure apparatus, and the reticle pattern 13 is exposed on the resist film 1 by the exposure apparatus. As a result, the chip data area 9 and the first and second scribe line data areas 1 are formed in the resist film 1.
The pattern 3 composed of 0 and 11 is transferred, and the patterns 7 and 8 such as alignment marks and test element groups are transferred to the first scribe line data area 10.

Next, on the right side of the pattern 3 exposed on the resist film 1, the reticle pattern 1
3 is exposed. At this time, the first scribe line data area 10 arranged on the right of the chip data area 9 in the pattern 3 and the second scribe line arranged on the left of the chip data area 19 in the reticle pattern 13 shown in FIG. The reticle pattern 13 is exposed on the resist film 1 so that the line data areas 21 overlap. As a result, as shown in FIG. 1, the pattern 4 including the chip data area 9 and the first and second scribe line data areas 10 and 11 is transferred to the right side of the pattern 3 in the resist film 1, and the first Scribe line data area 10
Are transferred patterns 7, 8 such as an alignment mark and a test element group. At this time, pattern 4
The second scribe line data area 11 arranged on the left of the chip data area 9 in the pattern 3 overlaps with the first scribe line data area 10 arranged on the right of the chip data area 9 in the pattern 3. However, the first scribe line data area 10 does not overlap the pattern 7. In other words, the pattern 7 is formed with a narrow width such that the first scribe line data areas 10 do not overlap.

Thereafter, a reticle pattern 13 is exposed by using the reticle below the pattern 3 exposed on the resist film 1. At this time, the first scribe line data area 10 arranged below the chip data area 9 in the pattern 3 is placed in the first scribe line data area 10 arranged in the reticle pattern 13 shown in FIG. The reticle pattern 13 is exposed on the resist film 1 so that the regions 21 overlap. As a result, as shown in FIG. 1, the pattern 5 including the chip data area 9 and the first and second scribe line data areas 10 and 11 is transferred below the pattern 3 in the resist film 1, and the first Scribe line data area 10
Are transferred patterns 7, 8 such as an alignment mark and a test element group. At this time, pattern 5
The second scribe line data area 11 arranged above the chip data area 9 in the pattern 3 overlaps the first scribe line data area 10 arranged below the chip data area 9 in the pattern 3. However, the first scribe line data area 10 does not overlap the pattern 8. In other words, the pattern 8 is formed with a narrow width such that the first scribe line data areas 10 do not overlap.

Next, on the right side of the pattern 5 exposed on the resist film 1, the reticle pattern 1
3 is exposed. At this time, the first scribe line data area 10 arranged on the right part of the chip data area 9 in the pattern 5 and the second scribe line arranged on the left part of the chip data area 19 in the reticle pattern 13 shown in FIG. The reticle pattern 13 is exposed on the resist film 1 so that the line data areas 21 overlap. As a result, as shown in FIG. 1, the pattern 6 including the chip data area 9 and the first and second scribe line data areas 10 and 11 is transferred to the right side of the pattern 5 in the resist film 1, and the first Scribe line data area 10
Are transferred patterns 7, 8 such as an alignment mark and a test element group. At this time, pattern 6
The second scribe line data area 11 arranged on the left part of the chip data area 9 in the pattern 5 is overlapped with the first scribe line data area 10 arranged on the right part of the chip data area 9 in the pattern 5, and the pattern 6 The second scribe line data area 11 arranged above the chip data area 9 in the pattern 4 overlaps the first scribe line data area 10 arranged below the chip data area 9 in the pattern 4.

Thereafter, by developing the resist film 1, a resist pattern (not shown) is formed on the Al alloy film. Next, by etching using this resist pattern as a mask, the Al alloy film is patterned to form an Al wiring.

Next, after the usual semiconductor device manufacturing process (wafer pre-process) is performed on the wafer, the wafer is diced along the scribe center 25. Thereby, a plurality of semiconductor chips are separated from the wafer. At this time, since a dicing blade having a width larger than the width of the patterns 7 and 8 is used, the patterns 7 and 8 are completely removed by the dicing blade. That is, the width of the dicing blade is large enough to remove a part of the second scribe line data area 11.

According to the above embodiment, the second scribe line data area 21 is arranged above and to the left of the chip data area 19 in the reticle pattern 13. Therefore, when the reticle pattern 13 is transferred to the resist film 1, the second scribe line data area 11 can be formed on the upper side and the left side of the patterns 3 to 6. Thereby, in the step of forming the Al wiring, the A and the second scribe line data area 11 on the upper side and the left side
The 1 alloy film is not left (in other words, a pattern is formed in the second scribe line data area 11 so that the Al alloy film is not left in the Al wiring process). Therefore, when the upper and left sides are diced in the wafer dicing step, the Al alloy film remaining on the upper and left sides other than the second scribe line data area 11 is completely cut off by a dicing blade. Can be. For this reason, it is possible to suppress the occurrence of Al burr due to the Al alloy film on the outer peripheral portion of the semiconductor chip, and it is possible to suppress the occurrence of defects such as short-circuiting of the wiring.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In the present embodiment, the reticle pattern 13 is transferred four times (four shots) to the resist film 1 on the wafer.
The number of shots is not limited to four and can be changed as appropriate.

The width of the second scribe line data area 11 may be equal to or less than １ ／ of the width of the first scribe line data area 10. About 1/4 times is particularly preferable.

[0034]

As described above, according to the present invention, the scribe line data area having a width of 1/4 or less of the predetermined scribe width is arranged at the upper part and the left part of the rectangular chip data area. . Therefore, it is possible to provide a scribe line arrangement method, a reticle, and an exposure method that can suppress generation of Al burrs on the chip side during the scribe process.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an exposure method according to an embodiment of the present invention.

FIG. 2 is a plan view showing a reticle pattern used in the exposure method according to the embodiment of the present invention.

FIG. 3 is a plan view for explaining a conventional exposure method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Resist film 3-6 Transfer pattern 7, 8 Pattern of alignment mark, test element group, etc. 9 Chip data area 10 First scribe line data area 11 Second scribe line data area 13 Reticle pattern 17, 18 Alignment mark and test Element group data 19 Chip data area 20 First scribe line data area 21 Second scribe line data area 25 Scribe line center 101 Resist film 103 to 106 Reticle pattern 107, 108 Data such as alignment mark and test element group 109 Chip data area 110 Scribe line data area 125 Scribe line center

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/301 H01L 21/30 502P 21/78 L

Claims (8)

[Claims] 1. A method for arranging scribe lines on a wafer by exposing a reticle pattern comprising a rectangular chip data area and a scribe line data area around the rectangular chip data area on the wafer, the method comprising: A scribe line data area having a predetermined scribe width is arranged at a lower part and a right part, and a scribe line data area having a width of 1/4 or less of the predetermined scribe width is arranged at an upper part and a left part of the chip data area. A method for arranging scribe lines. 2. A method of arranging a scribe line on a wafer by exposing a reticle pattern composed of a rectangular chip data area and a scribe line data area around the rectangular area on a wafer so as to be adjacent to each other, A scribe line data area having a predetermined scribe width is arranged at a lower part and a right part of the chip data area, and a scribe line having a width of 1/4 or less of the predetermined scribe width is provided at an upper part and a left part of the chip data area. When arranging the data area and exposing the adjacent reticle pattern on the wafer,
The scribe line data area arranged above the chip data area in the other reticle pattern is superimposed on the scribe line data area arranged below the chip data area in the one reticle pattern, and the chip data area arranged in the one reticle pattern. A scribe line data area arranged on the right side of the reticle pattern and a scribe line data area arranged on the left side of the chip data area in the other reticle pattern. 3. The scribe according to claim 1, wherein at least one of alignment mark data and test element group data is arranged in the scribe line data area having the predetermined scribe width. Line placement method. 4. A reticle having a reticle pattern including a rectangular chip data area and a scribe line data area formed around the rectangular chip data area, wherein a predetermined scribe width is arranged at a lower part and a right part of the chip data area. A first scribe line data area having a width of not more than 1/4 of a scribe width of the first scribe line data area, which is arranged above and to the left of the chip data area. A reticle comprising a reticle pattern comprising: a line data area; 5. The reticle according to claim 4, wherein at least one of alignment mark data and test element group data is arranged in the first scribe line data area. 6. A reticle pattern comprising a rectangular chip data area and a scribe line data area surrounding the rectangular chip data area, wherein a scribe line data area having a predetermined scribe width is arranged below and to the right of the chip data area. Preparing a reticle having a reticle pattern in which a scribe line data area having a width equal to or less than 1/4 of the predetermined scribe width is arranged at an upper part and a left part of the chip data area; and An exposure method, comprising: exposing on top. 7. A method of exposing a reticle pattern composed of a rectangular chip data area and a scribe line data area around the rectangular area to a wafer so that a plurality of reticle patterns are adjacent to each other. A reticle having a reticle pattern in which a scribe line data area having a width is arranged and a scribe line data area having a width equal to or less than 1/4 of the predetermined scribe width is arranged above and to the left of the chip data area. A first step of exposing the reticle pattern on a wafer; and a second step of exposing a reticle pattern next to the reticle pattern exposed on the wafer in the first step. A chip data area in a reticle pattern exposed on a wafer in the first step The scribe line data area arranged above the chip data area in the reticle pattern to be next exposed on the wafer is superimposed on the scribe line data area arranged below, and the wafer is exposed on the wafer in the first step. A double exposure is performed in which the scribe line data area arranged on the right side of the chip data area in the reticle pattern is overlapped with the scribe line data area arranged on the left side of the chip data area in the reticle pattern to be exposed on the next wafer. An exposure method, comprising: a second step. 8. The exposure according to claim 6, wherein at least one of alignment mark data and test element group data is arranged in the scribe line data area having the predetermined scribe width. Method.