JP2008098417A - Acceleration sensor manufacturing substrate, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out an anode junction stably in a surface protection cover glass. <P>SOLUTION: An anode junction electrode terminal 8 comes into contact with a wafer substrate 1 through an opening 5c for an anode junction electrode terminal, and is connected to an anode junction internal electrode 6b of an internal region through the wafer substrate 1. Upon the anode junction, a voltage is applied from the anode junction electrode terminal 8 to the anode junction internal electrode 6b through the wafer substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an acceleration sensor manufacturing substrate before and after anodically bonding a cover glass for protecting the surface of a sensor chip to a semiconductor wafer on which an acceleration sensor is formed, and a manufacturing method thereof.

  A silicon substrate and an SOI (Silicon On Insulator) wafer are used as a wafer substrate for manufacturing an acceleration sensor chip.

  In the method using a silicon substrate, a metal layer is formed on a portion of the silicon substrate in contact with the cover glass, and the metal layer is conducted from the wiring to the silicon substrate through the diffusion layer, and between the silicon substrate and the cover glass. A voltage is applied to perform anodic bonding (see Patent Documents 1 and 2). The method assumes that the anodic bonding electrode terminal for anodic bonding is taken from the back side of the silicon substrate.

  The SOI wafer is composed of an active layer, an intermediate layer, and a support layer in this order from the wafer surface side. In the method using an SOI wafer as a wafer substrate for manufacturing an acceleration sensor chip, since the intermediate layer is an insulating film, an anodic bonding electrode terminal for anodic bonding of the surface protective cover glass on the active layer side is taken from the back side of the wafer. There is a problem that can not be. Therefore, it is necessary to take the anodic bonding electrode terminal for anodic bonding from the wafer surface side. However, when the anodic bonding electrode terminal is to be formed on the surface side, the contact area with the anodic bonding apparatus side terminal can be secured sufficiently. These terminals or terminal patterns must be formed on the wafer surface separately from the acceleration sensor chip.

  Therefore, in the conventional method, in order to secure the anodic bonding electrode terminal exposed on the wafer surface side, the shape of the cover glass is such that a part of the outer peripheral portion of the wafer does not cover the wafer. In order to ensure a sufficient contact area with the terminal, it may be small and stable anodic bonding may not be performed.

One proposed method uses an SOI wafer in which the active layer is formed to have a diameter smaller by several mm than the support layer, and the intermediate oxide film is exposed in a ring shape on the outer peripheral portion on the surface side of the support layer. It is. There, the thermal oxide film on the back side of the support layer of the SOI wafer is removed, and the support layer is exposed by removing the intermediate oxide film by performing cutting, polishing and etching processes from the active layer side on the outer periphery of the SOI wafer. Then, a metal film is coated from the active layer side, and the active layer and the support layer are electrically connected by the metal film to form an anodic bonding electrode terminal for anodic bonding. By performing such processing, it is possible to prevent destruction of the intermediate oxide film during anodic bonding, and to perform anodic bonding with glass on both surfaces of the wafer (see Patent Document 3).
Japanese Patent No. 3433570 JP 2000-249718 A Japanese Patent No. 3578028

  The first object of the present invention is to be able to stably anodize the surface protective cover glass regardless of whether a silicon wafer or an SOI wafer is used as the wafer substrate, or to stabilize the surface protective cover glass. It is another object of the present invention to provide an acceleration sensor manufacturing substrate that is anodically bonded.

  The proposed method using an SOI wafer can collectively perform anodic bonding with glass on both surfaces of the wafer, but requires an anodic bonding electrode terminal forming process in addition to the sensor chip forming process. The additional processing of the substrate itself for forming the electrode for anodic bonding is not preferable from the viewpoint of cost.

  The second object of the present invention is to simplify the process of manufacturing the substrate for manufacturing an acceleration sensor of the present invention and to facilitate contact with the anodic bonding apparatus side terminal, that is, to ensure a sufficient contact area. Therefore, it is possible to form an anodic bonding electrode terminal having a size suitable for the anodic bonding apparatus side terminal, and to make the anodic bonding electrode terminal conductive with the anodic bonding pattern in the sensor chip. It is an object of the present invention to provide a manufacturing method capable of forming an anodic bond.

  In order to achieve the first object, an acceleration sensor manufacturing substrate of the present invention includes a wiring lower layer insulating film, a wiring layer, and a wiring upper layer on the surface of a wafer substrate on which an acceleration sensor element including a piezoresistor is formed on the surface side. An acceleration sensor manufacturing substrate on which an insulating film is formed, wherein the wiring lower layer insulating film includes an opening for acceleration sensor connection, an internal electrode pattern for anodic bonding disposed in an internal region where the acceleration sensor chip is disposed, and The wiring layer is patterned to have at least an anodic bonding internal electrode opening for connecting the wafer substrate and an anodic bonding electrode terminal opening for connecting the anodic bonding electrode terminal and the wafer substrate, and the wiring layer has the acceleration Via a wiring pattern for an acceleration sensor connected to an acceleration sensor element through an opening for sensor connection, and through the opening for an anodic bonding internal electrode The anodic bonding internal electrode pattern connected to the substrate and the anodic bonding internal electrode pattern are not connected on the wiring lower layer insulating film and contact the wafer substrate through the anodic bonding electrode terminal opening. At least an anodic bonding electrode terminal pattern extending to the outer peripheral edge of the wafer substrate, and the wiring upper layer insulating film has a thickness that does not hinder the anodic bonding of the cover glass to the wafer substrate surface side, and the anodic bonding The electrode terminal pattern is patterned so as to have an opening that exposes at least a portion that can be connected to a terminal of an anodic bonding apparatus.

  The anodic bonding electrode terminal is in contact with the wafer substrate through the anodic bonding electrode terminal opening, and is connected to the anodic bonding internal electrode in the internal region through the wafer substrate. In anodic bonding, a voltage is applied from the anodic bonding electrode terminal to the anodic bonding internal electrode through the wafer substrate.

  The anodic bonding electrode terminal opening is disposed in the peripheral region. A region where the acceleration sensor chip is not formed on the outer peripheral portion of the wafer substrate is referred to as a peripheral region.

The substrate for manufacturing an acceleration sensor of the present invention includes a substrate on which a cover glass for protecting the surface of the acceleration sensor chip is bonded by anodic bonding.
The wafer substrate may be a silicon substrate, but it is an SOI wafer that exhibits the features of the present invention more effectively. In the SOI wafer, an active layer is formed on a support layer via an insulating intermediate layer.

The manufacturing method of the present invention for achieving the second object includes the following steps (A) to (F) in that order.
(A) A piezoresistor is formed on the wafer substrate surface, and an acceleration sensor element up to a stage where an uppermost wiring layer, a wiring lower layer insulating film thereunder, and a wiring upper layer insulating film on the wiring layer are not yet formed Forming step,
(B) a wiring lower layer insulating film forming step of forming the wiring lower layer insulating film on the wafer substrate surface;
(C) An anode for patterning the wiring lower-layer insulating film to connect the internal electrode pattern for anodic bonding disposed in the internal region where the acceleration sensor connection opening and the acceleration sensor chip are disposed to the wafer substrate A wiring underlayer insulating film patterning step for forming at least a bonding internal electrode opening, and an anodic bonding electrode terminal opening for connecting the anodic bonding electrode terminal and the wafer substrate;
(C) a film forming process for forming a metal layer on the wafer substrate surface;
(D) The metal layer is patterned and connected to an acceleration sensor wiring pattern connected to an acceleration sensor element through the acceleration sensor connection opening, and connected to a wafer substrate through the anode junction internal electrode opening. The anodic bonding internal electrode pattern, and the anodic bonding internal electrode pattern are not connected on the wiring lower layer insulating film and contact the wafer substrate through the anodic bonding electrode terminal opening, and the outer peripheral edge of the wafer substrate. A metal layer patterning process for forming at least an anodic bonding electrode terminal pattern extending to
(E) a wiring upper layer insulating film forming step for forming the wiring upper layer insulating film to a thickness that does not interfere with the anodic bonding of a cover glass to the wafer substrate surface side on the wafer substrate surface; and (F) the wiring upper layer. A wiring upper layer insulating film patterning step of patterning an insulating film to form an opening having a size that can be connected to at least a terminal of an anodic bonding apparatus among the anodic bonding electrode terminal patterns.

  In the step (D), the anodic bonding electrode terminal pattern is formed at the time of wafer peripheral exposure processing included in the photolithography process for forming the acceleration sensor wiring pattern, or the photo for forming the acceleration sensor wiring pattern. It can be formed simultaneously with the wiring pattern for the acceleration sensor in the lithography process.

  The acceleration sensor manufacturing substrate of the present invention includes an anodic bonding electrode terminal pattern that contacts the wafer substrate through the anodic bonding electrode terminal opening and extends to the outer peripheral edge of the wafer substrate, and is formed on the anodic bonding electrode terminal pattern. Since the wiring upper layer insulating film has an opening of a size that can be connected to at least the terminal of the anodic bonding apparatus among the anodic bonding electrode terminal patterns, the anodic bonding electrode terminal pattern is disposed on the outer peripheral portion of the wafer substrate. The size and position of the bonding electrode terminal pattern can be set such that the bonding electrode terminal pattern can be connected to the anodic bonding apparatus side terminal with a sufficient contact area, and the stability of anodic bonding is increased.

  Since the anodic bonding electrode terminal contacts the wafer substrate through the anodic bonding electrode terminal opening and is connected to the anodic bonding internal electrode through the wafer substrate, the anodic bonding electrode terminal can be applied to the SOI substrate to which no anodic bonding voltage can be applied from the back side. Can also be applied.

  Also, since the anodic bonding electrode terminal and the anodic bonding internal electrode are not directly connected, there is no need to leave a wiring metal in the dicing line between chips, and the wiring metal film adheres to the dicer blade during dicing. It is possible to reduce problems such as a decrease in cutting performance due to the operation.

  In the manufacturing method of the present invention, the anodic bonding electrode terminal pattern is formed of the same metal layer as the acceleration sensor wiring pattern, which simplifies the process of manufacturing the acceleration sensor manufacturing substrate and prevents the cost increase and the manufacturing period extension. it can.

  Since the anodic bonding electrode terminal pattern is arranged on the outer peripheral portion of the wafer substrate, the size and position of the anodic bonding electrode terminal can be easily changed by a combination of the peripheral exposure technique, the mask layout, and the pattern layout. Less susceptible to shape restrictions.

  Further, since the anodic bonding electrode terminal is partially formed on the outer peripheral portion, it is possible to avoid a problem that foreign matter is generated when the clamp of the etching apparatus contacts the resist during etching.

  If the anodic bonding electrode terminal pattern is formed during the wafer peripheral exposure process included in the photolithography process when forming the wiring pattern for the acceleration sensor, the anode can be accurately adjusted in mm by the peripheral exposure apparatus recipe setting. The shape and arrangement position of the bonding electrode terminal can be freely set.

  In addition, if the anodic bonding electrode terminal pattern is formed at the same time as the acceleration sensor wiring pattern in the photolithography process when forming the acceleration sensor wiring pattern, the accuracy of the mask layout setting is further improved than the peripheral exposure. The shape and arrangement position of the anodic bonding electrode terminal can be set with an accuracy of μm.

(Example 1 of substrate)
3A and 3B show an acceleration sensor manufacturing substrate according to an embodiment.
The wafer substrate 1 may be a silicon substrate or an SOI substrate, but here, an SOI substrate is used. An acceleration sensor element including a piezoresistor 3 is formed on the surface side of the wafer substrate 1. On the surface of the wafer substrate 1, a wiring lower layer insulating film 4, a wiring layer 6, and a wiring upper layer insulating film 11 are formed.

  The wafer substrate 1 is roughly divided into a peripheral region (c) and an inner region (a) inside thereof. Among the internal regions, the region shown as (b) is a region where the anodic bonding electrode terminal pattern 6c formed in the peripheral region (c) extends, and the piezoresistor 3a is also formed in the region (b). However, since the piezoresistor 3a does not function as an acceleration sensor element, the region (b) is a dummy region and is not included in the internal region.

  The wiring lower layer insulating film 4 includes an acceleration sensor connection opening 5a, an anode bonding internal electrode opening 5b for connecting the internal electrode pattern 6b for anodic bonding disposed in the inner region and the wafer substrate 1, and an anodic bonding electrode. It is patterned so as to have an opening 5c for an anodic bonding electrode terminal for connecting the terminal 8 and the wafer substrate 1.

  The wiring layer 6 includes an acceleration sensor wiring pattern 6a connected to the acceleration sensor element via the acceleration sensor connection opening 5a, and an anodic bonding inside connected to the wafer substrate 1 via the anodic bonding internal electrode opening 5b. The electrode pattern 6b and the anodic bonding internal electrode pattern 6b are not connected on the wiring lower layer insulating film 4, and come into contact with the wafer substrate 1 through the anodic bonding electrode terminal opening 5c to the outer peripheral edge of the wafer substrate 1. An extending anodic bonding electrode terminal pattern 6c. The anodic bonding electrode terminal opening 5c is arranged in a region (b) inside the peripheral region (c).

  The wiring upper layer insulating film 11 has a thickness that does not interfere with the anodic bonding of the cover glass 22 to the surface of the wafer substrate. The thickness is, for example, 1.0 to 1.5 μm. Further, the wiring upper layer insulating film 11 is patterned so as to have an opening exposing at least a size that can be connected to the terminal of the anodic bonding apparatus in the anodic bonding electrode terminal pattern 6c. A portion of the wiring layer 6 exposed in the opening of the wiring upper layer insulating film 11 becomes the anodic bonding electrode terminal 8.

  The inner boundary of the peripheral opening of the wiring upper layer insulating film 11 is indicated by reference numeral 12, and the width of the peripheral opening is uniform at the outer periphery of the wafer. However, as shown in FIG. 4, the width of the peripheral opening of the wiring upper layer insulating film 11 is wide in the vicinity of the anodic bonding electrode terminal 8 and is narrower in the other peripheral portions. You can also Reference numeral 17 denotes an inner boundary of the peripheral opening. Thus, by widening the peripheral exposure width in the vicinity of the anodic bonding electrode terminal 8, connection with the terminal of the anodic bonding apparatus is facilitated.

  This embodiment shows the acceleration sensor manufacturing substrate in a state where the cover glass 22 for protecting the surface of the acceleration sensor chip is not bonded, but for manufacturing the acceleration sensor in which the cover glass 22 is bonded by anodic bonding. A substrate is also included as an embodiment of the invention.

(Example 1 of manufacturing method)
A first embodiment of the method for manufacturing the first embodiment of the substrate will be described with reference to FIGS. 1 to 3, (A) is a plan view and (B) is a cross-sectional view taken along the line AA ′.

  The manufacturing method of this example is an example in which it is not necessary to remove the wiring lower layer insulating film on the outer periphery of the wafer before forming the wiring metal film, and the patterning of the wiring lower layer insulating film and the metal film thereon is performed. In this method, sequential exposure processing and peripheral exposure processing are used as lithography for this purpose. This is also an embodiment in which the number of shots with the wiring pattern on the wafer needs to be smaller than the number of shots with the wiring lower layer insulating film opening pattern.

(1) Patterning of wiring lower layer insulating film (FIGS. 1A and 1B)
A piezoresistor 3 is formed on the surface of the wafer substrate 1. The steps so far are performed by a known method.

  Thereafter, a wiring lower layer insulating film 4 is formed. As the wiring lower layer insulating film 4, a BPSG film, an SOG film or the like is deposited to a thickness of 0.5 to 1.0 μm. A resist layer is formed on the wiring lower layer insulating film 4, and the resist layer is patterned by a photolithography technique. For the exposure for patterning, sequential exposure by reduced projection exposure is performed using a reticle of 3 chips × 3 chips per shot. Reference numeral 2 indicates 3 chips × 3 chips exposed in one shot. At this time, it is not necessary to perform peripheral exposure processing on the outer periphery of the wafer. The hatched area is an unexposed area. After the exposure, a developing process and a rinsing process are performed to form a resist pattern, and the wiring lower layer insulating film 4 is etched using the resist pattern as a mask, whereby the acceleration sensor connecting opening 5a and the acceleration are formed in the wiring lower layer insulating film 4. An anodic bonding internal electrode opening 5b for connecting the internal electrode pattern for anodic bonding arranged in the internal region where the sensor chip is arranged and the wafer substrate 1 and the anodic bonding electrode terminal and the wafer substrate 1 are connected. An opening 5c for anodic bonding electrode terminals is formed. The boundary region between the chips is a region that becomes a dicing line when separating into individual acceleration sensor chips. The wiring lower layer insulating film 4 in the boundary region that becomes the dicing line is also removed in this patterning step.

(2) Wiring pattern formation (FIGS. 2A and 2B)
A wiring metal film is formed on the entire surface of the wafer substrate 1 by a PVD technique such as sputtering. As the metal film for wiring, an Al—Si alloy film, an Al—Si—Cu alloy film or the like is deposited to a thickness of 0.5 to 1.0 μm.

  Thereafter, a resist layer is formed on the metal film, and the resist layer is patterned by a photolithography technique. As exposure for patterning, sequential exposure by reduced projection exposure is performed using a reticle of 3 chips × 3 chips per shot. In this exposure, the outer peripheral portion of the wafer is formed so that the portion that finally becomes the anodic bonding electrode has a structure that is electrically connected to the wafer substrate 1 through the anodic bonding electrode terminal opening 5c opened in the opening step. The sensor chip wiring pattern is not exposed at several places (several shots) (the hatched portions in FIG. 2A) where the acceleration sensor connection openings 5a are present. By doing so, the opening 5 c of the wiring lower layer insulating film 4 becomes a connection portion to the wafer substrate 1. Further, the bonding electrode area of the wafer substrate 1 at the time of anodic bonding increases, and an improvement in bonding strength can be expected. However, if the number of portions (shots) (the hatched portions in FIG. 2A) is increased excessively, the wafer substrate Since the number of effective chips per sheet decreases, it is necessary to select an appropriate number of points (shots).

  Thereafter, peripheral exposure processing is performed on the outer peripheral portion of the wafer. The exposure width is such that the terminal on the anodic bonding apparatus side can be connected, and the portion 8 serving as the anodic bonding electrode terminal is not exposed and the other peripheral portion of the wafer is exposed. A boundary indicated by reference numeral 9 in FIG. 2A indicates the innermost side of the peripheral area subjected to peripheral exposure. The position to be the anodic bonding electrode terminal is determined in consideration of the shape of the cover glass and the ease of taking the electrode from the anodic bonding apparatus. In addition, since the photoresist remains in the portion 8 which becomes the anodic bonding electrode terminal after development, a clamp or the like is in contact with the etching until the etching of the wiring metal film and the removal of the photoresist are completed. If there is a concern about the occurrence of a defect such as the generation of foreign matter, the peripheral exposure is performed so that the anodic bonding electrode terminal 6c is formed at a position not in contact with the clamp or the like. A portion indicated by reference numeral 10 in FIG. 2A is a contact portion with the clamp at the time of etching.

  Thereafter, a wiring pattern 6 is formed by development and etching techniques. Thus, the acceleration sensor wiring pattern 6a connected to the acceleration sensor element through the acceleration sensor connection opening 5a and the anodic bonding internal electrode connected to the wafer substrate 1 through the anodic bonding internal electrode opening 5b. The pattern 6b and the anodic bonding internal electrode pattern 6b are not connected on the wiring lower layer insulating film 4, but come into contact with the wafer substrate 1 through the anodic bonding electrode terminal opening 5c and extend to the outer peripheral edge of the wafer substrate 1. A wiring pattern 6 including the anodic bonding electrode terminal pattern 6c is formed. In the wiring metal film patterning step, the wiring metal film in the boundary region that becomes the dicing line is also removed.

  The example of FIG. 2A shows an example in which the anodic bonding electrode terminal 6c is formed on the right side of the wafer substrate 1 when the orientation flat (a portion cut flat around the periphery of the wafer substrate) is viewed downward. However, the present invention is not particularly limited to this example.

(3) Opening of wiring upper layer insulating film pattern (FIGS. 3A and 3B)
As the wiring upper layer insulating film 11, a thin oxide film that does not hinder the anodic bonding of the wafer and glass is formed on the entire surface of the wafer substrate after the wiring pattern 6 is formed by heat treatment or CVD technology. As the wiring upper layer insulating film 11, a SiO ₂ film or the like is deposited to a thickness of 1.0 to 1.5 μm.

  Thereafter, a resist layer is formed on the wiring upper layer insulating film 11, and the resist layer is patterned by a photolithography technique. A reticle is used as exposure for patterning, and the sensor chip pattern is sequentially exposed by reduced projection exposure. Here, the wiring upper layer insulating film 11 in the boundary region that becomes a dicing line between chips in the inner region is also removed in this patterning step. In this step, a portion (shot) that is not exposed when the wiring pattern is formed (a portion that is hatched in FIG. 3A) may or may not be exposed.

  Thereafter, peripheral exposure processing is performed on the outer peripheral portion of the wafer. The exposure width is a width at which the outer peripheral portion of the wiring pattern 6c is exposed and becomes the anodic bonding electrode terminal 8, and is a width that can be connected to the terminal on the anodic bonding apparatus side. The exposure location may be only in the vicinity of the portion where the anodic bonding electrode terminal 8 is formed, or may be the entire outer peripheral portion of the wafer substrate 1. However, since the resist remains in the unexposed portion after development, in order to avoid the resist remaining on the contact portion 13 with the clamp at the wafer outer periphery during etching, the entire wafer outer periphery is exposed. Is good. In the case of exposing the entire outer peripheral portion of the wafer, it is preferable to set the exposure width so that the underlying wiring metal film is not exposed after the oxide film etching except for the anodic bonding electrode terminal 8 during the oxide film etching. It is possible to prevent a product (furyl) generated by exposure to an etching gas from being generated from the outer periphery of the wafer. Further, in the peripheral exposure, it is not necessary to make the exposure width in the vicinity of the anodic bonding electrode terminal 8 and other portions the same.

  Formation of a resist pattern by development processing and pattern opening processing by etching of an oxide film using the resist pattern as a mask are performed to expose the outer peripheral portion of the wiring pattern 6 c to form the anode bonding electrode terminal 8.

Here, an example is shown in which the peripheral exposure width is uniform at the outer periphery of the wafer as indicated by reference numeral 12 at the inner boundary of the peripheral exposure width.
On the other hand, the form shown in FIG. 4 shows an example in which the peripheral exposure width is wide in the vicinity of the anodic bonding electrode terminal 8 and narrower in the other peripheral portions. Reference numeral 17 denotes an inner boundary of the peripheral exposure width. Thus, by widening the peripheral exposure width in the vicinity of the anodic bonding electrode terminal 8, connection with the terminal of the anodic bonding apparatus is facilitated.

(Example 2 of manufacturing method)
A second embodiment of the method for manufacturing the first embodiment of the substrate will be described with reference to FIGS.
The manufacturing method of this embodiment is also an embodiment in which it is not necessary to remove the wiring lower layer insulating film on the outer periphery of the wafer before forming the wiring metal film, but in this embodiment, the wiring lower layer insulating film and the metal film thereon In this method, batch exposure processing is performed as lithography for patterning, and peripheral exposure processing is not performed. Further, like the first embodiment of the manufacturing method, the number of shots with the wiring pattern on the wafer needs to be smaller than the number of shots with the wiring lower layer insulating film opening pattern.

(1) Patterning of wiring underlayer insulating film (FIG. 5)
As in the first embodiment of the manufacturing method, a piezoresistor is formed on the surface of the wafer substrate 1, and then a wiring lower layer insulating film is formed.

  A resist layer is formed on the wiring lower layer insulating film, and the resist layer is patterned by a photolithography technique. As the exposure for patterning, the sensor chip pattern is collectively exposed with a mask.

  Thereafter, a pattern opening process using a development process and an etching technique is performed. FIG. 5 shows a state in which the wiring lower layer insulating film is patterned, and each of the square areas indicated by reference numeral 14 shows an area that finally becomes a sensor chip. The cross-sectional shape of the portion indicated by AA ′ in FIG. 5 is the same as that in FIG. 1B of the first embodiment of the manufacturing method.

(2) Wiring pattern formation (FIG. 6)
A wiring metal film is formed on the entire surface of the wafer substrate 1 by a PVD technique such as sputtering.

  Thereafter, a resist layer is formed on the metal film, and the resist layer is patterned by a photolithography technique. As exposure for patterning, the sensor chip pattern is collectively exposed with a mask. A boundary indicated by reference numeral 16 indicates a boundary between a peripheral region where there is no wiring pattern other than the anodic bonding electrode terminal 8 and an internal region where the wiring pattern is formed. In several places (several chips 15) where there are sensor chip opening patterns on the outer periphery of the wafer, a portion that finally becomes an anodic bonding electrode is electrically connected to the wafer substrate through the sensor chip opening pattern opened in the opening process. In order to achieve this, not a sensor chip wiring pattern but a mask laid out so that the metal film becomes a wiring pattern remaining on the entire surface of those chips is used. By doing in this way, the wiring lower layer insulating film opening pattern becomes a connection location to the wafer substrate 1. Also, the bonding electrode area on the wafer substrate 1 side during anodic bonding is increased, and an improvement in bonding strength can be expected. However, if the number of chips (chips) is excessively increased, the number of effective chips per wafer is reduced. It is necessary to select the correct number of points (chips). On the mask, a pattern that becomes the anodic bonding electrode terminal 8 is laid out on the outer periphery of the wafer. The width of the pattern serving as the anodic bonding electrode terminal 8 is set to a width that allows connection of the terminal on the anodic bonding apparatus side. The position where the electrode terminal is laid out on the mask is determined in consideration of the shape of the cover glass and the ease of taking the electrode from the anodic bonding apparatus.

  In addition, since the photoresist remains in the portion that becomes the anodic bonding electrode terminal, the clamp or the like comes into contact with the peripheral portion of the wafer until the etching of the wiring metal film and the removal of the photoresist are completed. If there is a concern about the occurrence of problems such as the occurrence of the above, the position of the clamp or the like is also taken into consideration, and the anodic bonding electrode terminal pattern is laid out at a position where it does not come into contact therewith.

  Thereafter, a development process and a wiring pattern forming process using an etching technique are performed. FIG. 6 shows a state after the wiring pattern is formed. A cross-sectional view taken along the line AA ′ in FIG. 6 is the same as FIG.

  Here, as in the first embodiment of the manufacturing method, an example in which the anodic bonding electrode terminal 8 is formed on the right side of the wafer substrate 1 with the orientation flat facing down is shown, but the present invention is not limited to this.

(3) Opening of wiring upper layer insulating film pattern (FIG. 7)
As in the first embodiment of the manufacturing method, a thin oxide film that does not hinder the anodic bonding of the wafer and glass to the entire surface of the wafer substrate after forming the wiring pattern is formed as a wiring upper layer insulating film by heat treatment or CVD technology. To do.

  Thereafter, a resist layer is formed on the wiring upper layer insulating film 7, and the resist layer is patterned by a photolithography technique. As exposure for patterning, the sensor chip pattern is collectively exposed with a mask. At this time, a mask laid out so that the anodic bonding electrode terminal of the wiring pattern is exposed with a width connectable with the terminal on the anodic bonding apparatus side after the opening of the oxide film is used in the outer peripheral portion of the wafer substrate 1. Thereafter, a resist pattern is formed by development processing, and pattern opening processing is performed by etching the oxide film using the resist pattern as a mask. FIG. 7 shows the state of etching, and the cross-sectional shape at the position of the AA ′ line in FIG. 7 is the same as that in FIG.

  Here, an example in which the peripheral exposure width is uniform at the outer periphery of the wafer is shown as the inner boundary of the peripheral area is indicated by reference numeral 12, but as shown in FIG. The width may be wide in the vicinity of the anodic bonding electrode terminal 8 and narrower in the other peripheral portions. When the width of the peripheral region is made different between the portion of the anodic bonding electrode terminal 8 and the other portion, a mask having a form as shown in FIG. 4 is used.

(Example 2 of substrate)
10A to 10C show an anodic bonding electrode terminal portion of a substrate for manufacturing an acceleration sensor according to another embodiment. (A) is a plan view of the portion, (B) is a cross-sectional view at the AA ′ line position, and (C) is a cross-sectional view at the BB ′ line position.

  The wafer substrate 1 may be a silicon substrate or an SOI substrate, but an SOI substrate is also used in this embodiment. An acceleration sensor element including a piezoresistor is formed on the surface side of the wafer substrate 1. On the surface of the wafer substrate 1, a wiring lower layer insulating film 4, a wiring layer 6, and a wiring upper layer insulating film 11 are formed.

  The wiring lower layer insulating film 4 has an opening for connecting an acceleration sensor (not shown), and an opening for an anodic bonding internal electrode (not shown) for connecting the anodic bonding internal electrode pattern arranged in the inner region to the wafer substrate 1. In the peripheral region, the anodic bonding electrode terminal 8 or the anodic bonding electrode and the anodic bonding electrode opening 5d for connecting the wafer substrate 1 are patterned.

  The wiring layer 6 includes an acceleration sensor wiring pattern (not shown) connected to the acceleration sensor element through the acceleration sensor connection opening, and an anodic bonding connected to the wafer substrate 1 through the anodic bonding internal electrode opening. The internal electrode pattern (not shown) and the anodic bonding internal electrode pattern are not connected on the wiring lower layer insulating film 4, and come into contact with the wafer substrate 1 through the anodic bonding electrode opening 5 d and the outer periphery of the wafer substrate 1. And an anodic bonding electrode terminal pattern 6c extending to the end.

  The wiring upper layer insulating film 11 has a thickness that does not interfere with the anodic bonding of the cover glass to the wafer substrate surface side. The wiring upper layer insulating film 11 is patterned so as to have an opening exposing at least a size that can be connected to the terminal of the anodic bonding apparatus among the anodic bonding electrode terminal pattern 6c. A portion of the wiring layer 6 exposed in the opening of the wiring upper layer insulating film 11 becomes the anodic bonding electrode terminal 8.

  This embodiment shows the acceleration sensor manufacturing substrate in a state where the cover glass for protecting the surface of the acceleration sensor chip is not bonded, but the acceleration sensor manufacturing substrate in which the cover glass is bonded by anodic bonding is also used. It is included as an example of the present invention.

(Example 3 of manufacturing method)
One embodiment of a method for manufacturing the second embodiment of the substrate will be described as a third embodiment with reference to FIGS. 8 to 10, (A) is a plan view, (B) is a sectional view at each AA ′ line position, and (C) is a sectional view at each BB ′ line position.

  The third embodiment is an embodiment in which the wiring lower layer insulating film on the outer periphery of the wafer is removed before forming the wiring metal film, and is sequentially used as a lithography for patterning the wiring lower layer insulating film and the metal film thereon. This is a method using an exposure process and a peripheral exposure process. Further, in this embodiment, the number of shots with the wiring pattern on the wafer need not be smaller than the number of shots with the wiring lower layer insulating film opening pattern.

(1) Opening of wiring lower layer insulating film pattern (FIGS. 8A, 8B, 8C)
As in the first embodiment of the manufacturing method, a piezoresistor is formed on the wafer substrate 1, and then a wiring lower layer insulating film 4 is formed.

  A resist layer is formed on the wiring lower layer insulating film 4, and the resist layer is patterned by a photolithography technique. As exposure for patterning, sequential exposure processing is performed by a reduction projection exposure method using a reticle.

  Thereafter, peripheral exposure processing is performed on the outer peripheral portion of the wafer. The exposure width is set such that the metal film and the wafer substrate can be sufficiently in contact with each other at the outer periphery of the wafer after the metal film for wiring is formed. A boundary indicated by reference numeral 18 is an inner boundary of the outer peripheral portion of the wafer.

  Thereafter, a pattern opening process using a development process and an etching technique is performed. FIG. 8A is a plan view of the vicinity of the anodic bonding electrode terminal forming portion in this state. In this figure, the left side is the wafer center direction and the right side is the wafer outer peripheral direction.

(2) Wiring pattern formation (FIGS. 9A, 9B, 9C)
A metal film for wiring is formed on the entire surface of the wafer substrate by PVD technology such as sputtering.

  Thereafter, a resist layer is formed on the metal film, and the resist layer is patterned by a photolithography technique. As exposure for patterning, the sensor chip pattern is sequentially exposed by reduction projection exposure using a reticle.

  Thereafter, peripheral exposure processing is performed on the outer peripheral portion of the wafer other than the portion serving as the anodic bonding electrode terminal. The peripheral exposure width other than the part that becomes the anodic bonding electrode terminal is the periphery in the wiring lower layer insulating film opening process so that the contact between the wiring metal film and the wafer surface substrate can be sufficiently taken in the peripheral part of the wafer after the wiring pattern etching. Set narrower than exposure width. The position to be the anodic bonding electrode terminal is determined in consideration of the shape of the cover glass and the ease of taking the electrode from the anodic bonding apparatus. In addition, since the photoresist remains in the portion serving as the anodic bonding electrode terminal, a clamp or the like is in contact with the outer periphery of the wafer until the etching of the wiring metal film and the removal of the photoresist are completed. When there is a concern about the occurrence of a defect such as the generation of foreign matter, the peripheral exposure is performed so as to form the anodic bonding electrode terminal at a position not in contact with the position of the clamp or the like.

  Thereafter, development processing is performed to form a resist pattern, and the wiring metal film is etched using the resist pattern as a mask to perform wiring pattern formation processing. A plan view of the vicinity of the anodic bonding electrode terminal forming portion in this state is shown in FIG.

(3) Opening of wiring upper layer insulating film pattern (FIGS. 10A, 10B, 10C)
A thin oxide film 11 that does not hinder the anodic bonding of the wafer and glass is formed on the entire surface of the wafer after the wiring pattern is formed by heat treatment or CVD technology.

  Thereafter, a resist layer is formed on the wiring upper layer insulating film 11, and the resist layer is patterned by a photolithography technique. A reticle is used as exposure for patterning, and the sensor chip pattern is sequentially exposed by reduced projection exposure.

  Thereafter, the outer peripheral portion of the wafer substrate 1 is subjected to peripheral exposure processing. The exposure width is set such that the anodic bonding electrode terminal 8 of the wiring pattern is exposed and the terminal on the anodic bonding apparatus side can be connected. The exposure location may be only near the anodic bonding electrode terminal 8 or the entire outer peripheral portion of the wafer substrate 1. However, since the resist remains in the unexposed part after development, in order to avoid the resist remaining in the contact portion with the clamp at the outer periphery of the wafer during etching, it is better to expose the entire outer periphery of the wafer. Good. When the entire outer periphery of the wafer substrate 1 is exposed, except for the anodic bonding electrode terminals 8, the exposure width should be such that the underlying wiring metal film is not exposed after the oxide film etching. It is possible to prevent a product (frill) generated by exposing the wiring metal film to the etching gas from the outer peripheral portion of the wafer. Further, in the peripheral exposure, it is not necessary to make the exposure width in the vicinity of the anodic bonding electrode terminal 8 and other portions the same.

  Thereafter, a pattern opening process using a development process and an etching technique is performed to expose the outer peripheral portion of the wiring pattern 6 c to form the anodic bonding electrode terminal 8. Here, an example in which the peripheral exposure width is uniform at the outer peripheral portion of the wafer is shown. The boundary indicated by reference numeral 12 indicates the inner boundary of the peripherally exposed region.

  On the other hand, the form shown in FIG. 11 shows an example in which the peripheral exposure width is wide in the vicinity of the anodic bonding electrode terminal 8 and narrower in the other peripheral portions. Reference numeral 17 denotes an inner boundary of the peripheral exposure width.

(Example 4 of manufacturing method)
Another embodiment of the method for manufacturing the second embodiment of the substrate will be described as a fourth embodiment. The drawings to be referred to are FIGS. 8 to 10 which are the same as those of the third embodiment.

  This Example 4 is also an example in which the wiring lower layer insulating film on the outer periphery of the wafer is removed before forming the wiring metal film, but the mask is used as lithography for patterning the wiring lower layer insulating film and the metal film thereon. This is a method of performing batch exposure using a pattern. Further, in this embodiment, the number of shots with the wiring pattern on the wafer need not be smaller than the number of shots with the wiring lower layer insulating film opening pattern.

(1) Opening of wiring lower layer insulating film pattern (FIGS. 8A, 8B, 8C)
As in the first embodiment of the manufacturing method, a piezoresistor is formed on the wafer substrate 1, and then a wiring lower layer insulating film 4 is formed.

A resist layer is formed on the wiring lower layer insulating film 4, and the resist layer is patterned by a photolithography technique. As the exposure for patterning, the sensor chip pattern is collectively exposed with a mask. At this time, a mask is used that is laid out so that an opening having a width that can be sufficiently in contact with the wafer surface substrate after the wiring metal film is formed on the outer periphery of the wafer.
Thereafter, patterning processing is performed by development processing and etching technology.

(2) Wiring pattern formation (FIGS. 9A, 9B, 9C)
A metal film for wiring is formed on the entire surface of the wafer substrate by PVD technology such as sputtering.

  Thereafter, the wiring pattern is collectively exposed by photolithography. At this time, a mask laid out so that the resist remains outside the opening of the wiring lower layer insulating film on the outer periphery of the wafer after development so that the contact between the wiring metal film and the wafer surface substrate is sufficient at the outer periphery of the wafer. Use. The width of the region where the resist remains outside the opening of the wiring lower layer insulating film is such that the photoresist remains after development, so that the metal is clamped on the outer periphery of the wafer until etching of the wiring metal film and removal of the photoresist are completed. If there is a concern about the occurrence of a defect such as a foreign object due to contact, the layout of the clamp and the like is taken into consideration so as not to contact it.

  Thereafter, development processing is performed to form a resist pattern, and the wiring metal film is etched using the resist pattern as a mask to perform wiring pattern formation processing. A plan view of the vicinity of the anodic bonding electrode terminal forming portion in this state is shown in FIG.

(3) Opening of wiring upper layer insulating film pattern (FIGS. 10A, 10B, 10C)
A thin oxide film 11 that does not hinder the anodic bonding of the wafer and glass is formed on the entire surface of the wafer after the wiring pattern is formed by heat treatment or CVD technology.

  Thereafter, the opening pattern of the wiring upper layer insulating film is collectively exposed by a photolithography technique. At this time, a mask is used that is laid out so that the portion that becomes the electrode end is exposed after the etching of the oxide film so that the wiring metal film is exposed and a width capable of connecting the terminal on the anodic bonding apparatus side can be secured. In addition, the layout of the outer peripheral portion other than the electrode ends has a defect due to a narrow area without resist on the outer peripheral portion, for example, a defect due to contact with a clamp on the outer peripheral portion of the wafer due to the resist remaining after development, and Problems due to widening of the exposed area of the wiring metal film, for example, the generation of a product (frill) generated by exposing the underlying wiring metal film to the etching gas when the oxide film is etched occurs at the outer periphery of the wafer. Appropriate to take into account defects.

  Thereafter, a pattern opening process using a development process and an etching technique is performed. A plan view of this state is shown in FIG.

  Also in this embodiment, the peripheral exposure width may be uniform at the outer peripheral portion of the wafer. As shown in FIG. 11, the peripheral exposure width is wide in the vicinity of the anodic bonding electrode terminal 8 and in the other peripheral portions, it is larger than that. You may make it narrow.

It is a figure which shows the patterning process of the wiring lower layer insulating film in 1st Example of a manufacturing method, (A) is a top view, (B) is sectional drawing in the AA 'line position. 4A and 4B are diagrams showing a wiring pattern forming process in the embodiment, where FIG. 5A is a plan view and FIG. It is a figure which shows the opening process of the wiring upper layer insulating film pattern in the Example, and is a figure which shows one Example of the board | substrate for acceleration sensor manufacture, (A) is a top view, (B) is the AA ' It is sectional drawing in a line position. It is a partial top view which shows the anode junction electrode terminal vicinity in the other Example of the board | substrate for acceleration sensor manufacture. It is a top view which shows the patterning process of the wiring lower layer insulating film in 2nd Example of a manufacturing method. It is a top view which shows the wiring pattern formation process in the Example. It is a top view which shows the opening process of the wiring upper layer insulating film pattern in the Example. It is a figure which shows the patterning process of the wiring lower layer insulating film in 3rd Example of a manufacturing method, (A) is a top view, (B) is sectional drawing in the AA 'line position, (C) is It is sectional drawing in the BB 'line position. It is a figure which shows the wiring pattern formation process in the Example, (A) is a top view, (B) is sectional drawing in the AA 'line position, (C) is the BB' line position. It is sectional drawing. It is a figure which shows the opening process of the wiring upper-layer insulating film pattern in the Example, and is a figure which shows the further another Example of the board | substrate for acceleration sensor manufacture, (A) is a top view, (B) is the A- Sectional view at the A 'line position, (C) is a sectional view at the BB' line position. It is a partial top view which shows the anode junction electrode terminal vicinity in the further another Example of the board | substrate for acceleration sensor manufacture.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer substrate 2 Piezoresistor 4 Wiring lower layer insulating film 6 Wiring layer 5a Acceleration sensor connection opening 5b Anodic bonding internal electrode opening 5c Anodic bonding electrode terminal opening 6a Acceleration sensor wiring pattern 6b Anode bonding internal electrode pattern 6c anodic bonding electrode terminal pattern 8 anodic bonding electrode terminal 11 wiring upper layer insulating film 12, 17 inner boundary of peripheral opening

Claims (9)

In the acceleration sensor manufacturing substrate in which the wiring lower layer insulating film, the wiring layer and the wiring upper layer insulating film are formed on the surface of the wafer substrate on which the acceleration sensor element including the piezoresistor is formed on the surface side,
The wiring lower layer insulating film includes an opening for acceleration sensor connection, an opening for anodic bonding internal electrode for connecting an internal electrode pattern for anodic bonding disposed in an internal region where the acceleration sensor chip is disposed, and a wafer substrate, and It is patterned to have at least an opening for an anodic bonding electrode terminal that connects the anodic bonding electrode terminal and the wafer substrate,
The wiring layer includes an acceleration sensor wiring pattern connected to an acceleration sensor element through the acceleration sensor connection opening, and an anodic bonding internal electrode pattern connected to a wafer substrate through the anodic bonding internal electrode opening. And the anodic bonding internal electrode pattern are not connected on the wiring lower layer insulating film, and contact the wafer substrate through the anodic bonding electrode terminal opening and extend to the outer peripheral edge of the wafer substrate. Including at least a pattern,
The wiring upper layer insulating film has a thickness that does not interfere with the anodic bonding of the cover glass to the wafer substrate surface side, and has a size that can be connected to at least a terminal of the anodic bonding apparatus among the anodic bonding electrode terminal patterns. A substrate for manufacturing an acceleration sensor, wherein the substrate is patterned so as to have an opening that exposes a portion of the acceleration sensor.   The acceleration sensor manufacturing substrate according to claim 1, wherein the anodic bonding electrode terminal opening is disposed in a peripheral region.   The acceleration sensor manufacturing substrate according to claim 1, wherein a cover glass for protecting the surface of the acceleration sensor chip is bonded to the surface of the acceleration sensor manufacturing substrate by anodic bonding.   4. The acceleration sensor manufacturing substrate according to claim 1, wherein the wafer substrate is an SOI wafer in which an active layer is formed on a support layer via an insulating intermediate layer. 5. A method for manufacturing a substrate for manufacturing an acceleration sensor, comprising the following steps (A) to (F) in that order:
(A) A piezoresistor is formed on the wafer substrate surface, and an acceleration sensor element up to a stage where an uppermost wiring layer, a wiring lower layer insulating film thereunder, and a wiring upper layer insulating film on the wiring layer are not yet formed Forming step,
(B) a wiring lower layer insulating film forming step of forming the wiring lower layer insulating film on the wafer substrate surface;
(C) An anode for patterning the wiring lower-layer insulating film to connect the internal electrode pattern for anodic bonding disposed in the internal region where the acceleration sensor connection opening and the acceleration sensor chip are disposed to the wafer substrate A wiring underlayer insulating film patterning step for forming at least a bonding internal electrode opening, and an anodic bonding electrode terminal opening for connecting the anodic bonding electrode terminal and the wafer substrate;
(C) a film forming process for forming a metal layer on the wafer substrate surface;
(D) The metal layer is patterned and connected to an acceleration sensor wiring pattern connected to an acceleration sensor element through the acceleration sensor connection opening, and connected to a wafer substrate through the anode junction internal electrode opening. The anodic bonding internal electrode pattern, and the anodic bonding internal electrode pattern are not connected on the wiring lower layer insulating film and contact the wafer substrate through the anodic bonding electrode terminal opening, and the outer peripheral edge of the wafer substrate. A metal layer patterning process for forming at least an anodic bonding electrode terminal pattern extending to
(E) a wiring upper layer insulating film forming step for forming the wiring upper layer insulating film to a thickness that does not interfere with the anodic bonding of a cover glass to the wafer substrate surface side on the wafer substrate surface; and (F) the wiring upper layer. A wiring upper layer insulating film patterning step of patterning an insulating film to form an opening having a size that can be connected to at least a terminal of an anodic bonding apparatus among the anodic bonding electrode terminal patterns.   After the step (F), a cover glass is placed on the surface of the wafer substrate, a terminal of an anodic bonding apparatus is connected to the exposed portion of the anodic bonding electrode terminal pattern, and a voltage is applied between the cover glass and the anodic bonding electrode terminal. The manufacturing method according to claim 5, wherein a bonding step of applying and bonding the cover glass to the wafer substrate surface side by anodic bonding is performed.   The manufacturing method according to claim 5, wherein the wafer substrate is an SOI wafer in which an active layer is formed on a support layer via an insulating intermediate layer.   8. The anodic bonding electrode terminal pattern in the step (D) is formed during wafer peripheral exposure processing included in a photolithography step when forming the acceleration sensor wiring pattern. Production method.   The anodic bonding electrode terminal pattern in the step (D) is formed at the same time as the acceleration sensor wiring pattern in a photolithography step when the acceleration sensor wiring pattern is formed. Production method.

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