JP2002014663A - Image display preprocessing device and image display device - Google Patents

Abstract

(57) Abstract: In an image display preprocessing apparatus having a frame memory for storing input image data before format conversion, data I / O of the frame memory is provided.
When image data having a narrower bus width is input, a part of the bus width of the data I / O is not used, so that the capacity of the frame memory cannot be effectively used. SOLUTION: Input image data is temporarily stored by a first bus width conversion unit 11, and then stored in a frame memory 1.
It is converted to a bus width of 2 and output to the frame memory 12. The invalid data generated at this time is transmitted to the frame memory 12 by the CKE signal for stopping the internal operation of the frame memory.
Not stored in The image data stored in the frame memory 12 is transferred to the second bus width conversion unit 1 while maintaining the converted bus width.
3 and temporarily stored, and then restored to the bus width of the original image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying input image data, and in particular, temporarily stores the image data in a frame memory before performing a conversion process into a format suitable for image display. The present invention relates to an image display preprocessing device and an image display device.

[0002]

2. Description of the Related Art In recent years, in a display device used for displaying an image such as a computer and a television, a plasma display panel (hereinafter, referred to as "P") has been developed.
DP ”. ) Is attracting attention as a display device that can be large, thin, and lightweight.

[0003] The PDP is a display device having a so-called dot matrix structure in which a plurality of pixels are arranged on a panel, and displays an image by lighting a pixel to be lit according to a received image signal. However, the received image signal is not in a signal format suitable for PDP, for example,
Since the signal form is suitable for a raster scan system such as a CRT, it is necessary to convert the format of the image signal so as to match the number of pixels of the panel. Therefore, in order to guarantee the format conversion operation at the subsequent stage, P
The DP display device temporarily stores the received image signal in a frame memory at a previous stage.

[0004] As the frame memory, those having a data I / O bus width of 32 bits are generally used, which are generally supplied relatively inexpensively among the memories. On the other hand, the image data input to the frame memory is usually 24 bits wide, and the frame memory is 32 bits wide.
Of the data I / Os, upper 8 bits are invalidated, and image data is temporarily stored using lower 24 bits.

[0005]

However, in the above prior art, the bus width of the input image data (24
bit) is the bus width of data I / O of the frame memory (3
Since the area is smaller than 2 bits, an unused area is generated in the frame memory, and there is a problem that the capacity of the frame memory cannot be effectively used. Therefore, when handling high-resolution image data with a large data amount,
Although relatively inexpensive, the number of frame memories must be increased, and an increase in cost is inevitable.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an image display preprocessing device and an image display device that can effectively utilize the capacity of a frame memory.

[0007]

In order to achieve the above object, an image display preprocessing apparatus according to the present invention comprises a frame memory for storing input image data before converting the image data into a format suitable for image display. A first bus width conversion circuit that converts a first bus width that is a data bus width of the image data into a second bus width that is a bus width of the frame memory, and writes the second bus width into the frame memory; A second bus width conversion circuit that reads out the image data written in the frame memory, restores the image data to a first bus width, and outputs the first bus width, and the first bus width conversion circuit, the second bus width conversion circuit, And a control circuit for outputting a control signal for controlling the operation timing of the frame memory. As a result, the input image data is converted from the first bus width to the second bus width, and when read from the frame memory, is restored from the second bus width to the first bus width. The bus width and capacity of the memory can be used effectively.

More specifically, the first bus width conversion circuit includes a write data holding register group having a bit number corresponding to the least common multiple of the first bus width and the second bus width.
The control circuit controls the write data holding register group to sequentially enable registers for the number of bits corresponding to the first bus width in synchronization with a clock, and stores the activated image data in the registers. A write data storage control circuit section and registers of the number of bits corresponding to the second bus width are sequentially enabled in synchronization with a clock from the write data holding register group, and an image stored in the enabled register is stored in the enabled register. A write data output control circuit for outputting data to the frame memory.

Here, the write data storage control circuit performs control for validating the register of the first bus width every clock, and the write data output control circuit controls all the write data holding registers in the write data holding register group. When the register is activated once, control for providing a pause period during which one register is not activated for one clock may be performed. As a result, it is possible to sequentially convert the width of image data that is continuously input and write the converted image data to the frame memory.

Further, the second bus width conversion circuit comprises a first bus width conversion circuit.
A read data holding register group having a bit number corresponding to the least common multiple of the bus width of the second bus width and the second bus width;
A read data storage control circuit for sequentially enabling registers of the number of bits corresponding to the bus width of the bus in synchronization with the clock, and performing control to store image data of the same number of bits from the frame memory in the enabled registers; The register of the number of bits corresponding to the first bus width is sequentially enabled in synchronization with a clock from the read data holding register group, and control is performed to output image data stored therein from the enabled register. A read data output control circuit section.

[0011] Here, the read data storage control circuit section activates all the registers in the read data holding register group at one time, and sets a pause period during which no register is activated for one clock. The read data output control circuit unit performs
The control for enabling the register having the bus width of may be performed every clock. This makes it possible to sequentially convert the image data written in the frame memory to the bus width and restore the original image data. Specifically, the first bus width is 24 bits, and the second bus width is 24 bits. If the bus width is 32 bits, it is generally used and is preferable.

Further, the same clock is used for a clock for storing image data in the write data holding register group and the read data holding register group and a clock for outputting image data from the register group. It is characterized by. Normally, different clock pulses are used before and after the bus width conversion because a difference in data speed occurs. However, the same clock can be used in the image display preprocessing device according to the present invention. There is no need to provide a device for generation.

The image display device according to the present invention is an image display device provided with a frame memory for storing input image data before converting the image data into a format suitable for image display. A first bus width conversion circuit for converting the first bus width to the second bus width and writing the frame data to the frame memory; and reading the image data written to the frame memory with the second bus width. , A second bus width conversion circuit for restoring the first bus width and outputting the same, and control for controlling operation timings of the first bus width conversion circuit, the second bus width conversion circuit, and the frame memory And a control circuit for outputting a signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an image display device according to the present invention will be described with reference to the drawings. <Overall Configuration of PDP Display Device> FIG.
FIG. 2 is a circuit block diagram illustrating a configuration of a DP display device.

As shown in FIG. 1, the PDP display device displays a memory unit 10, an image processing unit 20, a subfield conversion unit 30, a subfield conversion table 40, an image conversion unit 50, and an image. PDP (not shown). The memory unit 10 delays input image data for format conversion, and includes a first bus conversion unit 11, a frame memory 12, a second bus conversion unit 13, and a memory control unit 14. .

The first bus width conversion unit 11 is, for example, a red (R), green (G), blue (B) input from the outside.
Image data having a data bus width of a total of 24 bits quantized to 8 bits for each color of
The data is converted to a bus width of / O and output to the frame memory 12. The frame memory 12 has a data I / O of 32 bits
It has a width and a storage capacity for one frame, and has a storage area for storing input image data every 32 bits. Then, after sequentially storing the 32-bit width image data output from the first bus width conversion unit 11,
The second bus width converter 13 reads the data in units of 32 bits.

The second bus width converter 13 sequentially converts the 32-bit image data read from the frame memory 12
Image processing unit 2 by restoring the original 24-bit image data
Output to 0. The memory control unit 14 controls the operation timing of the first bus width conversion unit 11, the frame memory 12, and the second bus width conversion unit 13 so that a series of operations is performed smoothly.

The image processing unit 20 converts the image data output from the memory unit 10 into a known format so as to conform to the number of pixels of the PDP panel. For example, when converting the number of pixels in one line from A to B (A <B) according to the number of pixels of the PDP, pixel interpolation processing such as weighted average interpolation is performed, and conversely, the number of pixels in one line is changed to B When converting from A to A, the data is converted into a format according to the number of pixels of the PDP by performing pixel thinning processing such as weighted average thinning, and the image data is output to the subfield conversion unit 30. Subfield converter 3
0 converts the format-converted image data into write data expressed by the luminance weight of the subfield with reference to the subfield table 40 for each pixel data. In a PDP, a driving method called a so-called time-division in-frame display method is generally employed to display multiple gradations. One frame is divided into a plurality of subfields, and lighting in each subfield is performed. / Gray out is combined to express an intermediate gradation. for that reason,
The brightness weighting makes it possible to express an intermediate gradation.

The subfield table 40 stores a well-known table in which values to be converted are associated with each gradation value of image data (for example, Japanese Patent Laid-Open No. 11-2318).
No. 24). The image conversion unit 50 converts the write data converted by the subfield conversion unit 30 into the time-division in-frame gradation display method, and outputs the converted data to the PDP.

The PDP has a known configuration having a drive circuit for lighting a discharge cell to be turned on, and drives the drive circuit in accordance with input image data to display an image. <Configuration of Memory Unit 10> Next, the configuration of the first bus width conversion unit 11 and the second bus width conversion unit 13 specific to the present embodiment in the configuration of the memory unit 10 will be described.

(1) Configuration of First Bus Width Converter 11 First, the configuration of the first bus width converter 11 will be described.
FIG. 2 is a circuit diagram showing a configuration of the first bus width converter 11. For convenience of explanation, the registers 111, 112, 1
13, the register units R1 to R12 are sequentially arranged for each of the register units divided into 8 bits.
And numbered.

As shown in FIG. 1, the first bus width conversion unit comprises:
Three registers 111, 112, and 113 are provided, and the output circuits of the registers 111 to 113 are configured to be connected in parallel. The input circuit of each of the registers 111 to 113 includes three register units R1-R4-R7-
R10, R2-R5-R8-R11, R3-R6, R9
The same data line is connected to -R12.

Each of the registers 111 to 113 has 3
Register units R1 to R4 and register units R5 to R each having a 2-bit width and divided into 8 bits
8, a memory control unit 1 that includes register units R9 to R12 and receives image data having a 24-bit data bus width quantized into 8 bits for each of red, green, and blue.
In accordance with the control of No. 4, the data is temporarily stored in a predetermined register unit, converted to a bus width of 32 bits, which is the bus width of the data I / O of the frame memory 12, and sequentially output.

Here, the memory control unit 14 applies a write enable signal (hereinafter, referred to as a WE signal) and an output enable signal (hereinafter, referred to as an OE signal) to each of the register units R1 to R12 at the timing shown in FIG. )) To each of the register units R1 to R12,
The image data is written and output in synchronization with each of the WE and OE signals.

FIG. 3 is a timing chart showing a write and output operation in each of the register units R1 to R12 for explaining how to convert image data from a 24-bit bus width to a 32-bit bus width. In addition,
For convenience of explanation, the clock CLK is numbered in chronological order.
(1) to (12) are shown. First, the clock CL
At K (1), the WE signal to the register units R1 to R3 rises,
Bit image data is latched in the register units R1 to R3.

At the clock CLK (2), the WE signal for the register units R4 to R6 rises, and in synchronization with this, the 24-bit image data is similarly latched by the register units R4 to R6. Clock CLK
In (3), W for register units R7 to R9
Similarly, in synchronization with the rise of the E signal, the image data is latched by the register units R7 to R9, and the OE signal to the register units R1 to R4 rises. At this time, the data is latched in the register units R1 to R6, and the 32-bit image data A1 latched in the register units R1 to R4 is output to the frame memory 12 in synchronization with the rising signal.

At the clock CLK (4), 24-bit image data is latched and the OE signal to the register units R5 to R8 rises in synchronization with the rise of the WE signal to the register units R10 to R12. At this time, the register units R5 to R5
Data is latched up to R9, and the 32-bit image data A2 of the register units R5 to R8 is output to the frame memory in synchronization with the rise.

At the clock CLK (5), the WE signal to the register units R1 to R3 rises again, and the image data is latched in synchronism with the rise in the same manner as described above, and the register units R9 to R1
2 rises. At this point, the data is latched in the register units R9 to R12, and the register units R9 to R12 are synchronized with this rising.
, The 32-bit image data A3 latched is output.

Next, at the clock CLK (6), the WE signal to the register units R4 to R6 rises again and the image data is latched again as described above.
Since the OE signal for any of the registers does not rise, no image data is output, and thus invalid data indicated by oblique lines is generated. Normally, when bus width conversion is performed on image data, a difference occurs between the data speed before conversion and the data speed after conversion, so that different clock pulses are used before and after conversion. By the generation, the difference in data rate can be absorbed even if clocks of the same rate are used before and after the conversion.

Thereafter, the same operation is repeated, and the clock C
LK (7), (8), (9)
After generating 3, invalid data is generated at the clock CLK (10). Further, such an operation is sequentially repeated for the input image data. Here, the CKE signal for stopping the internal operation of the frame memory 12 is sent to the memory controller 1.
4 and output to the frame memory 12 so that this CKE signal is Low when the clock rises.
, The invalid data for one clock is not written in the frame memory 12.

By performing such an operation, the input image data is converted to be equal to the bus width of the frame memory, and the invalid data generated during the conversion is not written to the frame memory. Image data can be written so as to effectively utilize the capacity of the memory. (2) Configuration of Second Bus Width Converter 13 Next, the second bus width converter 13 will be described.

FIG. 4 is a circuit diagram showing a configuration of the second bus width converter 13. For convenience of explanation, the register 13
Of the register units 1, 132 and 133, register units divided into 8 bits are sequentially numbered and shown as register units R21 to R32. As shown in the figure, the second bus width conversion unit includes three registers 13
1, 132 and 133, and the input circuits of the registers are connected in parallel. The output circuit of each register includes every third register unit R21-R24.
-R27-R30, R22-R25-R28-R31,
The same data line is connected to R23-R26-R29-R32.

Each of the registers 131 to 133 has 3
Register units R21 to R24 and register unit R2 having a 2-bit width and divided into 8 bits
5 to R28, and register units R29 to R32,
32, which is the bus width of the data I / O of the frame memory 12
After the image data is read from the frame memory 12 with a bit width, the image data is restored to the original 24-bit image data and output.

Here, the memory control unit 14 sends the W to each of the register units R21 to R32 at a predetermined timing.
An E signal and an OE signal are supplied to cause each of the register units R21 to R32 to write and output image data in synchronization with each of the WE and OE signals. FIG. 5 is a diagram illustrating each of the register units R21 to R21 for explaining how the image data is restored from 32 bits to the original bus width of 24 bits.
9 is a timing chart showing a write and output operation in R32. For convenience of explanation, clocks CLK are numbered (1) to (12) in chronological order and have the same clock frequency as the clock CLK in FIG.

First, at the clock CLK (1), the WE signal for the register units R21 to R24 rises, and the 32-bit image data A1 is latched by the register units R21 to R24 in synchronization with the rise. Proceed to clock CLK (2) and register unit R2
5 to 3 in synchronization with the rising edge of the WE signal for R28
The 2-bit image data A2 is stored in the register units R25 to R25.
R28 and the register unit R2
Register units R21 to R23 that have already been latched in synchronization with the rise of the OE signal for
Of image data having a width of 24 bits.

At the clock CLK (3), the 32-bit width image data A3 is latched by the register units R29 to R32 in synchronization with the rise of the WE signal to the register units R29 to R32, and the OE signal to the register units R24 to R26. Stand up. At this point, the register units R24 to R24 have already been registered.
Data is latched up to 28, and the 24-bit image data latched by the register units R24 to R26 is output in synchronization with the rise of the OE signal.

In the clock CLK (4), no writing is performed because the WE signal does not rise, but the data is already latched in the register units R27 to R32 and the OE for the register units R27 to R29 has been latched.
The register units R27 to R27 are synchronized with the rise of the signal.
Image data having a width of 24 bits of R29 is output. At the clock CLK (5), the register unit R2
The WE signals to 1 to R24 rise, the image data B1 is latched by the register units R21 to R24 in the same manner as described above in synchronization with the rise, and the OE signal to the register units R30 to R32 rises to synchronize with this rise. Register unit R3
The 24-bit image data already latched at 0 to R32 is output.

Thereafter, the same operation is repeated, and 32 bits
The image data having the width is sequentially restored to the original image data having the 24-bit width. The image data is converted into the write data by the subfield conversion unit 30 and then output to the image conversion unit 50. Note that the CKE signal is generated in the memory control unit 14 and output to the frame memory 12, so that the CKE signal is Lo at the rising of the clock.
In the case of the position w, it is arranged not to output new image data to each register unit for one clock after one clock. By performing such an operation, the image data is sequentially restored from the bus width of the frame memory to the original bus width.

With the above-described configuration, image data input with a 24-bit width is converted into 32-bit image data, so that the bus width of the data I / O of the frame memory 12 can be used effectively and this conversion can be performed. The invalid data generated on the way is not written into the frame memory by the CKE signal. When image data is read from the frame memory 12, the data is read with the 32-bit width, and then the original 24-bit width is converted by the second bus width conversion unit 13.
It is possible to sequentially restore image data having a width.

Therefore, unlike the prior art, the data I is stored without invalidating the upper 8 bits of the frame memory.
/ O can be effectively used, and the frame memory capacity can be effectively used. <Structure of Image Conversion Unit 50> Next, the image conversion unit 50 that converts image data to the intra-frame time division gray scale display method will be described.

FIG. 6 is a circuit diagram for explaining the configuration of the image conversion unit 50. The image conversion unit 50 includes two frame memories 510 and 520, a write circuit 530, a read circuit 540, and a frame memory switching control circuit 550.
Consists of The frame memories 510 and 520 have a storage area for each subfield, and the storage area of each subfield has a capacity to store binary data for the number of pixels of the plasma display panel.

The write circuit 530 includes a write buffer memory 531, a write operation control circuit 532, and bus control circuits 533 and 534. In addition, a write-only operation clock is used as the operation clock, and the phase assurance circuit 535 is provided due to this. The write buffer memory 531 includes two line memories, and under the control of the write operation control circuit 532, the subfield unit 3
The write data input from 0 is alternately written to the two line memories in synchronization with the operation clock, and the image data is transferred from the line memory where the writing has been completed to the operation clock in the opposite phase. , And the image data is written line by line to the frame memory 510 (520) to which writing is permitted by the bus control circuits 533 and 534 and the control signal switching circuit 550. One frame memory 510 (52
When the image for one frame has been written in 0), the control signal switching circuit 550 switches the frame memory,
Writing of image data to the other frame memory 520 (510) is started.

The read circuit 540 includes the input selection circuit 54
1, read buffer 542, read operation control circuit 5
43 is provided. In addition, a read-only operation clock is used as the operation clock, and the phase assurance circuit 544 is provided due to this. Under the control of the read operation control circuit 543, the input selection circuit 5
41 reads out image data.

The reading performed by the input selection circuit 541 is as follows.
This is performed in subfield units. That is, data belonging to the same subfield is read from all the lines in the frame memory from the image data written in the frame memory in synchronization with the operation clock. The read subfield data is sequentially stored in the read buffer 542, and when one line of subfield data has been stored, the subfield data is stored in a subsequent PDP (not shown).
Output to

The frame memory switching control circuit 550 includes a clock switching circuit 551 for switching an operation clock between writing and reading of the frame memories 510 and 520, and a chip select signal for selecting which frame memory to select. And the like, and control signal switching circuits 552 and 553 for switching in synchronization with the switching of the operation clock. In this embodiment, a blanking detection circuit 601 is provided in addition to the above circuits. This circuit 601 detects a vertical synchronizing signal of the received image data and generates a clock switching signal at the start of the retrace time.

(Structure peculiar to the present embodiment) The write operation clock has a frequency of about 30 MHz, and the read operation clock has a frequency of about 53 MHz. The write operation clock is set to the above frequency based on the following calculation. For example, VGA wide (480 × 852
Pixel), the number of subfields is Sn = 12, the read cycle is Ta = 1.5 μs, and the write horizontal frequency is fh = 32 k
Hz, and the data bus width of the frame memory is 32 bits, the operation clock frequency fw at the time of writing becomes fw = fh * 852 * 3 * Sn / 32 = about 30 MHz. On the other hand, the operation clock frequency fr during reading
Is fr = (1 / Ta) * 852 * 3/32 = 53 MHz.

As the clock of this frequency, the dot clock used when processing the image signal on the upper stage side of the present circuit can be used as it is, or it is generated by extracting the horizontal synchronizing signal and multiplying it by frequency. You can do it. As the read operation clock, the one used conventionally is used. The phase assurance circuits 535 and 544 output the chip select (CS) signal among the control signals supplied to the frame memories 510 and 520 with the phase shown in FIG. 7B. As shown in FIG. 7 (d), the “Vali” includes a period in which the chip select (CS) signal is low, and a period of one clock cycle or more before and after the period.
This circuit guarantees the phase so as to maintain the d ”state.

Although not shown, this circuit counts, for example, a write operation clock and a read operation clock, and is reset by a CS signal. The counter reaches a count value “K1” corresponding to one clock cycle. Control signal other than the CS signal is changed from "Don't care" to "Valid" when the value "R-K1" is smaller than the reset value "R" by the count number corresponding to one clock cycle. Or a circuit for performing a process for reversing the CS signal, and a circuit for outputting the CS signal as it is.

As described above, since the control signals other than the CS signal are held at "Valid" for a period longer than the "Valid" period of the CS signal, even if the control signals other than the chip select (CS) signal are delayed. A margin for the setup and hold period of the clock can be secured. As a result, a delay adjustment circuit may be used only for the CS signal, and a high-speed operation of the frame memory can be guaranteed even if a clock switching circuit is added at a subsequent stage. FIG. 7A is a waveform diagram of a write or read operation clock, and FIG. 7C is a waveform diagram of a control signal other than the CS signal.

The control signal switching circuits 552 and 553 use the switching signal supplied from the blanking detection circuit 601 to control the control signal output from the write-side phase assurance circuit 535 and the control signal output from the read-side phase assurance circuit 544. Switch with signal. In this case, the two control signal switching circuits 552 and 553 are operated in reverse so that one selects the control signal output from the phase guarantee circuit 535 on the write side and the other selects the phase guarantee circuit 544 on the read side. Switching is performed based on the phase.

At the time of writing, the clock switching circuit 551
Although the write operation clock is supplied to the frame memory and the read operation clock is switched at the time of reading, in the present embodiment, since the write operation clock and the read operation clock are asynchronous, the switching is performed by one. The clock cycle is guaranteed. FIG. 8 shows a specific example of a clock switching circuit 551 that guarantees such clock switching. In the figure, TR and TW are flip-flops.
Write operation clock WCLK, read operation clock RCLK
Are output as switched clocks SGCLKA and SGCLKB through four AND circuits and two OR circuits. FIG. 9 is a waveform diagram illustrating the switching operation of the clock switching circuit 551. The illustrated example shows a case where the switching signal is issued at the timing of “A”. Then, the clock is switched by capturing the falling edge of the clock. In the case of switching from read to write, the read operation clock is stopped at the timing of “B”,
The output of the write operation clock is started at the timing “E”. If the timing is from writing to reading,
The write operation clock is stopped at the timing "C", and the output of the read operation clock is started at the timing "D". In either case, a period of one or more clock cycles is secured for switching. The clock SGCLKA output from the clock switching circuit 551 is supplied to the frame memory 510, and SGCLKB is supplied to the frame memory 520.

(Operation of Image Converter 50) According to the above configuration, image data is written in the write buffer 530 line by line in synchronization with the dot clock.
The image data written to the write buffer 530 is read and written to the frame memory 510 (520) selected by the bus control circuits 533 and 534.
The writing speed to the frame memory at this time is determined by the writing operation clock. In the case of the present embodiment, since the speed is as low as about 30 MHz and the same speed as the dot clock, writing is performed using almost the entire period in which one frame memory is selected on the writing side.

On the other hand, at this time, the remaining frame memories 5
From 20 (510), the image data is sequentially read from one subfield selected by the input selection circuit 541, and is output to the subsequent plasma display panel driving circuit (not shown) through the read buffer 542.
At this time, the reading speed from the frame memory is:
It is as fast as about 53 MHz.

One for each frame memory 510, 520
When the writing and reading of the image data for the frame are completed, the frame memories 510 and 520 are switched by the operations of the bus control circuits 533 and 534, the control signal switching circuits 552 and 553, and the clock switching circuit 551.
The writing operation is performed on the frame memory 520 (510) from which the reading is completed, and the reading operation is performed on the frame memory 510 (520) from which the writing is completed. In this switching, although the write operation clock and the read operation clock are asynchronous, the clock switching circuit 551 switches the clocks while guaranteeing at least one clock period. Is performed even immediately after the switching.

As described above, the image conversion unit 50 for the intra-frame division gray scale display method writes the image data into the frame memory in a time-series manner for each line, and converts the image data from the frame memory to the weight data. Since the frequency of the operating clock is changed when reading divided data, use the high-speed clock required for reading, and use the low-speed clock for writing image data using the entire writing period during writing. As a result, the restrictions on high-frequency operation are eased for the write-side circuit, the degree of freedom in design is increased, and the circuit cost is reduced. The clock frequency is reduced compared to when a high-speed read operation clock is used as the write operation clock. Amount corresponding power consumption was also heating value is reduced, the stability of operation, reduction of energy loss is effective such realized.

In the image conversion section 50 of the above embodiment, two frame memories are used. However, three or more frame memories are used, and image data is written and read out by using these frame memories in order. You can do it. In the embodiment, the switching of the clock in the image conversion unit 50 is performed during the vertical blanking period. However, this is a normal operation in which the horizontal scanning is repeatedly performed while the vertical scanning is performed once. If image data captured by a scanning method in which vertical scanning is repeated while horizontal scanning is performed once is targeted, the clock signal is output during the horizontal blanking period. Switching may be performed.

In this embodiment, a PDP has been described as an example of an image display device. However, the present invention is not limited to this, and the present invention is applicable to a case where an image is displayed on an image display device requiring format conversion. can do. Further, in the present embodiment, the bus width of the input image data has been described as 24 bits and the bus width of the data I / O of the frame memory 12 has been described as 32 bits. If registers having the bus width of the data I / O are provided in the first and second bus width converters by the number of values obtained by dividing the least common multiple of the bus width by the bus width of the data I / O of the frame memory, It is possible to cope with other bus widths.

[0058]

As described above, according to the image display pre-processing apparatus of the present invention, a frame memory for storing input image data before converting it into a format suitable for image display, A first bus width conversion circuit that converts a first bus width, which is a data bus width of data, into a second bus width, which is a bus width of the frame memory, and writes the converted data into the frame memory; A second bus width conversion circuit for reading out the written image data, restoring the read image data to a first bus width, and outputting the first bus width, the first bus width conversion circuit, the second bus width conversion circuit, and a frame memory And a control circuit for outputting a control signal for controlling the operation timing of the image data, the input image data is converted from the first bus width to the second bus width, and the frame data is converted. When reading from the memory, the second bus width is restored to the first bus width. As a result, a state in which a part of the bus width and the capacity of the frame memory is not used as in the related art is eliminated, and the capacity of the frame memory is reduced. Can be effectively used, and even when handling high-resolution image data having a large data amount, there is no need to provide an unnecessary frame memory, which is advantageous in terms of cost.

According to the image display preprocessing device of the present invention, the clock for storing the image data in the write data holding register group and the read data holding register group and the clock for outputting the image data from the register group are provided. Since the same clock can be used for any of the above clocks, there is no need to use different clock pulses corresponding to the difference in data speed before and after the bus width conversion, which is seen in the normal bus width conversion. In addition, there is an effect that it is not necessary to provide a device for newly generating a clock.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PDP display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a first bus width conversion unit.

FIG. 3 is a timing chart for explaining an operation of a first bus width conversion unit.

FIG. 4 is a circuit diagram showing a configuration of a second bus width conversion unit.

FIG. 5 is a timing chart for explaining an operation of a second bus width conversion unit.

FIG. 6 is a block diagram illustrating a circuit of an image conversion unit.

FIG. 7 is a waveform chart for explaining an operation of the phase assurance circuit in FIG. 6;

FIG. 8 is a logic circuit diagram showing a specific example of a clock switching circuit.

FIG. 9 is a waveform diagram illustrating a clock switching operation of the clock switching circuit.

[Explanation of symbols]

Reference Signs List 10 memory unit 11 first bus width conversion unit 12 frame memory 13 second bus width conversion unit 14 memory control unit 20 image processing unit 30 subfield conversion unit 40 subfield conversion table 50 image conversion units 111, 112, 113, 131, 132,133
Registers 510, 520 Frame memory 530 Write circuit 540 Read circuit 550 Frame memory switching control circuit 531 Write buffer memory 532 Write operation control circuit 533, 534 Bus control circuit 535, 544 Phase guarantee circuit 541 Input selection circuit 542 Read buffer 543 Read operation control Circuit 551 Clock switching circuit 552, 553 Control signal switching circuit 601 Blanking detection circuit

Claims (8)

[Claims] 1. A frame memory for storing input image data before converting it into a format suitable for image display, and a first bus width which is a data bus width of the image data.
A first bus width conversion circuit which converts the image data into the second bus width which is the bus width of the frame memory and writes the image data into the frame memory; A second bus width conversion circuit for restoring and outputting the width, and a control for outputting a control signal for controlling operation timing of the first bus width conversion circuit, the second bus width conversion circuit, and the frame memory An image display pre-processing device comprising: a circuit; 2. The first bus width conversion circuit includes a write data holding register group having a bit number corresponding to a least common multiple of a first bus width and a second bus width, and the control circuit includes: A write data storage control circuit unit for sequentially validating registers for the number of bits corresponding to the first bus width with respect to the write data holding register group in synchronization with a clock and storing image data in the activated registers. From the write data holding register group, sequentially activate the registers of the number of bits corresponding to the second bus width in synchronization with the clock, and output the image data stored therein from the validated registers to the frame memory. 2. A write data output control circuit section comprising:
The image display pre-processing device according to the above. 3. The write data storage control circuit section,
The control for validating the register having the first bus width is performed at every clock, and the write data output control circuit unit performs one clock for every register in the write data holding register group once. 3. The image display pre-processing device according to claim 2, wherein control is performed to provide a pause period during which no register is made valid. 4. The second bus width conversion circuit includes a read data holding register group having a bit number corresponding to a least common multiple of a first bus width and a second bus width, and the control circuit includes: Control for sequentially validating registers of the number of bits corresponding to the second bus width for the read data holding register group in synchronization with a clock, and storing the image data of the same number of bits from the frame memory in the activated registers And a read data storage control circuit unit for sequentially performing, from the read data holding register group, registers of the number of bits corresponding to the first bus width to be sequentially enabled in synchronization with a clock, and the enabled registers are stored therein. 4. An image table according to claim 1, further comprising: a read data output control circuit for controlling output of the image data. Pretreatment device. 5. The read data storage control circuit section,
When all the registers in the read data holding register group are enabled at one time, control is performed to provide a pause period during which no register is enabled for one clock, and the read data output control circuit unit 5. The image display pre-processing apparatus according to claim 4, wherein control for validating the register having the bus width of 2 is performed every clock. 6. The image display pre-processing apparatus according to claim 1, wherein the first bus width is 24 bits, and the second bus width is 32 bits. 7. A clock for storing image data in the write data holding register group and the read data holding register group and a clock for outputting image data from the register group are the same. The image display pre-processing device according to any one of claims 2 to 6, wherein: 8. An image display device comprising a frame memory for storing input image data before converting the image data into a format suitable for image display, wherein the image data is converted from the first bus width to the second bus width. A first bus width conversion circuit for converting the image data into the bus width and writing the image data into the frame memory; and reading out the image data written into the frame memory with the second bus width and restoring the image data to the first bus width. A first bus width conversion circuit, a second bus width conversion circuit, and a control circuit that outputs a control signal for controlling operation timing of a frame memory. An image display device characterized by the above-mentioned.