JPH06138868A - Display controller - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a display controller, and an object thereof is to realize a reduced display without changing the contents of the frame memory when the dual port memory is used as the frame memory. A display control device having a frame memory for storing a display image, a memory control circuit for reading display data from the frame memory in accordance with display scanning, and an output circuit for supplying the display data to the display device is read from the frame memory. A dual port line memory for storing the stored data and a line memory control unit are provided. The line memory control unit includes write control means for thinning out lines and respective pixels according to a display magnification when writing data read from the frame memory into the line memory, and decompressing lines and respective pixels according to the display magnification during reading from the line memory. It is configured to include a read control unit for performing the read operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for displaying the contents of a frame memory connected to a computer in an arbitrary size (reduction or enlargement). The present invention also relates to an extended display control device for superimposing and displaying a moving image on a video signal from the main display control device.

In recent years, display control of bit map display data is stored in a dual port memory type frame memory, and display control is performed. However, when the display data is reduced or enlarged, particularly when reduction is performed, software or hardware is used. Although the method is used, there are problems in terms of performance and cost, and its improvement is desired.

[0003]

2. Description of the Related Art FIG. 7 is a block diagram of Conventional Example 1, FIG. 8 is a diagram showing vertical timing of Conventional Example 1, and FIG. 9 is a block diagram of Conventional Example 2.

In FIG. 7, a CPU 70 is connected to a frame memory 72 for storing image data and a memory control section 73 by a bus 71. Display timing control unit 7
An output circuit 5 drives the memory control unit 73 to read the image data and outputs the image data read from the frame memory 72 to a display 76 such as a CRT.
The display timing of 4 is controlled.

The frame memory 72 is a dual port memory which has been adopted with the increase in the resolution of the display device, and the memory controller 7 controls the writing operation of the image data input from the device connected to the bus 71 such as the CPU 70.
Memory control unit 7
Sequential read operation by 3 is executed at the same time. With this configuration, reading of data for display and high speed access from the CPU 70 to the frame memory 72 during display are realized.

The vertical timing in the configuration of FIG. 7 is shown in FIG.
Shown in. As shown in Fig. 8, vertical sync signal (* VS is displayed, * represents negative logic), vertical blank signal (* VBL
In contrast to ANK), the data (RDT) read from the frame memory 72 is displayed on the display 76 via the output circuit 74 at substantially the same timing (DD).
Is output as T). Read data (R
At the same timing (including a slight delay) as the DT timing, each line data indicated by 1, 2, 3 ... (each line data displayed in horizontal scanning) is output from the output circuit 74 and displayed on the display 76. To be done.

The configuration of the first conventional example shown in FIG. 7 can cope with a case where data is generated a plurality of times such as enlargement, but when an image is reduced, it is possible to perform an operation that continuously requires data at distant addresses. Is not suitable because it is assumed to read sequentially like dual port memory.

FIG. 9 is a configuration diagram of the second conventional example. In this configuration, a high-speed RAM is used as the frame memory 77,
The display is performed by random access. When writing data from the CPU 70 side as in drawing, data can be input to the frame memory 77 by switching the gate circuit 78 of the data bus 79 connecting the frame memory 77 and the bus 71. When reading the data in the frame memory 77 to the display 76 for display, the frame memory 77 cannot be accessed from the CPU 70.

In this method, the processing for reducing the image is easily realized because it is a random access.

[0010]

When the frame memory of the dual port memory is used as in the above-mentioned conventional example 1 (FIG. 7), the reduction processing can be performed by software, but the processing takes time. It causes a drop in performance,
There is a problem that the circuit becomes complicated and the cost is increased when the reduction is realized by the high speed processing by the hardware.

Further, when the frame memory of the RAM is used as in the conventional example 2 (FIG. 9), access to the frame memory such as reading for display and reading for drawing competes with each other and only one side can access. There was a problem that performance deteriorated.

An object of the present invention is to provide a display control device which can realize reduced / enlarged display without changing the contents of the frame memory when the dual port memory is used as the frame memory.

[0013]

FIG. 1 is a basic configuration diagram of the present invention. In FIG. 1, 1 is a CPU, 2 is a dual port frame memory, 3 is a memory controller, 4 is a line memory composed of a dual port RAM, 5 is a line memory controller, 6 is a display timing controller, and 7 is The output circuit 8 is a display device such as a CRT display.
2 to 7 constitute a display control device.

The present invention realizes a reduced display by storing display data read from a frame memory in a line memory while thinning it according to a display magnification, and an enlarged display is realized by controlling reading from the line memory. Is.

[0015]

In FIG. 1, the CPU 1 to the frame memory 2
The writing and reading of the data to be displayed on the one side are executed under the control of the memory control unit 3 with one port meeting. Further, the image data is read from the other port of the frame memory 2 by the serial interface under the control of the memory control unit 3. A plurality of lines of the read image data are written in the line memory 4 under the control of the line memory control unit 5.

When performing a reduced display on the display device 8, the display timing control unit 6 generates a write control signal corresponding to the reduction ratio. That is, when writing the data for one line output from the frame memory 2 into one area of the line memory 4, a timing control signal for stopping the write address of the input pixel is generated according to the reduction ratio. As a result, the image data reduced by writing by the writing control means 50 of the line memory control unit 5 is written for one line, and the one line stored in the line memory 4 in the period preceding the period of the next horizontal synchronizing signal. Minute data is read from the output circuit 7 and a reduced image is displayed on the display device 8. Simultaneously with this reading, the data for the next one line is written in the other area of the line memory 4 while being reduced. For vertical reduction, writing is stopped according to the reduction ratio.

Next, when the enlarged display is performed, the display timing control unit 6 generates a control signal corresponding to the enlargement ratio. That is, the image data read from the frame memory 2 is written in the line memory 4 line by line as it is, and when read to the output circuit 7, the read address is stopped according to the enlargement ratio and a timing control signal for reading the same address is generated. To do. In response to this, the read control means 51 of the line memory control unit 5 reads out from the line memory 4 to output the enlarged image data to the display device 8 via the output circuit 7.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The CPU 1, frame memory 2, memory control unit 3, output circuit 7 and display device 8 shown in FIG. 1 are the same as in the conventional example, and the structure of the line memory and line memory control unit and the display timing control unit The generated control signal will be described below as an example.

FIG. 2 is a block diagram of the line memory and the line memory controller of the embodiment, FIG. 3 is a diagram showing the address allocation of the line memory, FIG. 4 is a diagram showing the vertical timing according to the present invention, and FIG. 5 is an embodiment. 6 is a timing chart of the control signal at the time of the reduced display and the data signal of each part, and FIG. 6 is a timing chart of the control signal at the time of the enlarged display of the embodiment and the data signal of each part.

In FIG. 2, 4 to 6 are the same as those in FIG. 1, 4 is a line memory composed of a dual port static RAM capable of simultaneously executing small-capacity reading and writing, 5 is a line memory controller, 6 is a display timing control unit. In the line memory control unit 5,
Reference numeral 5a is a write address generating circuit composed of a counter, 5b is a most significant address generating circuit for generating most significant bits of a write address and a read address of the line memory 4 composed of a T-type flip-flop, and 5c is a counter. And a read address generation circuit for the line memory 4. DCLK generated from the display timing control unit 6 is a data clock generated for each horizontal pixel data, * HS is a horizontal synchronizing signal of the display device (8 in FIG. 1), * LDEN is writing of pixel data to the line memory. * SOEN is a serial enable signal that controls reading of pixel data from the line memory.

First, read data (displayed by RDT) read from the frame memory (2 in FIG. 1) and input to the line memory 4 in FIG. 2, and output from the line memory 4 to the display device via the output circuit. The relationship of the vertical timing of the display data (displayed by DDT) according to FIG.
The relationship is as shown in.

That is, the vertical sync signal (* VS) and the vertical blank signal (* VBLANK) are generated in the same manner as in the prior art shown in FIG. 8, but the read data (RDT) is generated as shown in, and one line Minute image data is read and written in the line memory 4, and the display data (DDT) indicated by is read from the line memory 4 at a timing delayed by one line, and this display data (DDT) is output. The timing is synchronized with the vertical blank (* VBLANK). In this way, the image data is reduced and enlarged using the line memory 4 while being delayed by one line.

The basic operation of the line memory 4 shown in FIG. 2 will be described with reference to FIG. The line memory 4 is provided with an area A and an area B for storing image data for two lines as shown in FIG. 3, and the most significant bit of the head address of the area A is “0” and each of the lower bits. Each position in the area A is designated by the address bit, the most significant bit of the head address of the area B is "1", and each position in the area B is designated by each lower address bit, Address is assigned.

The most significant bit of the address is generated from the most significant address generation circuit 5b of the line memory control section 5, and when its output terminal Q is "0", this most significant bit "0".
And the lower address specified by the write address generation circuit 5a is the write address terminal (Wad) of the line memory 4.
Read data (RDT) from the frame memory is supplied to the data input terminal (Di
It is input from n) and written in the area A.

At this time, since the output terminal -Q of the highest address generating circuit 5b is "1", the area B is designated, and the highest address (bit) and the lower address generated by the read address generating circuit 5c are Since it is supplied to the read address terminal (Rad) of the line memory 4, the data in the corresponding area B is output to the data output terminal (Dout).
Is read as display data (DDT).

After that, when the highest-order address generation circuit 5b is inverted by the horizontal synchronizing signal (* HS) from the display timing control section 6, the output terminal Q becomes "1" and the output terminal -Q becomes "0". , Read data (RDT) is written in area B this time, and display data (D
DT) is read, and the display data is read one line after writing.

Next, the operation of the reduced display in FIG. 2 will be described with reference to FIG.
It will be described with reference to the timing chart shown in FIG. In FIG. 5, is DCLK, is a horizontal synchronization signal (* H
S), is a horizontal blank (* BLANK), is 1,
Read data 2 and 3 represent horizontal pixel data (R
DT) is a load enable signal (* LDEN) supplied to the write address generation circuit 5a, is display data (DDT), is a serial out enable signal (* SOEN) supplied to the read address generation circuit 5c.
Is.

FIG. 5 shows the timing when the reduction ratio of the reduced display is set to ⅔. In this case, the display timing control unit 6 outputs the load enable signal (*
LDEN) occurs. When the load enable signal is at the low level, the write address generating circuit 5a counts the data clock (DCLK) shown in
When the level is high, counting is prohibited and the previous count value is maintained. Therefore, the write address generation circuit 5
The address generated from a is input from the frame memory when a signal having a waveform as shown in is input 1, 2, 3
.., 1 and 2 are written to the addresses 1 and 2 of the area A of the line memory 4, but the pixel data of 3 is not written to the line memory 4 (or 3 to the address 2). (Pixel data is written in the overwrite format), the next pixel data of 4 and 5 is written to the addresses 3 and 4 of the area A, and the pixel data of 6 is not written. Thus, only two of the three are written,
Since the remaining one is not written, the reduction is ⅔.

The data in the area A of the line memory 4 is read by the read address generating circuit 5 when the highest address generating circuit 5b is switched by the next horizontal synchronizing signal.
It is read by the lower address from c. At this time, the read data (RDT) is written in the area B. Since the data in the area A is in the enabled state (low level) of the serial output enable signal shown in FIG. 5, the read address generation circuit 5c
Generates a corresponding read address by sequentially counting in accordance with the data clock (DCLK). In this case, since the reduction is performed at the time of writing,
.. are output as display data (DDT) according to the order of addresses.

Next, the operation for enlarged display will be described with reference to FIG. It should be noted that FIG. 6 is an example in the case of performing a 4/3 enlarged display, and each signal in FIG. 6 to is the same signal as in FIG.

Since the load enable signal (* LDEN) is at a low level, the read address of the frame memory is counted by the write address generation circuit 5a according to the data clock (DCLK) and written according to the lower address corresponding to each count value. Be done. For example,
When the writing to the area A is completed and the reading is started from the area A by the horizontal synchronizing signal, the serial output enable signal (* S
OEN) becomes high level once every three data clocks (DCLK) are generated. At this time, the read address generation circuit 5c stops counting, but since the read operation is continued, the same pixel data is displayed once every three (or four) times as the display data (DDT) as shown in FIG. It is read continuously. By performing the reading in this way, a 4/3 enlarged display is realized.

[0032]

According to the present invention, it is possible to efficiently change and display the display magnification without changing the image data in the dual port type frame memory in the bit map type display control device.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a line memory and a line memory control unit according to the embodiment.

FIG. 3 is a diagram showing address allocation of a line memory.

FIG. 4 illustrates vertical timing according to the present invention.

FIG. 5 is a timing chart of a control signal at the time of reduced display and a data signal of each part according to the embodiment.

FIG. 6 is a timing chart of a control signal and a data signal of each part at the time of enlarged display in the embodiment.

FIG. 7 is a configuration diagram of Conventional Example 1.

FIG. 8 is a diagram showing vertical timing in Conventional Example 1.

FIG. 9 is a configuration diagram of Conventional Example 2.

[Explanation of symbols]

 1 CPU 2 frame memory 3 memory control unit 4 line memory 5 line memory control unit 6 display timing control unit 7 output circuit 8 display device

Claims (1)

[Claims] 1. A display control device comprising: a dual port frame memory for storing a display image; a memory control unit for reading display data from the frame memory in accordance with a display scan; and an output circuit for supplying the display data to the display device. A dual port line memory connected to the frame memory for storing data read from the frame memory, and a line memory control unit for controlling writing and reading of the line memory, the line memory control unit comprising: Write control means for thinning lines and respective pixels according to a display magnification in writing the data read from the frame memory into a line memory, and read control for extending lines and respective pixels according to the display magnification in reading from the line memory And means Display controller.