JP2001274418A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a high-performance Schottky barrier diode that prevents an increase in parasitic capacitance and a reduction in reverse breakdown voltage. SOLUTION: A polycrystalline silicon layer 8 in which an impurity such as boron is introduced in advance is formed on the surface of an n ⁻ type semiconductor layer 4,
An opening 10b is provided in a region where a Schottky barrier is to be formed. A p ⁺ -type guard ring layer 11b is formed by thermal diffusion from the polycrystalline silicon layer 8, and an n ⁺ -type high-concentration cathode layer 13b is formed inside the semiconductor layer 4 by ion implantation from the opening 10b. A silicide layer 18e is formed. Since the p ⁺ -type guard ring layer 11b is determined in a self-aligned manner, it is possible to prevent the contact area with the semiconductor layer 4 from increasing due to a mask shift or the like, thereby preventing an increase in parasitic capacitance, and maintaining the position with the high-concentration cathode layer 13b. It is possible to suppress the reduction and the variation in the reverse breakdown voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a Schottky barrier diode (hereinafter, referred to as SBD) and a method of manufacturing the same.

[0002]

2. Description of the Related Art SBDs are used for high-frequency rectification circuits because of their high switching characteristics and low forward loss. Conventionally, an SBD has been manufactured as a single element, but by forming it on the same substrate as a bipolar transistor or a BiCMOS transistor, it is possible to realize element reduction and high-performance operation, and development is proceeding.

FIG. 6 shows a conventional example of the SBD. An n ⁺ -type (high-concentration n-type) buried diffusion layer 2 and an n ⁻ -type (low-concentration n-type) semiconductor layer 4 are formed on a semiconductor substrate 1.
To form A p ⁺ -type (high-concentration p-type) guard ring layer 11 is provided on the surface of the n ⁻ -type semiconductor layer 4 near the element isolation insulating film 6.
b is formed. Further, an n ⁺ -type cathode layer 13b is provided in the n ^-- type semiconductor layer 4 to reduce the resistance of the cathode region. n ⁻ type semiconductor layer 4 and p ⁺ type guard ring layer 1
1b, a refractory metal silicide layer 18e is formed on the surface of
An interlayer insulating film 17, a barrier metal 19, and a metal electrode 20 are formed.

Conventionally, the formation of the n ⁺ type cathode layer 13 b
Using a resist mask or the like, ions of phosphorus or the like are implanted into the n ⁻ -type semiconductor layer 4 between the high melting point metal silicide layer 18 e and the n ⁺ -type buried diffusion layer 2, and the p ⁺ -type guard ring layer 11 b The formation was performed by ion implantation of boron or the like using a resist mask or the like at a predetermined position on the periphery of the semiconductor layer 4 and the element isolation insulating film 6.

[0005]

However, in the above-described conventional manufacturing method, the position of the p ⁺ -type guard ring layer 11b is determined by the resist pattern. Then, the position of the p ⁺ -type guard ring layer 11b formed by ion implantation also shifts. Therefore, when the p ⁺ -type guard ring layer 11b is separated from the element isolation insulating film 6,
The contact area with the n ⁻ -type semiconductor layer 4 increases (part E in FIG. 7), causing an increase in parasitic capacitance and deteriorating high-frequency characteristics. Further, the high-concentration layers of the n ⁺ -type cathode layer 13b and the p ⁺ -type guard ring layer 11b come close to each other (portion F in FIG. 7), and the reverse breakdown voltage is reduced. .

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides a semiconductor device and a method for manufacturing the same, which can prevent an increase in parasitic capacitance and a decrease in reverse breakdown voltage due to misalignment of an SBD guard ring layer. The purpose is to do.

[0007]

In order to achieve this object, a semiconductor device according to a first aspect of the present invention includes a first conductive type semiconductor layer formed on a semiconductor substrate and an element region. And a second conductivity type polycrystal formed on the element isolation insulating film from the semiconductor layer around the element region to the element isolation insulating film formed on the semiconductor layer, and having an opening at the center of the element region. A silicon layer, a guard ring layer of the second conductivity type formed on the surface of the semiconductor layer immediately below the polycrystalline silicon layer, and a high concentration layer formed in the opening region of the polycrystalline silicon layer and inside the semiconductor layer and having a higher concentration than the semiconductor layer. It comprises a high-concentration cathode layer of the first conductivity type and a refractory metal silicide layer formed on the surface of the semiconductor layer in the opening region of the polycrystalline silicon layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first conductivity type semiconductor layer on a semiconductor substrate; and forming an element isolation insulating film on the semiconductor layer so as to surround the element region. Forming a polycrystalline silicon layer containing a second conductivity type impurity on the semiconductor layer and the element isolation insulating film, and selectively removing the polycrystalline silicon layer to form a semiconductor layer in a peripheral portion of the element region. Forming an opening in the center of the element region by leaving the element over the element isolation insulating film, and thermally diffusing the second conductivity type impurity contained in the remaining polycrystalline silicon layer. Forming a guard ring layer of the second conductivity type on the surface of the semiconductor layer immediately below the layer, and performing ion implantation through the opening of the polycrystalline silicon layer so that the first conductivity type having a higher concentration than the semiconductor layer is formed inside the semiconductor layer. High concentration It is intended to include a step of forming a cathode layer, and forming a refractory metal silicide layer on a semiconductor layer surface of the opening portion of the polycrystalline silicon layer.

According to the first and second aspects of the present invention,
Since the guard ring layer is formed by thermally diffusing the second conductivity type impurity from the polycrystalline silicon layer formed over the semiconductor layer around the element region and over the element isolation insulating film, the guard ring layer The position is determined in a self-aligned manner, and the second conductive type guard ring layer is not separated from the element isolation insulating film due to positional displacement as in the related art, and the junction area with the first conductive type semiconductor layer does not increase. An increase in parasitic capacitance can be prevented. Further, the position of the high-concentration cathode layer is determined in a self-aligned manner by the opening of the polycrystalline silicon layer, so that the positions of the guard ring layer and the high-concentration cathode layer can be stably maintained. Therefore, the risk that the high concentration layers come close to each other can be avoided, and the reduction and the variation in the reverse breakdown voltage can be prevented.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, the guard ring layer is formed by performing a high-temperature rapid heat treatment.

According to the third aspect of the present invention, the guard ring layer is formed by thermal diffusion from the impurity-containing polycrystalline silicon layer.
By performing a high-temperature rapid heat treatment such as aling), the junction can be made shallow, and the junction capacitance can be further reduced by making the junction shallow. Further, since the distance from the high-concentration cathode layer is increased, the reverse breakdown voltage can be improved.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which an SBD and a bipolar transistor are formed on the same semiconductor substrate, wherein the first conductive type is formed on the semiconductor substrate. A step of forming a semiconductor layer, a step of forming an element isolation insulating film on the semiconductor layer so as to surround each element region of the SBD and the bipolar transistor, and a step of forming a second conductivity type impurity on the semiconductor layer and the element isolation insulating film. A polycrystalline silicon layer including the polycrystalline silicon layer is deposited, and the polycrystalline silicon layer is selectively removed, so that the polycrystalline silicon layer is left over the semiconductor layer around the element region of the SBD from over the element isolation insulating film to the central part of the element region of the SBD. Forming an opening in a portion corresponding to a region where an intrinsic base layer is to be formed in the element region of the bipolar transistor at the same time as forming an opening in the bipolar transistor; By thermally diffusing the second conductivity type impurity contained in the silicon layer, a second conductivity type guard ring layer is formed on the surface of the semiconductor layer immediately below the polycrystalline silicon layer in the SBD element region, and at the same time, the element region of the bipolar transistor is formed. A second surface is formed on the surface of the semiconductor layer immediately below the polycrystalline silicon layer.
Forming a conductive type external base layer, and performing ion implantation through an opening in the polycrystalline silicon layer to form an SB.
A first conductivity type high-concentration cathode layer having a higher concentration than the semiconductor layer is formed inside the semiconductor layer in the D element region, and a first conductivity type having a higher concentration than the semiconductor layer is formed inside the semiconductor layer in the bipolar transistor element region. Forming a high-concentration collector layer, and forming a refractory metal silicide layer on the surface of the semiconductor layer at the opening of the polycrystalline silicon layer in the SBD element region.

According to the present invention, the guard ring layer and the high-concentration cathode layer of the SBD can be formed without adding a new process to the conventional bipolar process. can get.

According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor device according to the fourth aspect, the guard ring layer and the external base layer are formed by performing a high-temperature rapid heat treatment. It is characterized by the following.

According to the fifth aspect of the present invention, the guard ring layer and the external base layer are formed by thermal diffusion from the impurity-containing polycrystalline silicon layer.
By performing a high-temperature rapid heat treatment such as (Rapid Thermal Annealing), the junction of the guard ring layer and the semiconductor layer in the SBD can be made shallow, and the junction capacitance can be further reduced by making the junction shallow. Further, since the distance from the high-concentration cathode layer is increased, the reverse breakdown voltage can be improved.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an SBD according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate such as silicon, 2 denotes an n ⁺ -type buried layer, and a low-concentration n ⁻ -type semiconductor layer 4 is provided thereon. Reference numeral 6 denotes an element isolation insulating film formed on the surface of the semiconductor layer 4. Reference numeral 8 denotes a polycrystalline silicon layer provided on a portion of the semiconductor layer 4 and the element isolation insulating film 6 and doped with a p-type impurity in advance.
Is an insulating film. Reference numeral 11b is a p ⁺ -type guard ring layer formed by thermal diffusion from the polycrystalline silicon layer 8. An n ⁺ -type high-concentration cathode layer 13b is formed inside the n ⁻ -type semiconductor layer 4 immediately below the opening of the polycrystalline silicon layer 8, and the opening of the polycrystalline silicon layer 8 has a high melting point serving as a Schottky barrier metal. A metal silicide layer 18e is formed. The high concentration cathode layer 13b is for lowering the cathode resistance. Reference numeral 17 denotes an interlayer insulating film, 19 denotes a barrier metal such as TiN, and 20 denotes a metal electrode such as Al.

In FIG. 1, the region where the element isolation insulating film 6 is not formed is the element region A of the SBD, and the planar shape of the element region A is an island shape such as a circle, an ellipse, and a rectangle. The insulating film 6 is formed so as to surround the periphery of the island-shaped element region A. Then, the polycrystalline silicon layer 8
Is formed over the semiconductor layer 4 at the periphery of the element region A and over the element isolation insulating film 6, and the central part of the element region A is opened. The guard ring layer 11b is a polycrystalline silicon layer 8
Is formed by thermal diffusion of p-type impurities from the surface of the semiconductor layer 4 immediately below the polycrystalline silicon layer 8.
The high-concentration cathode layer 13b is formed substantially in the opening region of the polycrystalline silicon layer 8 and inside the semiconductor layer 4.
The portion of the high melting point metal silicide layer 18e formed on the surface of the semiconductor layer 4 in the opening of the polycrystalline silicon layer 8 becomes the anode region. The refractory metal silicide layer 18e includes a platinum silicide (PtSi, PtSi ₂ ) layer and a titanium silicide (TiS).
i ₂ ) layer and a silicide layer such as a molybdenum silicide (MoSi ₂ ) layer.

Next, a method of manufacturing the SBD will be described with reference to FIG. First, as shown in FIG. 2 (a), on a semiconductor substrate 1, after forming the n ⁺ -type buried layer 2 by thermal diffusion or the like, by epitaxial growth thereon n ^-
A type semiconductor layer 4 (for example, an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ and an epi-specific resistance of 1.2 Ω · cm) is formed, and an element isolation insulating film 6 is formed by LOCOS or the like.

Next, as shown in FIG. 2B, an impurity such as a polycrystalline silicon layer 8 such as boron is previously introduced into the surface of the semiconductor layer 4 and the element isolation insulating film 6 (for example, boron is 30 keV, Conductive doped polysilicon having a dose of 4 × 10 ¹⁵ cm ⁻² ) is deposited by CVD, and an insulating film 9 such as SiO ₂ is formed thereon by CVD. Then, the polycrystalline silicon layer 8 and the insulating film 9 are selectively removed by photolithography and dry etching techniques, and the opening 10b is formed on the surface of the semiconductor layer 4 at a position corresponding to the region where the refractory metal silicide layer is to be formed. To form Then, heat treatment (for example, 950)
(30 ° C., 30 minutes), the boron previously introduced into the polycrystalline silicon 8 is thermally diffused into the n ⁻ -type semiconductor layer 4 to be activated, and the p ⁺ -type guard ring layer 11b is activated.
(For example, an impurity concentration of 1 × 10 ²¹ cm ⁻³ ). Therefore, since the position of the guard ring layer 11b is determined in a self-aligned manner, the guard ring layer 11b is formed without leaving the peripheral edge of the element isolation insulating film 6.

Next, impurities such as phosphorus are introduced through the opening 10b.
(For example, phosphorus is 180 keV and the dose amount is 1.5).
× 10¹²cm^-2), Inside the semiconductor layer 4 immediately below the opening 10b
To n ⁺Type high-concentration cathode layer 13b (for example, an impurity concentration of 5
× 10¹⁶cm^-3) Is formed. This high concentration cathode layer 1
The position of 3b is also determined by the opening 10b of the polycrystalline silicon layer
Determined consistently and formed inside the low concentration semiconductor layer 4
You. The high concentration cathode layer 13b lowers the resistance of the cathode.
From the guard ring layer 11b.
It is also desirable to form it at a deep position.

Thereafter, as shown in FIG. 2C, an interlayer insulating film 17 such as a BPSG film or a TEOS film is deposited on the entire surface of the semiconductor layer 4, the element isolation insulating film 6 and the insulating film 9 by the CVD method. Then, a contact hole for forming the refractory metal silicide layer 18e is formed, and a refractory metal serving as a Schottky barrier metal is formed on the entire surface. Then, heat treatment such as lamp annealing is performed on the high melting point metal to selectively silicify only the high melting point metal located on silicon and polycrystalline silicon, and select an unreacted high melting point metal on the interlayer insulating film 17. High melting point metal silicide layer 1
8e are formed. The refractory metal silicide layer 18e formed on the surface of the semiconductor layer 4 becomes the anode region of the SBD,
A Schottky junction is formed between the refractory metal silicide layer 18 e and the relatively low concentration n ⁻ -type semiconductor layer 4.

Thereafter, as shown in FIG. 2D, a barrier metal 19 such as TiN is formed by a sputtering method, and a wiring 20 such as Al is formed.

As described above, according to the present embodiment, the position of guard ring layer 11b is determined in a self-aligned manner by thermal diffusion from polycrystalline silicon layer 8, and is separated from element isolation insulating film 6 at the periphery of the element region. Never. Therefore, it is possible to prevent an increase in the contact area between the guard ring layer 11b and the semiconductor layer 4 due to misalignment of the mask, thereby preventing an increase in parasitic capacitance.

The polycrystalline silicon layer 8 for determining the position of the guard ring layer 11b is selectively etched together with the insulating film 9 by photolithography and dry etching in the step of FIG. At this time, since the opening of the multilayer pattern of the polycrystalline silicon layer 8 and the insulating film 9 is arranged in the opening of the element isolation insulating film 6,
The total contact area of the polycrystalline silicon layer 8 in contact with the surface of the semiconductor layer 4 does not change even if the arrangement of the openings of the laminated pattern is shifted to the left or right, for example. Therefore,
The contact area between the subsequently formed guard ring layer 11b and the semiconductor layer 4 also remains unchanged.

The high-concentration cathode layer 13b is also determined in a self-aligned manner by the opening 10b of the polycrystalline silicon layer 8, so that the distance from the guard ring layer 11b can be kept constant. When the high-concentration layers are close to or adjacent to each other, the withstand voltage is reduced at that portion. Therefore, a decrease in the reverse breakdown voltage can be prevented. Further, since the distance between the high-concentration cathode layer 13b and the guard ring layer 11b can be kept constant, the variation in reverse breakdown voltage can be suppressed.

When forming the guard ring layer 11b, a shallow junction may be formed by high-temperature rapid heat treatment such as RTA (Rapid Thermal Annealing). Thereby, the contact area with the semiconductor layer 4 is reduced, the parasitic capacitance can be reduced, and the distance from the high-concentration cathode layer 13b is increased, so that the reverse breakdown voltage can be improved.

Next, a method of manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. The second embodiment is a method of manufacturing a semiconductor device in which an SBD having the structure of the first embodiment is formed on the same substrate as a bipolar transistor.

First, as shown in FIG. 3A, an n ⁺ -type buried layer 2 and a p-type
After forming the ⁺ -type buried layer 3, an n ⁻ -type semiconductor layer 4 is formed thereon by epitaxial growth.
^A p-type impurity diffusion layer 5 is formed on the ⁺ -type buried layer 3.
Next, an element isolation insulating film 6 is formed in a predetermined portion (a portion excluding the element region C and the collector lead region D of the bipolar transistor and the element region A and the cathode lead region B of the SBD) by the LOCOS method or the like, and n ⁺ Formed impurity diffusion layer 7 is formed in collector lead region D and cathode lead region B.

Next, as shown in FIG. 3B, a polycrystalline silicon layer 8 in which impurities such as boron are introduced in advance is deposited on the surfaces of the semiconductor layer 4 and the element isolation insulating film 6 by CVD. An insulating film 9 such as SiO ₂ is formed thereon by a CVD method. Then, the polycrystalline silicon layer 8 and the insulating film 9 are selectively removed by photolithography and dry etching techniques, and the opening 10a of the region where the intrinsic base is to be formed and the region where the Schottky barrier refractory metal silicide layer is to be formed Are simultaneously formed. Thereafter, by applying a heat treatment, boron previously introduced into the polycrystalline silicon layer 8 is thermally diffused into the n ⁻ -type semiconductor layer 4 to be activated, and the p ⁺ -type external base layer 11a and the guard ring layer 11b are activated. Form at the same time.

Next, as shown in FIG.
Boron or the like is ion-implanted only in 0a to form a p-type intrinsic base layer 12. Further, impurities such as phosphorus are implanted from the openings 10a and 10b to form an n ⁺ -type high-concentration collector layer (SIC layer) 13a near the junction between the semiconductor layer 4 and the intrinsic base layer 12, and at the same time to form an n ⁺ -type. Is also formed inside the semiconductor layer 4.
The high concentration collector layer 13a is provided for suppressing the Kirk effect, and the high concentration cathode layer 13b is effective for reducing the cathode resistance.

Next, a side wall insulating film 14 is formed on the side wall of the intrinsic base opening 10a, and thereafter a polycrystalline silicon layer is formed on the entire surface, and the resultant is patterned to form an emitter electrode 15a, a collector electrode 15b, and a cathode electrode. 15c is formed. This emitter electrode 15a
Then, for example, arsenic is ion-implanted and an annealing process is performed to form an n-type emitter diffusion layer 16.

Next, as shown in FIG. 4B, the semiconductor layer 4, element isolation insulating film 6, polycrystalline silicon layer 8, insulating film 9
BPS is formed on the entire surface of the emitter electrode 15a, the collector electrode 15b, and the cathode electrode 15c by CVD.
An interlayer insulating film 17 such as a G film or a TEOS film is deposited, a Schottky barrier forming area and contact holes for the collector, emitter, base, and cathode are formed, and a refractory metal serving as a Schottky barrier metal is formed on the entire surface. I do. Then, heat treatment such as lamp annealing is performed on the high melting point metal to selectively silicify only the high melting point metal located on silicon and polycrystalline silicon, and select an unreacted high melting point metal on the interlayer insulating film 17. To form high melting point metal silicide layers 18a to 18e. The refractory metal silicide layer 18e formed on the surface of the semiconductor layer 4 becomes the anode region of the SBD, and the refractory metal silicide layer 18e
A Schottky junction is formed between e and the relatively low concentration n ⁻ -type semiconductor layer 4.

Thereafter, as shown in FIG. 5, a barrier metal 19 such as TiN is formed by a sputtering method.
The wiring 20 of Al or the like is formed.

As described above, according to the second embodiment,
The SBD guard ring layer 11b and the high-concentration cathode layer 13b can be formed in the same step as the bipolar forming step without adding a new process to the conventional self-aligned bipolar process.
Is obtained.

When the guard ring layer 11b and the external base layer 11a are formed, RTA (Rapid Thermal
By forming a shallow junction by high-temperature rapid heat treatment such as annealing (annealing), the guard ring layer 1 is formed in the SBD.
The contact area between the semiconductor layer 4 and the semiconductor layer 4 is reduced, the parasitic capacitance can be reduced, and the distance between the guard ring layer 11b and the high-concentration cathode layer 13b is increased, so that the reverse breakdown voltage can be improved.

In the first and second embodiments, an example has been described in which the first conductivity type is n-type and the second conductivity type is p-type.

[0038]

As described above, according to the first and second aspects of the present invention, the guard ring layer and the high-concentration cathode layer of the SBD are formed in a self-aligned manner using the polycrystalline silicon layer. In addition, it is possible to prevent an increase in parasitic capacitance and a decrease in reverse breakdown voltage.

According to the fourth aspect of the present invention, the SBD guard ring layer and the high-concentration cathode layer can be formed without adding a new process to the conventional bipolar process. Is obtained.

Further, according to the third and fifth aspects of the present invention,
The junction of the guard ring layer with the semiconductor layer in the SBD can be made shallower, which reduces the contact area with the semiconductor layer and reduces the parasitic capacitance, and also increases the distance between the high-concentration cathode layer and the opposite direction. The withstand voltage can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view for illustrating the method for manufacturing the semiconductor device in FIG.

FIG. 3 is a process cross-sectional view for describing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a process cross-sectional view for describing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a process cross-sectional view for describing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional SBD.

FIG. 7 is a cross-sectional view of a conventional SBD when the position of a guard ring layer of the SBD is shifted.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 n ⁺ -type buried layer 3 p ⁺ -type buried layer 4 n ^-- type semiconductor layer 5 p-type impurity diffusion layer 6 element isolation insulating film 7 n ⁺ -type impurity diffusion layer 8 polycrystalline silicon layer 9 insulating film 10 a intrinsic base Region opening 10b Schottky barrier forming region opening 11a External base layer 11b Guard ring layer 12 Intrinsic base layer 13a n ⁺ type high concentration collector layer 13b n ⁺ type high concentration cathode layer 14 Side wall insulating film 15a Emitter electrode 15b Collector electrode 15c Cathode electrode 16 Emitter diffusion layer 17 Interlayer insulating film 18a-18e Refractory metal silicide layer 19 Barrier metal 20 Metal electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB22 BB25 BB26 BB40 CC03 DD02 DD26 DD78 DD81 DD84 DD92 FF35 GG03 GG15 HH20 5F048 AA00 AA05 AA09 AC05 AC10 BA02 BA07 BA12 BF03 BF06 BG12 BH01 DB03 CA07 AA02 AA06 BA02 BA04 BA21 BC09 BC12 DA09 EA04 EA09 EA27 EA29 EA45

Claims (5)

[Claims] A first conductive type semiconductor layer formed on a semiconductor substrate; an element isolation insulating film formed on the semiconductor layer so as to surround an element region; and the semiconductor in a peripheral portion of the element region. A second conductivity type polycrystalline silicon layer formed over the layer from above the element isolation insulating film and having an opening at the center of the element region; and formed on the semiconductor layer surface immediately below the polycrystalline silicon layer. A second conductive type guard ring layer, a first conductive type high concentration cathode layer formed in the opening region of the polycrystalline silicon layer and inside the semiconductor layer and having a higher concentration than the semiconductor layer; And a refractory metal silicide layer formed on the surface of the semiconductor layer in an opening region of the silicon layer. A step of forming a first conductivity type semiconductor layer on a semiconductor substrate; a step of forming an element isolation insulating film on the semiconductor layer so as to surround an element region; Depositing a polycrystalline silicon layer containing a second conductivity type impurity on the isolation insulating film, and selectively removing the polycrystalline silicon layer to remove the element isolation insulating film from above the semiconductor layer around the element region; Forming an opening in the center of the element region by leaving it over the upper portion; and thermally diffusing the second conductivity type impurity contained in the remaining polycrystalline silicon layer to form a portion immediately below the polycrystalline silicon layer. Forming a second conductivity type guard ring layer on the surface of the semiconductor layer; and performing ion implantation through an opening in the polycrystalline silicon layer to form a second semiconductor layer having a higher concentration than the semiconductor layer inside the semiconductor layer. Forming a high-concentration cathode layer conductivity type, a method of manufacturing a semiconductor device including the step of forming a refractory metal silicide layer on the semiconductor layer surface of the opening portion of the polycrystalline silicon layer. 3. The method according to claim 2, wherein the guard ring layer is formed by performing a high-temperature rapid heat treatment. 4. A method of manufacturing a semiconductor device in which a Schottky barrier diode and a bipolar transistor are formed on the same semiconductor substrate, comprising: forming a first conductivity type semiconductor layer on the semiconductor substrate; Forming an element isolation insulating film on the semiconductor layer so as to surround each element region of the diode and the bipolar transistor; and a polycrystalline silicon layer containing a second conductivity type impurity on the semiconductor layer and the element isolation insulating film. And by selectively removing the polycrystalline silicon layer, the Schottky barrier diode is allowed to remain over the semiconductor layer around the element region of the Schottky barrier diode over the element isolation insulating film. An opening is formed at the center of the element region of the bipolar transistor, and at the same time, an opening in the element region of the bipolar transistor is formed. Forming an opening in a portion corresponding to a region where an intrinsic base layer is to be formed; and thermally diffusing a second conductivity type impurity contained in the remaining polycrystalline silicon layer to form an element region of the Schottky barrier diode. Forming a guard ring layer of a second conductivity type on the surface of the semiconductor layer immediately below the polycrystalline silicon layer, and simultaneously forming a second conductivity type externally on the surface of the semiconductor layer immediately below the polycrystalline silicon layer in the element region of the bipolar transistor. Forming a base layer; and performing ion implantation through an opening in the polycrystalline silicon layer to increase the concentration of the first conductivity type higher than the semiconductor layer inside the semiconductor layer in the element region of the Schottky barrier diode. At the same time as forming the high-concentration cathode layer, the semiconductor layer is formed inside the semiconductor layer in the element region of the bipolar transistor. Forming a high-concentration first-concentration-type high-concentration collector layer; and forming a high-melting-point metal silicide layer on the surface of the semiconductor layer in the opening of the polycrystalline silicon layer in the element region of the Schottky barrier diode. And a method of manufacturing a semiconductor device. 5. The method according to claim 4, wherein the formation of the guard ring layer and the external base layer is performed by performing a high-temperature rapid heat treatment.