JP2001267553A - Charge transfer device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve transfer efficiency at he final step of a charge transfer part by reducing floating diffusion capacity in a charge-detecting part. SOLUTION: A floating diffusion layer 3 consists of an N+ type semiconductor region 3a, an N--type semiconductor region 3b and an N-type semiconductor offset region 18. The N+-type semiconductor region 3a is formed into an island shape or is stretched from an output gate electrode 10 as far as a reset gate electrode 9 in the floating diffusion layer 3, without making contact with a P+-type element isolation region 2, and is formed at a concentration higher than that of an N-type semiconductor region 7 of the charge transfer part. The N--type semiconductor region 3b is formed of a concentration lower part that of the N-type semiconductor region 7 of the charge transfer part so as to be depleted, and is formed between the P+-type element isolating region 23 and he N+-type semiconductor region 3a, in such a manner that a region end of an output gate electrode side of the N--type semiconductor region 3b is separated from the output gate electrode 10. The N-type semiconductor offset region 18 is formed of the same concentration as that of the N-type semiconductor region 7 of the charge transfer part, in a gap between the output gate electrode 10 and the N--type semiconductor region 3b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a charge transfer technique, and more particularly, to a charge transfer device for detecting a signal charge transferred from a charge transfer portion with a floating diffusion layer and a method of manufacturing the same.

[0002]

2. Description of the Related Art A reset MOSFET having a floating diffusion layer is used for detecting a signal charge transferred from a charge transfer section.
A charge transfer device having a gate electrode connected to the floating diffusion layer and having a floating diffusion amplifier composed of a detection MOSFET constituting a detection circuit has been well known in the related art. For example, as conventional examples, there are those described in JP-A-61-198676 and JP-A-11-135772.

A charge transfer device having the floating diffusion amplifier will be described with reference to FIGS. FIG. 19 is a plan view of a floating diffusion layer including a charge transfer portion and a reset MOSFET of the charge transfer device, and FIG.
FIG. 21 is a diagram schematically showing a cross section along a line, and FIG.
FIG. 9 is a diagram schematically illustrating a cross section taken along line II-II ′ of FIG. 9.
19 to 21, 1 is a P-type semiconductor substrate, 2 is a high-concentration P ⁺ -type element isolation region for element isolation, 3 is a floating diffusion layer, 3a is an N ⁺ -type semiconductor region of a floating diffusion layer, and 3b is The N ⁻ -type semiconductor region of the floating diffusion layer, 4 is a high-concentration N ⁺ -type reset drain connected to the reset drain power supply VRD, and 5 is a detection MO of a detection circuit connected to the floating diffusion layer.
The gate electrode of the SFET, the gate electrode of the load MOSFET is 6, for return prevention of signal charge by an N-type semiconductor region and the same conductivity type of the two-phase drive charge transfer sections known respectively 7, 8 N ^- -type semiconductor region, 9 is a reset gate electrode to which a reset pulse ФR is applied, 10 is an output gate electrode to which a constant voltage of the last stage of the charge transfer section is applied, and 11 and 12 are charge transfer electrodes to which charge transfer pulses 1H1 and ФH2 are applied, respectively. , 13 are the drain power supply VDD of the detection circuit,
Reference numeral 14 denotes a signal output terminal VOUT, and reference numeral 24 denotes a charge transfer unit.

In this charge transfer device, as is well known, a high level of a reset pulse ΔR is applied to the reset gate electrode 9 immediately before signal charges are transferred from the charge transfer portion to the floating diffusion layer. Reset drain voltage V
After resetting to RD, the reset pulse ΔR returns to low level, and the charge transfer pulse {H2
Is applied, and the signal charge is transferred to the floating diffusion layer 3.

Here, the detection M connected to the floating diffusion layer
The floating diffusion capacitance of the entire floating diffusion amplifier including the gate electrode of the OSFET and the like is Cfj, and the transferred signal charge amount is Qsi.
g, the potential fluctuation ΔVfj = Qsig /
Cfj is generated, and this potential fluctuation is detected by the detection MOSF of the detection circuit.
The gate voltage of the ET is changed, and a voltage change proportional to the signal charge Qsig is output to the signal output terminal 14 of the detection circuit.

In order to increase the detection sensitivity, it is necessary to reduce the floating diffusion capacitance Cfj. The lower the N-type impurity concentration of the floating diffusion layer 3 is, the more the P-type semiconductor substrate 1 and the floating diffusion layer 3 are surrounded. The parasitic capacitance between the P ⁺ -type element isolation region 2, the reset gate electrode 9, and the output gate electrode 10 is reduced. For this reason, the conventional floating diffusion layer 3 is a high-concentration N ⁺ type semiconductor region 3a (for example, impurity concentration = 1 ×) for connecting to the gate electrode of the detection circuit using a metal wiring.
About 10 ²⁰ atoms / cm ³ ) and P ⁺ -type element isolation region 2
Between them, a low-concentration N ⁻ type semiconductor region (for example, impurity concentration = about 5 × 10 ¹⁶ atoms / cm ³ ) 3b was formed.

[0007]

However, the charge transfer device having the above-mentioned conventional floating diffusion amplifier has the following problems. That is, in a charge transfer device having a conventional floating diffusion amplifier, a photoresist having an opening overlapping the reset gate electrode 9 and the output gate electrode 10 or an N ⁺ type semiconductor from the output gate electrode 10 to the reset gate electrode 9 Area 3
The N ^- type semiconductor region 3b is formed by ion-implanting a P-type impurity such as boron by using a photoresist covering a region near the center of the channel including a and a gate electrode of the reset gate electrode 9 and the output gate electrode 10 as a mask. It is formed inside the floating diffusion layer 3. Usually, the N ^- type semiconductor region 3b
Is to reduce the floating diffusion capacitance Cfj as much as possible.
P-type impurity implantation formed in a region narrower than the channel width of output gate electrode 10 on floating diffusion layer 3 side determined by ⁺ -type element isolation region 3 and implanted to form N ⁻ -type semiconductor region 3b The amount is selected as large as possible (for example, about 1 × 10 ¹² atoms / cm ² ) in a range where the potential near the center of the channel from the output gate electrode 10 to the reset gate electrode 9 of the floating diffusion layer 3 is not depleted. .

The problem when the N ⁻ type semiconductor region 3b is formed in the floating diffusion layer 3 as described above will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 22 is a plan view showing the vicinity of a floating diffusion layer of a conventional charge transfer device, and FIG.
24 is a schematic view of a cross section and a potential distribution along the line III-III ′, and FIG. 24 is a schematic view of a cross section and a potential distribution along the line IV-IV ′ of FIG.

The potential in the transfer direction near the center of the channel where the N ⁻ type semiconductor region 3 b of the floating diffusion layer 3 in FIG. 22 is not formed is obtained by applying the high level of the reset pulse ΔR to the reset gate electrode 9. As shown in FIG. 23, the reset drain voltage VRD is set. At this time, the signal charge flowing through the center of the channel of the charge transfer section floats linearly from the charge transfer electrode 12 to which the charge transfer pulse ΔH2 is applied through the output gate electrode 10, as shown in the transfer path 16a of FIG. It is quickly transferred to the diffusion layer 3.

On the other hand, the floating diffusion layer 3 in FIG. 22 N ^-
The potential of the transfer direction in the region -type semiconductor region 3b is formed, as shown in FIG. 24, N ^- -type semiconductor regions 3
Since the potential is shallow at b, a potential barrier 17 is formed at the electrode end of the output gate electrode 10 on the floating diffusion layer side. Therefore, when the signal charge flowing through the channel end of the charge transfer section is transferred from the charge transfer electrode 12 to which the charge transfer pulse ΔH2 is applied to the floating diffusion layer 3, the signal charge shown in FIG.
As shown in the transfer path 16b, N under the output gate electrode 10 from the channel edge of the charge transfer section to the channel center ^-
It is transferred so as to go around the type semiconductor region 3b.

[0011] As a result, the signal charges flowing through the channel end of the charge transfer portion, as compared to the signal charge flowing through the channel center of the charge transfer portion, since the transfer time is long at the output gate electrode, N ^- -type semiconductor region 3b is In the conventional charge transfer device having the floating diffusion layer 3 formed, the charge transfer at the output gate electrode 10 is a factor that limits the transfer efficiency of the charge transfer unit.

In the conventional charge transfer device having a floating diffusion amplifier, the structure in which the N ⁻ type semiconductor region 3b is formed in the floating diffusion layer 3 in order to reduce the floating diffusion capacitance Cfj has been described. In order to further reduce the capacitance Cfj, the amount of the P-type impurity to be implanted into the floating diffusion layer 3 is further increased so that the P ⁻ -type semiconductor region (for example, impurity concentration = 5 × 10 4) is used instead of the N ⁻ -type semiconductor region 3b. ¹⁶ at
oms / cm ³ ) is also well known.

In this structure, the potential barrier 1 shown in FIG.
7, the signal charge flowing through the channel end of the charge transfer section is transferred such that the output gate electrode 10 further extends around the P ⁻ type semiconductor region from the channel end of the charge transfer section to the center of the channel. You. As a result, the signal charge flowing through the channel end of the charge transfer unit is shorter in the transfer time at the output gate electrode than the signal charge flowing through the center of the channel of the charge transfer unit in the N ⁻ type semiconductor region 3b.
Is formed, and the transfer efficiency of signal charges at the output gate electrode 10 is further reduced.

Therefore, in the conventional charge transfer device having a floating diffusion amplifier, the larger the amount of P-type impurity to be injected into the floating diffusion layer to reduce the floating diffusion capacitance Cfj, the more the output gate electrode becomes. Therefore, it has been difficult to increase the detection sensitivity while maintaining the transfer efficiency (for example, 99% for all-stage transfer) with no problem in image quality.

The present invention has been made in view of such a problem, and an object of the present invention is to simultaneously increase the detection sensitivity in a floating diffusion amplifier and the transfer efficiency in an output gate electrode. And a method for manufacturing the same.

[0016]

The gist of the present invention is that a floating diffusion layer receiving a signal charge from a charge transfer portion of a second conductivity type formed on a semiconductor substrate of a first conductivity type; A second conductive type diffusion layer connected to a reset drain power supply for removing the signal charge later, a reset MOSFET including a reset gate electrode to which a reset pulse is supplied, and a reset MOSFET connected to the floating diffusion layer. A detection MOSFET constituting a circuit for detecting a potential change of the floating diffusion layer, wherein the floating diffusion layer is formed in an island shape in the floating diffusion layer without contacting the first conductivity type element isolation region. A high-concentration second-conductivity-type semiconductor region for connection to the detection MOSFET; and the first-conductivity-type element isolation region formed apart from the output gate electrode of the second-conductivity-type charge transfer unit. A low concentration of the second conductivity type semiconductor region formed between the fine the high-concentration second conductivity-type semiconductor region,
A charge transfer device is provided with a second conductivity type semiconductor offset region formed in a gap between the output gate electrode and the low concentration second conductivity type semiconductor region. According to another aspect of the present invention, a floating diffusion layer receiving a signal charge from a second conductivity type charge transfer unit formed on a first conductivity type semiconductor substrate, and removing the signal charge after the charge detection. MOSFET comprising a second conductivity type diffusion layer connected to a reset drain power supply for resetting and a reset gate electrode supplied with a reset pulse
And a detection MOSFET connected to the floating diffusion layer and constituting a circuit for detecting a potential change of the floating diffusion layer, wherein the floating diffusion layer does not contact the first conductivity type element isolation region. A high-concentration second-conductivity-type semiconductor region formed in the diffusion layer so as to extend from the output gate electrode of the second-conductivity-type charge transfer section to the reset gate electrode and connecting to the detection MOSFET; A low-concentration second conductivity-type semiconductor region formed apart from the gate electrode and formed between the first conductivity-type element isolation region and the high-concentration second conductivity-type semiconductor region; The charge transfer device includes a second conductivity type semiconductor offset region formed in a gap between the second concentration conductivity type semiconductor region. Claim 3
The gist of the present invention is that a floating diffusion layer receiving a signal charge from a second conductivity type charge transfer unit formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after the charge detection And a reset MOSFET including a reset gate electrode to which a reset pulse is supplied, and a circuit connected to the floating diffusion layer and detecting a potential change of the floating diffusion layer. The floating diffusion layer is formed in an island shape in the floating diffusion layer without being in contact with the first conductivity type element isolation region, and has a high-concentration second concentration for connecting to the detection MOSFET. A two-conductivity-type semiconductor region, the first-conductivity-type element isolation region formed apart from an output gate electrode of the second-conductivity-type charge transfer section, and the high-concentration second-conductivity-type semiconductor region A charge transfer device comprising: a first conductivity type semiconductor region formed therebetween; and a second conductivity type semiconductor offset region formed in a gap between the output gate electrode and the first conductivity type semiconductor region. Exists. According to another aspect of the present invention, a floating diffusion layer receiving a signal charge from a second conductivity type charge transfer unit formed on a first conductivity type semiconductor substrate, and removing the signal charge after the charge detection. MOSFET comprising a second conductivity type diffusion layer connected to a reset drain power supply for resetting and a reset gate electrode supplied with a reset pulse
And a detection MOSFET connected to the floating diffusion layer and constituting a circuit for detecting a potential change of the floating diffusion layer, wherein the floating diffusion layer does not contact the first conductivity type element isolation region. A high-concentration second-conductivity-type semiconductor region formed in the diffusion layer so as to extend from the output gate electrode of the second-conductivity-type charge transfer section to the reset gate electrode and connecting to the detection MOSFET; A first conductivity type semiconductor region formed apart from the gate electrode and formed between the first conductivity type element isolation region and the high-concentration second conductivity type semiconductor region; the output gate electrode and the first conductivity type; The charge transfer device includes a second conductivity type semiconductor offset region formed in a gap between the semiconductor regions. According to another aspect of the present invention, a floating diffusion layer receiving a signal charge from a second conductivity type charge transfer unit formed on a first conductivity type semiconductor substrate, and removing the signal charge after the charge detection. Reset MOSFET composed of a second conductivity type diffusion layer connected to a reset drain power supply for resetting, a reset gate electrode to which a reset pulse is supplied, and a potential fluctuation of the floating diffusion layer connected to the floating diffusion layer. M for detection constituting a detection circuit
An OSFET, wherein the floating diffusion layer has a high-concentration second conductivity type semiconductor region formed in an island shape in the floating diffusion layer and connected to the detection MOSFET; A first conductivity type element isolation region formed apart from an output gate electrode of the first portion and formed so as to have a channel width smaller than that of the second conductivity type charge transfer portion; and the output gate electrode and the first conductivity type element The charge transfer device includes a second conductivity type semiconductor offset region formed in a gap between the isolation regions. According to another aspect of the present invention, a floating diffusion layer receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and removing the signal charge after the charge detection. Reset MOSFET composed of a second conductivity type diffusion layer connected to a reset drain power supply for resetting, a reset gate electrode to which a reset pulse is supplied, and a potential fluctuation of the floating diffusion layer connected to the floating diffusion layer. A detection MOSFET constituting a detection circuit, wherein the floating diffusion layer is formed in the floating diffusion layer so as to extend from the output gate electrode of the second conductivity type charge transfer section to the reset gate electrode. A high-concentration second-conductivity-type semiconductor region for connecting to the detection MOSFET; and a channel formed at a distance from the output gate electrode and larger than the second-conductivity-type charge transfer unit. And a second conductivity type semiconductor offset region formed in a gap between the output gate electrode and the first conductivity type device isolation region. Charge transfer device. The gist of the invention described in claim 7 is that the floating diffusion layer includes the second conductivity type semiconductor offset region having a higher concentration than the second conductivity type charge transfer portion. Item 7 is the charge transfer device according to any one of Items 1 to 6. The gist of the invention described in claim 8 is that the length of the second conductivity type semiconductor offset region in the charge transfer direction is 0.1 μm to 2 μm. The charge transfer device described in the above section. Further, the gist of the invention according to claim 9 is that the second conductive type semiconductor offset region stores the maximum amount of signal charges transferred from the second conductive type charge transfer unit in the floating diffusion layer. The charge transfer device according to any one of claims 1 to 8, wherein at least a part of the region is depleted. Claim 10
The gist of the invention described in (1) is a step of forming a second conductivity type semiconductor layer in a surface region of a first conductivity type semiconductor substrate, and a step of forming a conductive electrode on a surface of the second conductivity type semiconductor layer via a gate insulating film. Forming a material film; forming a first mask material on the conductive electrode material film; removing at least the first mask material on a region where a floating diffusion layer is formed; Removing the conductive electrode material film using the first mask material as a mask to form at least an output gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; Forming a second mask material on the entire surface of the conductive electrode material film and the gate insulating film; and covering a boundary between the output gate electrode and the floating diffusion layer, and forming a second mask material on at least the floating diffusion layer. A step of removing a second mask material; and a step of ion-implanting a first conductivity type impurity into the floating diffusion layer using at least the second mask material and the reset gate electrode as a mask. A method for manufacturing a charge transfer device. Claim 1
The gist of the invention described in 1 is a step of forming a second conductivity type semiconductor layer in a surface region of a first conductivity type semiconductor substrate;
Forming a conductive electrode material film on the surface of the conductive semiconductor layer via a gate insulating film, forming a first mask material on the conductive electrode material film, and forming at least a floating diffusion layer Removing the first mask material on a region to be formed, and removing the conductive electrode material film using the first mask material as a mask to form at least an output gate electrode and a reset gate electrode; Forming a floating diffusion layer between the electrode and the reset gate electrode; and removing a first mask material over the entire surface to remove a second mask material over the conductive electrode material film and over the gate insulating film. Forming, and at least the floating diffusion layer,
Removing the second mask material on a part of the output gate electrode and the reset gate electrode; and forming a first conductive material in the floating diffusion layer using at least the output gate electrode and the reset gate electrode as a mask. Ion-implanting a type impurity at an angle from the output gate electrode side. The gist of the invention described in claim 12 is a step of forming a second conductivity type semiconductor layer in a surface region of a first conductivity type semiconductor substrate, and forming a gate insulating film on a surface of the second conductivity type semiconductor layer. Forming a conductive electrode material film via a conductive material layer, forming a first mask material on the conductive electrode material film, and removing the first mask material on at least a region where a floating diffusion layer is to be formed Removing the conductive electrode material film using the first mask material as a mask to form at least an output gate electrode and a reset gate electrode, and a floating diffusion layer between the output gate electrode and the reset gate electrode. Forming a second mask material on the entire surface of the conductive electrode material film and the gate insulating film by removing the entire first mask material; and forming at least the floating diffusion layer Said Removing the second mask material on one region on the side of the power gate electrode, and ion-implanting a second conductivity type impurity into the floating diffusion layer using at least the second mask material and the output gate electrode as a mask And a method of manufacturing a charge transfer device. The gist of the invention described in claim 13 is that the second region is provided on the surface region of the first conductivity type semiconductor substrate.
Forming a conductive type semiconductor layer, forming a conductive electrode material film on a surface of the second conductive type semiconductor layer via a gate insulating film, and forming a first mask on the conductive electrode material film Forming a material, at least a step of removing the first mask material on a region where a floating diffusion layer is to be formed, and removing at least the output by removing the conductive electrode material film using the first mask material as a mask. Forming a gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; and forming at least the output gate electrode and the reset gate electrode as a mask in the floating diffusion layer. And a step of ion-implanting a second conductivity type impurity. Further, the gist of the invention according to claim 14 is that, after forming a floating diffusion layer between the output gate electrode and the reset gate electrode, a first layer is formed on the entire surface of the conductive electrode material film and the gate insulating film. Forming at least one third mask material on at least one region of the floating diffusion layer on the output gate electrode side; and forming at least the third mask material and the output gate electrode. And a step of ion-implanting a second conductivity type impurity into the floating diffusion layer by using a mask as a mask. The gist of the invention according to claim 15 is that, after forming a floating diffusion layer between the output gate electrode and the reset gate electrode, the floating diffusion layer is formed using at least the output gate electrode and the reset gate electrode as a mask. 2. The method according to claim 1, further comprising the step of ion-implanting a second conductivity type impurity into the semiconductor device.
0. The method for manufacturing a charge transfer device according to 0 or 11.

[0017]

(First Embodiment) A first embodiment of the present invention.
The structure, manufacturing method, and effects of the charge transfer device according to the embodiment will be described below. First, the first of the present invention
The structure near the floating diffusion layer 3, which is the most significant feature of the charge transfer device according to the embodiment, will be described with reference to FIGS. 1 and 2 are plan views of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the first embodiment. FIG. 3 is a schematic view of a cross section and a potential distribution along line III-III ′ in FIG. 4, FIG.
FIG. 4 is a schematic diagram of a cross section and a potential distribution along a line IV-IV ′.

In the structure near the floating diffusion layer 3 of the charge transfer device according to the first embodiment, as shown in FIGS. 1, 3, and 4, the floating diffusion layer 3 is composed of an N ⁺ type semiconductor region 3a,
It is composed of an N ⁻ type semiconductor region 3 b and an N ⁻ type semiconductor offset region 18. The N ⁺ -type semiconductor region 3a is formed in the floating diffusion layer 3 in an island shape without contacting the P ⁺ -type element isolation region 2, and is connected to the gate electrode of the detection MOSFET so that the N-type semiconductor region 3a It is formed at a higher concentration than the region 7. In FIG. 1, the N ⁺ type semiconductor region 3a is formed near the center in the floating diffusion layer 3, but is not necessarily formed near the center. N
^{The −} type semiconductor region 3 b is formed at a lower concentration than the N type semiconductor region 7 of the charge transfer section 24 so that this region is depleted, and the end of the N ⁻ type semiconductor region 3 b on the output gate electrode 10 side is output. It is formed between the P ⁺ -type element isolation region 2 and the N ⁺ -type semiconductor region 3a apart from the gate electrode 10. N ^-
The type semiconductor offset region 18 is formed in the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3 b at the same concentration as the N type semiconductor region 7 of the charge transfer section 24.

Next, a method of manufacturing the charge transfer device according to the first embodiment of the present invention will be described with reference to FIGS. FIGS. 5 and 6 are schematic views of a cross section taken along line IV-IV ′ of FIG. 1 for explaining the manufacturing method of the first embodiment.

In the manufacturing method according to the first embodiment, the N-type semiconductor region 7 and the N ⁻ -type semiconductor region 8 of the charge transfer portion 24, the charge transfer electrode 12, the output gate electrode 10, and the reset gate are formed on the P-type semiconductor substrate 1. The method of manufacturing the charge transfer device for forming the electrode 9 is the same as that of a known two-layer electrode two-phase drive charge transfer device. Here, a method of forming the N ⁻ -type semiconductor region 3b of the floating diffusion layer 3, which is the most significant feature of the manufacturing method of the first embodiment, will be described.

FIG. 5 is a view for explaining a first manufacturing method for forming the N ⁻ type semiconductor region 3b. Photoresist 2
0 is formed to cover one region of the floating diffusion layer 3 on the output gate electrode 10 side. Using the photoresist 20 and the reset gate electrode 9 as a mask, the P-type impurity 2
By ion-implanting 1, the N ⁻ type semiconductor region 3 b can be formed at a desired distance from the output gate electrode 10 and in a self-aligned manner with respect to the reset gate electrode 9.

FIG. 6 is a view for explaining a second manufacturing method for forming the N ⁻ type semiconductor region 3b. No photoresist 20 is formed on the floating diffusion layer 3, and a P-type impurity 21 is formed.
Are ion-implanted using the output gate electrode 10 and the reset gate electrode 9 as a mask. At this time, the P-type impurity 2
1 is implanted obliquely in the transfer direction so that the N ⁻ -type semiconductor region 3 b is separated from the output gate electrode 10 by a desired distance and self-aligned with the output gate electrode 10 and the reset gate electrode 9. It is formed.

Next, effects of the charge transfer device according to the first embodiment of the present invention will be described. According to the structure of the charge transfer device of the first embodiment, as a first effect, the N ⁻ type semiconductor region 3b is formed such that the charge transfer portion 2 is depleted in this region.
4 is formed at a lower concentration than the N-type semiconductor region 7,
The signal charge transferred from the charge transfer unit 24 to the floating diffusion layer 3 (see FIGS. 3B and 4B) is transferred to the P ⁺ -type element isolation region 2 surrounding the floating diffusion layer 3 and the reset gate electrode 9. , And the parasitic capacitance with the output gate electrode 10 is reduced. As a result, the floating diffusion capacitance Cfj is reduced, and the detection sensitivity is improved.

As a second effect, the N ⁻ type semiconductor region 3 b
Is formed such that the end of the region on the output gate electrode 10 side is separated from the output gate electrode 10, and the output gate electrode 10 and N ⁻
In the gap between the n-type semiconductor regions 3b, an N ⁻ -type semiconductor offset region 18 having the same concentration as that of the N-type semiconductor region 7 of the charge transfer section 24 is provided.
Is formed, the potential 19 of the N ⁻ type semiconductor offset region 18 (see FIG. 4B) becomes deeper than the channel potential 23 of the output gate electrode 10 (see FIG. 4B). The potential barrier 17 in the output gate electrode 10 generated in the device disappears. As a result, the signal charge flowing through the channel end of the charge transfer unit 24 (see FIGS. 3B and 4B) flows through the center of the channel of the charge transfer unit 24 as shown in the transfer path 16b in FIG. As in the case of the signal charges (see FIGS. 3B and 4B), the charge is quickly transferred to the floating diffusion layer 3 through the output gate electrode 10 linearly, and the transfer efficiency at the output gate electrode 10 is improved. I do.

As described above, the output gate electrode 10 and N^-Mold half
N is set in the gap between the conductor regions 3b.^-Type semiconductor offset region 18
To form N^-Type semiconductor offset region 1
8 (see FIG. 4B) is the length of the transfer direction.
It is possible to adjust the depth by changing the depth
You. The signal charge at the output gate electrode 10 (see FIG.
4 (b)), the transfer efficiency is N^-Type semiconductor offset
The potential 19 (see FIG. 4B) of the cut region 18 is deepened.
The better. On the other hand, N^-Type semiconductor offset region 1
8 (see FIG. 4B) is applied to the charge transfer unit 24.
Floating spread when the maximum charge is transferred and stored in the floating diffusion layer 3
The potential V of the layer 3_Qmax(See FIG. 3 (b) and FIG. 4 (b)
N)^-Type semiconductor offset region 1
8 also has signal charges (see FIGS. 3 (b) and 4 (b)).
Will be accumulated. As a result, signal charges (FIG. 3)
(B) and FIG. 4 (b)) show the reset gate in particular.
The parasitic capacitance with the electrode 9 increases, and the floating diffusion capacitance Cfj increases.
Will increase. Therefore, transfer at the output gate electrode 10
To reduce the floating diffusion capacitance Cfj while improving the efficiency
Is N ^-4 (see FIG. 4).
(B)) is the channel potential 23 of the output gate electrode 10.
(See FIG. 4B) and deeper than the maximum charge accumulation.
The potential V of the floating diffusion layer 3_Qmax(FIGS. 3B and 4
It should be adjusted so that it becomes shallower than (b).
^-The length of the semiconductor offset region 18 in the transfer direction is
It is desirable to set it to about 0.1 to 2 μm.

According to the method of manufacturing the charge transfer device of the first embodiment, as a third effect, in the first manufacturing method, the edge position of the photoresist 20 on the output gate electrode 10 side is changed. , The offset amount of the N ⁻ type semiconductor region 3b can be freely set, and the edge of the N ⁻ type semiconductor region 3b on the reset gate electrode 9 side is
Since the setting is performed in a self-aligned manner with respect to the reset gate electrode 9, the fluctuation of the floating diffusion capacitance Cfj due to the mask misalignment of the N ⁻ type semiconductor region 3b can be suppressed. Further, in the second manufacturing method, the offset amount of the N ⁻ -type semiconductor region 3b can be freely set by changing the angle at which the P-type impurity 21 is implanted, and the output of the N ⁻ -type semiconductor region 3b can be set. edge of the gate electrode 10 side and the reset gate electrode 9 side, since each is determined in a self-aligned manner with respect to the output gate electrode 10 and the reset gate electrode 9, N ^- -type floating diffusion capacitance by mask misalignment semiconductor region 3b Variations in Cfj can be further suppressed than in the first manufacturing method.

The above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 1 is formed in the floating diffusion layer 3 in an island shape. Represents an N ⁺ type semiconductor region 3a ′, as shown in FIG.
May be formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9. In addition,
In FIG. 2, the N ⁺ type semiconductor region 3a is a floating diffusion layer 3
Although it is formed near the center of the inside, it is not necessarily required to be formed near the center. In this structure, even if the floating diffusion layer 3 is charged up or the potential at the time of depletion of the floating diffusion layer 3 due to the decrease in the impurity concentration of the N ⁻ type semiconductor region 3b decreases, the high concentration N ⁺ type semiconductor Region 3a '
Is formed extending from the output gate electrode 10 to the reset gate electrode 9, the channel does not deplete from the output gate electrode 10 to the reset gate electrode 9, so that the floating diffusion capacitance Cfj The fourth effect is that a charge transfer device with small fluctuations in the sensitivity and stable detection sensitivity is realized.

The charge transfer device according to the first embodiment of the present invention will be described in more detail. First, the structure of the charge transfer device according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are plan views of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the first embodiment. FIG. 3 is a schematic cross-sectional view taken along line III-III ′ of FIG. FIG. 4 and FIG. 4 are schematic views of a cross section and a potential distribution along the line IV-IV ′ in FIG.

The reference numerals used in FIGS. 1 to 4 correspond to the reference numerals in FIGS. 1 to 4, 1 is a P-type semiconductor substrate, 2 is a high-concentration P ⁺ -type element isolation region for element isolation, 3 is a floating diffusion layer, 3a is an N ⁺ -type semiconductor region of a floating diffusion layer, 3b is an N ⁻ type semiconductor region of the floating diffusion layer, and 4 is a reset drain voltage VRD (FIG.
(B) and FIG. 4 (b)).
^{The +} -type reset drains 7, 8 are N-type semiconductor regions 7 of the two-phase drive charge transfer unit 24 and Ns of the same conductivity type for preventing signal charges (see FIGS. 3B and 4B) from returning back. ^The reset gate electrodes 9 and 10 to which the reset pulse ΔR is applied are connected to the charge transfer section 2.
4, the output gate electrode 10, to which the constant voltage of the final stage is applied,
11 and 12 are charge transfer pulses ФH1 and ФH2, respectively.
Are the drain power supply VDD of the detection circuit, 19 is the potential of the N-type semiconductor offset region, 23 is the channel potential of the output gate electrode, and 24 is the charge transfer section.

The structure of the charge transfer device of the first embodiment is
Referring to FIGS. 1, 3 and 4, the floating diffusion layer 3
Is N⁺Type semiconductor region 3a, N^-Type semiconductor region 3b, and
And N^-It is composed of a type semiconductor offset region 18. N⁺
Type semiconductor region 3a⁺Contact with the die isolation region 2
Is formed in the floating diffusion layer 3 in an island shape, and the detection MOS
In order to connect to the gate electrode 5 of the FET, an impurity concentration of 1 ×
10¹⁷atoms / cm ^ThreeN-type charge transfer unit 24
Higher concentration than semiconductor region 7 (1 × 10¹⁹atoms / c
m^ThreeDegree). N^-Type semiconductor region 3b
The N-type semiconductor region of the charge transfer section 24 is depleted so that the region is depleted.
Lower concentration than area 7 (5 × 10¹⁶atoms / cm^ThreeAbout
Degrees) and N^-Gate voltage of the semiconductor region 3b
The end of the region on the pole 10 side is 0.3 μm from the output gate electrode 10
P away⁺Type element isolation region 2 and N⁺Semiconductor region
3a. N^-Type semiconductor offset region 1
8 is the output gate electrode 10 and N^-Gap in semiconductor region 3b
In the meantime, the same concentration as the N-type semiconductor region 7 of the charge transfer section 24 (1
× 10¹⁷atoms / cm^ThreeDegree).

[0031] Thus the output gate electrode 10 and the N ^- by forming a type semiconductor offset region 18, N ^{- -} clearance type semiconductor region 3b is about 0.3 [mu] m, N in the gap type semiconductor offset region 18 Potential 19 (FIG. 4)
(See (b)) is set to about 12V. The output gate voltage is 1.5 V, the reset drain voltage VRD (FIG. 3B)
And FIG. 4B) is set to 15 V, and the charge of 100,000 electrons is transferred from the charge transfer unit 24 to the floating diffusion capacitance Cfj = 8.
When transferred to the floating diffusion layer 3 of fF, the channel potential 23 (see FIG. 4B) of the output gate electrode 10 becomes about 10
V, the potential V _Qmax of the floating diffusion layer 3 when the maximum charge amount is transferred and accumulated (see FIGS. 3B and 4B) is about 13
V. Accordingly, the channel potential 23 of the output gate electrode 10 (see FIG. 4B) (about 10 V) <the potential 19 of the N ⁻ type semiconductor offset region 18 (see FIG. 4B) (about 1 V).
2V), the signal charge (see FIGS. 3B and 4B) flowing through the channel end of the charge transfer section 24 is applied to the output gate electrode 10 as shown in the transfer path 16b of FIG.
Is transferred to the floating diffusion layer 3 in a straight line, and the transfer efficiency at the output gate electrode 10 is improved. In addition, N ^-
4 (see FIG. 4B) (approximately 12 V) <potential V _Qmax of the floating diffusion layer 3 when the maximum amount of charge is transferred and accumulated (see FIGS. 3B and 4B). )
(See FIG. 3B) (about 13 V), so that no signal charge (see FIGS. 3B and 4B) is accumulated in the N ⁻ type semiconductor offset region 18 and the floating diffusion capacitance Cfj does not increase.

Next, a method of manufacturing the charge transfer device according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 5 and FIG. 6 are schematic views of a cross section taken along line IV-IV ′ of FIG. 1 for explaining the manufacturing method of the first embodiment.

In the manufacturing method according to the first embodiment, P
Semiconductor region 7 of charge transfer section 24 on semiconductor substrate 1
The method of manufacturing the charge transfer device for forming the N ⁻ type semiconductor region 8, the charge transfer electrode 12, the output gate electrode 10, and the reset gate electrode 9 is the same as a known two-layer electrode two-phase drive charge transfer device. Here, a method of forming the N ⁻ type semiconductor region 3b, which is the most significant feature of the manufacturing method according to the first embodiment, will be described.

FIG. 5 is a view for explaining a first manufacturing method for forming the N ⁻ type semiconductor region 3b. Photoresist 2
0 is 0.3 from the output gate electrode 10 side of the floating diffusion layer 3.
It is formed so as to cover an area of about μm. Using the photoresist 20 and the reset gate electrode 9 as a mask, the P-type impurity 21 is ion-implanted at an implantation amount of about 5 × 10 ¹¹ atoms / cm ^2, so as to be separated from the output gate electrode 10 by a distance of about 0.3 μm. N ⁻ type semiconductor region 3 b can be formed in a self-aligned manner with reset gate electrode 9.

FIG. 6 is a view for explaining a second manufacturing method for forming the N ⁻ type semiconductor region 3b. No photoresist 20 is formed on the floating diffusion layer 3, and a P-type impurity 21 is formed.
Is set to 5 × 10 ¹¹ atoms using the output gate electrode 10 and the reset gate electrode 9 having a thickness of about 0.3 μm as a mask.
The ions are implanted at a dose of about s / cm ² . At this time,
By implanting the P-type impurity 21 at an angle of about 45 degrees in the transfer direction, the P-type impurity 21 is separated from the output gate electrode 10 by a distance of about 0.3 μm, and is self-aligned with the output gate electrode 10 and the reset gate electrode 9. N ^- type semiconductor region 3
b can be formed.

The above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 1 is formed in the floating diffusion layer 3 in an island shape, but the charge transfer device of the first embodiment is applied. The device has an N ⁺ type semiconductor region 3 as shown in FIG.
a ′ may be formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9 with a width of about 1 μm.

(Second Embodiment) The structure and effects of a charge transfer device according to a second embodiment of the present invention will be described below. First, the structure near the floating diffusion layer 3, which is the most significant feature of the charge transfer device according to the second embodiment of the present invention, will be described with reference to FIGS. FIG. 7 is a plan view of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the second embodiment.
Is a schematic diagram of a cross section and a potential distribution along the line III-III ′ in FIG. 7, and FIG. 9 is a schematic diagram of a cross section and a potential distribution along the line IV-IV ′ of FIG.

The structure near the floating diffusion layer 3 of the charge transfer device according to the second embodiment is described with reference to FIGS.
P ^- type semiconductor region 3c instead of N ^- type semiconductor region 3b of FIG.
The structure is the same as the structure of the charge transfer device of the first embodiment except that the structure is formed. Therefore, only the configuration of the P ⁻ type semiconductor region 3c will be described here.

[0039] P ^- -type semiconductor region 3c, this region is formed at a lower concentration than the N-type semiconductor region 7 of the charge transfer section 24 so depleted, P ^- -type semiconductor region 3c of the output gate electrode 10 side The end of the region is separated from the output gate electrode 10 by P
It is formed between the ⁺ type element isolation region 2 and the N ⁺ type semiconductor region 3a.

The method of manufacturing the charge transfer device according to the second embodiment of the present invention will be described with reference to FIGS.
Except for the injection amount, the method is the same as the method of manufacturing the charge transfer device of the first embodiment. That is, in the second embodiment,
By increasing the implantation amount of the P-type impurity 21 more than in the first embodiment, the P ⁻ -type semiconductor region 3c is formed instead of the N ⁻ -type semiconductor region 3b of the floating diffusion layer 3.

Next, the effect of the charge transfer device according to the second embodiment of the present invention will be described. According to the charge transfer device of the second embodiment, the first, second, and third effects can be obtained similarly to the charge device of the first embodiment, but the first effect is particularly remarkable. That is, in the second embodiment, the P ⁻ type semiconductor region 3 c is formed in the floating diffusion layer 3, so that this region is further depleted than in the first embodiment, and the charge transfer unit 24 removes the floating diffusion layer from the charge transfer unit 24. The signal charge (see FIGS. 8 (b) and 9 (b)) transferred and accumulated in the P.sub.3 is connected to the P.sup. ⁺ Type element isolation region 2 surrounding the floating diffusion layer 3, the reset gate electrode 9, and the output gate electrode 10. The parasitic capacitance is further reduced. As a result, the floating diffusion capacitance Cfj is greatly reduced, and the detection sensitivity is improved as compared with the charge transfer device of the first embodiment.

The length of the N ⁻ type semiconductor offset region 18 formed in the gap between the output gate electrode 10 and the P ⁻ type semiconductor region 3 c in the transfer direction is the same as that of the charge transfer device of the first embodiment. Therefore, it is desirable to set the thickness to about 0.1 to 2 μm.

Further, the above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 7 is formed in the floating diffusion layer 3 in an island shape. In the transfer device, similarly to the charge transfer device of the first embodiment, the N ⁺ -type semiconductor region 3a may be formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9. . In this case, the same effect as the fourth effect in the first embodiment can be obtained.

The charge transfer device according to the second embodiment of the present invention will be described in more detail. First, the structure of the charge transfer device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a plan view of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the second embodiment, and FIG.
FIG. 9 is a schematic view of a cross section and a potential distribution along the line II ′,
FIG. 8 is a schematic view of a cross section and a potential distribution along a line IV-IV ′ in FIG. 7.

The symbols used in FIGS. 7 to 9 correspond to the symbols in FIGS. 19 to 21, as in the first embodiment. The structure of the charge transfer device of the second embodiment is the same as that of the first embodiment except that the P ⁻ type semiconductor region 3c of the floating diffusion layer 3 is formed with reference to FIGS. It has the same structure as the charge transfer device. Therefore, only the configuration of the P ⁻ type semiconductor region 3c will be described here.

The P ⁻ type semiconductor region 3 c is formed with a P type impurity 21 concentration of about 5 × 10 ¹⁶ atoms / cm ³ so that this region is depleted, and the P ⁻ type semiconductor region 3 c is closer to the output gate electrode 10. Is formed between the P ⁺ -type element isolation region 2 and the N ⁺ -type semiconductor region 3a at a distance of about 0.5 μm from the output gate electrode 10.

As described above, the gap between the output gate electrode 10 and the P ⁻ -type semiconductor region 3 c is set to about 0.5 μm, and the N ⁻ -type semiconductor offset region 18 is formed in the gap. Similarly to the transfer device, the potential 19 of the N ⁻ type semiconductor offset region 18 (see FIG. 9B) is set to about 12V. Output gate electrode 10 and P
The gap (about 0.5 μm) in the transfer direction of the N ⁻ type semiconductor offset region 18, that is, the gap between the ⁻ type semiconductor regions 3 c is the first.
The length of the charge transfer device of the second embodiment (about 0.3 μm) is longer than that of the N ⁻ type semiconductor region 3 of the first embodiment.
The potential 19 of the N ⁻ -type semiconductor offset region 18 is affected by the P ⁻ -type semiconductor region 3 c having a potential lower than that of the N ⁻ -type semiconductor region 3 c.
This is to prevent (see FIG. 9B) from becoming lower than the channel potential 23 of the output gate electrode 10 (see FIG. 9B).

The method of manufacturing the charge transfer device according to the second embodiment of the present invention will be described with reference to FIGS. It is the same as the first and second manufacturing methods of the charge transfer device of the embodiment. That is, in the second embodiment, the P-type impurity 2
The P ⁻ type semiconductor region 3c of the floating diffusion layer 3 is formed by increasing the implantation amount of 1 to about 1.5 × 10 ¹² atoms / cm ² more than in the first embodiment. When the P-type impurity 21 is implanted at an angle,
By injecting tilted about 60 degrees in the forward direction, P from the output gate electrode 10 at a distance of about 0.5 [mu] m ^-
The type semiconductor region 3c can be formed.

The above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 7 is formed in the floating diffusion layer 3 in an island shape. The device is similar to the charge transfer device of the first embodiment,
The N ⁺ type semiconductor region 3a may be formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9 with a width of about 1 μm.

(Third Embodiment) The structure, manufacturing method and effects of a charge transfer device according to a third embodiment of the present invention will be described below.

First, the structure near the floating diffusion layer 3 which is the most significant feature of the charge transfer device according to the third embodiment of the present invention is shown in FIG.
Description will be made using 0 to 13. FIG. 10 and FIG.
FIG. 12 is a plan view of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the third embodiment. FIG. IV-
FIG. 4 is a schematic view of a cross section and a potential distribution along a line IV ′.

Referring to FIGS. 10 to 13, the structure of the charge transfer device of the third embodiment near the floating diffusion layer 3 has a channel width defined by the P ⁺ -type element isolation region 3d of the floating diffusion layer 3. Except that the charge transfer portion 24 is formed narrower than the channel width defined by the P ⁺ -type element isolation region 2,
This is the same as the structure of the charge transfer device of the first embodiment. Therefore, here, the P ⁺ -type element isolation region 3d of the floating diffusion layer 3 is used.
Only the configuration will be described.

The P ⁺ -type element isolation region 3d of the floating diffusion layer 3
Are formed such that the channel width of this region is smaller than the channel width of the P ⁺ -type device isolation region 2 of the charge transfer portion 24, and furthermore, faces the output gate electrode 10 of the P ⁺ -type device isolation region 3 d of the floating diffusion layer 3. A region end is formed apart from output gate electrode 10. Note that the N ⁺ -type semiconductor region 3a and the P ⁺ -type element isolation region 3d of the floating diffusion layer 3 do not necessarily need to be separated from each other, and may be in contact with each other or overlap each other.

Next, the effects of the charge transfer device according to the third embodiment of the present invention will be described. According to the charge transfer device of the third embodiment, the first and second effects can be obtained similarly to the charge transfer devices of the first and second embodiments, but the first effect is particularly remarkable. . That is, in the third embodiment, the channel width of the floating diffusion layer 3 is
Is formed narrower than the channel width of the floating diffusion layer 3, the signal transferred to the floating diffusion layer 3 is very small surrounded by the P ⁺ -type element isolation region 3 d of the floating diffusion layer 3, Is accumulated only in the area where As a result, the floating diffusion capacitance Cfj is further reduced, and the detection sensitivity is improved as compared with the charge transfer devices of the first and second embodiments.

Further, the charge transfer device of the third embodiment
As in the charge transfer devices of the first and second embodiments, the N ⁻ type semiconductor region 3 b and the P ⁻ type semiconductor region 3
It is not necessary to additionally form c, and it can be realized only by changing the shape of the floating diffusion layer 3 of the P ⁺ -type element isolation region 2. Therefore, the fifth effect that the number of masks and the number of steps for manufacturing the charge transfer device can be reduced and the manufacturing cost and the manufacturing period can be reduced can be obtained.

The length of the N ⁻ type semiconductor offset region 18 formed in the gap between the output gate electrode 10 and the P ⁺ type element isolation region 3 d in the transfer direction is the same as that of the charge transfer device of the first embodiment. For this reason, it is desirable to set it to about 0.1 to 2 μm. The channel width defined by the P ⁺ -type element isolation region 3d of the floating diffusion layer 3 is equal to the floating diffusion capacitance C
In order to reduce fj as much as possible, the potential near the center of the channel from the output gate electrode 10 to the reset gate electrode 9 of the floating diffusion layer 3 is reduced by the reset drain voltage VRD due to the narrow channel effect (see FIGS. 12B and 13B). It is better to form as narrow as possible within a range not to be shallower than in ()), and it is desirable to set it to about 0.5 to 5 μm.

Further, the above description is based on the N ⁺ shown in FIG.
The present invention is applied to a charge transfer device in which the type semiconductor region 3a is formed in the floating diffusion layer 3 in an island shape. The charge transfer device of the third embodiment is similar to the charge transfer device of the first embodiment. , N ⁺ type semiconductor region 3 a may be formed in floating diffusion layer 3 so as to extend from output gate electrode 10 to reset gate electrode 9. In this case, the same effect as the fourth effect in the first embodiment can be obtained.

Further, the charge transfer device according to the third embodiment
As shown in FIG. 11, the P ⁺ -type element isolation region 3 d ′ of the floating diffusion layer 3 may be formed so as to be gradually narrowed from the output gate electrode 10 to the floating diffusion layer 3. In this case, the potential distribution of the N ⁻ -type semiconductor offset region 18 gradually becomes deeper from the channel end toward the center of the channel. Transfer efficiency is further improved.

The charge transfer device according to the third embodiment of the present invention will be described in more detail. First, the structure of the charge transfer device according to the third embodiment of the present invention will be described with reference to FIGS. 10 and 11 are plan views of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the third embodiment, and FIG. 12 is a cross-sectional view taken along line III-III ′ of FIG. FIG. 13 and FIG. 13 are schematic views of a cross section and a potential distribution along the line IV-IV ′ in FIG.

The symbols used in FIGS. 10 to 13 correspond to the symbols in FIGS. 19 to 21, as in the first embodiment. The structure of the charge transfer device according to the third embodiment is shown in FIG.
13 to 13, the channel width defined by the P ⁺ -type element isolation region 3d of the floating diffusion layer 3 is
The structure is the same as that of the charge transfer device of the first embodiment except that the channel width is smaller than the channel width defined by the ⁺ type element isolation region 2. Therefore, here, only the configuration of the P ⁺ -type element isolation region 3d of the floating diffusion layer 3 will be described.

The P ⁺ -type element isolation region 3d of the floating diffusion layer 3
Is formed of a high-concentration P-type impurity 21 of about 1 × 10 ¹⁸ atoms / cm ³ , and the end of the P ⁺ -type element isolation region 3d facing the output gate electrode 10 is the output gate electrode 10
Is formed at a distance of about 0.7 μm. The channel width defined by the P ⁺ -type element isolation region 3d is such that the potential near the center of the channel from the output gate electrode 10 to the reset gate electrode 9 of the floating diffusion layer 3 is the reset drain voltage VRD (FIG. 12) due to the narrow channel effect. (B) and FIG.
3 (b)) so as not to be shallower than 2 μm.

As described above, the gap between the output gate electrode 10 and the P ⁺ -type element isolation region 3 d is set to about 0.7 μm, and the N ⁻ -type semiconductor offset region 18 is formed in the gap. As in the charge transfer device of the embodiment, the potential 19 of the N ⁻ -type semiconductor offset region 18 (see FIG.
3 (b)) is set to about 12V. A gap between the output gate electrode 10 and the P ⁺ type element isolation region 3d, that is, the length of the N ⁻ type semiconductor offset region 18 in the transfer direction (about 0.7
μm) is longer than that of the charge transfer device of the second embodiment (about 0.5 μm) because of P ⁻ of the second embodiment.
The potential 19 of the N ⁻ -type semiconductor offset region 18 (see FIG. 13B) is changed to the channel potential 23 of the output gate electrode 10 by the influence of the P ⁺ -type element isolation region 3 d whose potential is lower than that of the type semiconductor region 3 c. (See FIG. 13B).

The above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 10 is formed in the floating diffusion layer 3 in an island shape, but the charge transfer device according to the third embodiment is applied. In the device, similarly to the charge transfer device of the first embodiment, an N ⁺ type semiconductor region 3a is formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9 with a width of about 1 μm. May be. In this case, from the output gate electrode 10 of the floating diffusion layer 3 to the reset gate electrode 9
, The potential near the center of the channel does not become shallower than the reset drain voltage VRD (see FIGS. 12B and 13B) due to the narrow channel effect.
^The channel width defined by the ⁺ type element isolation region 3d is 1 μm
The floating diffusion capacitance Cfj can be further reduced.

In the charge transfer device according to the third embodiment, as shown in FIG. 11, the P ⁺ -type element isolation region 3 d ′ of the floating diffusion It may be formed so that it is narrowed down gradually at an angle of about.

(Fourth Embodiment) The structure, manufacturing method, and effect of a charge transfer device according to a fourth embodiment of the present invention will be described below.

First, the structure near the floating diffusion layer 3 which is the most significant feature of the charge transfer device according to the fourth embodiment of the present invention is shown in FIG.
This will be described with reference to 4 to 16. FIG. 14 is a plan view near the floating diffusion layer 3 of the charge transfer device according to the fourth embodiment.
FIG. 15 is a schematic diagram of a cross section and a potential distribution along the line III-III ′ in FIG. 14, and FIG. 16 is a schematic diagram of a cross section and a potential distribution along the line IV-IV ′ of FIG.

The structure near the floating diffusion layer 3 of the charge transfer device of the fourth embodiment is the same as that of the first embodiment except for the N-type impurity concentration of the N ⁻ type semiconductor offset region 18 with reference to FIGS. This is the same as the structure of the charge transfer device of the embodiment. Therefore, only the configuration of the N ⁻ type semiconductor offset region 18 will be described here.

The N ⁻ -type semiconductor offset region 18 is formed in the gap between the output gate electrode 10 and the N ⁻ -type semiconductor region 3b.
The semiconductor region 7 is formed at a higher concentration than the N-type impurity concentration.

Next, a method of manufacturing the charge transfer device according to the fourth embodiment of the present invention will be described with reference to FIGS. FIG.
FIGS. 7 and 18 are schematic views of a cross section taken along line IV-IV ′ of FIG. 14 for explaining the manufacturing method of the fourth embodiment.

Referring to FIGS. 17 and 18, the method of manufacturing the charge transfer device according to the fourth embodiment of the present invention will be described with reference to FIGS. 17 and 18 except that N-type impurity 22 is implanted into N ⁻ -type semiconductor offset region 18. This is the same as the method of manufacturing the charge transfer device according to the embodiment. Here, a description will be given of a method of forming the N ⁻ type semiconductor offset region 18 which is the most significant feature of the manufacturing method of the fourth embodiment.

FIG. 17 shows an N ^- type semiconductor offset region 1.
FIG. 9 is a diagram illustrating a first manufacturing method for forming No. 8; The photoresist 20 is formed on the output gate electrode 10 of the floating diffusion layer 3.
It is formed so as to leave a gap in one area on the side. By the N-type impurity 22 using the photoresist 20 and the output gate electrode 10 as a mask ion implantation, an output gate electrode 10 and the N ^- gap type semiconductor region 3b, than the N-type semiconductor region 7 of the charge transfer section 24 of high concentration N ^-
The type semiconductor offset region 18 can be formed in a self-aligned manner with respect to the output gate electrode 10.

FIG. 18 shows an N ^- type semiconductor offset region 1.
FIG. 9 is a diagram illustrating a second manufacturing method for forming No. 8; No photoresist 20 is formed on the floating diffusion layer 3 and N
The type impurity 22 is ion-implanted in a self-aligned manner using the output gate electrode 10 and the reset gate electrode 9 as a mask. In this, N ^- -type semiconductor region N-type impurity 22 in a region 3b is formed is injected, since the N-type impurity concentration of this portion becomes high, N ^- region -type semiconductor region 3b is formed The impurity concentration of N
Type or P type.

Next, the effects of the charge transfer device according to the fourth embodiment of the present invention will be described. According to the charge transfer device of the fourth embodiment, the first charge transfer device is similar to the charge transfer device of the first embodiment.
And the second effect is obtained, but the second effect is particularly remarkable. That is, in the fourth embodiment, the charge transfer section 2 is provided in the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3b.
Since the N ⁻ type semiconductor offset region 18 having a higher concentration than that of the N type semiconductor region 7 of No. 4 is formed, not only the potential barrier 17 in the output gate electrode 10 generated in the conventional charge transfer device disappears, but also As shown in FIG.
The charge transfer electric field from the output gate electrode 10 to the floating diffusion layer 3 is strengthened, and the transfer efficiency at the output gate electrode 10 is improved.

The length of the N ⁻ type semiconductor offset region 18 formed in the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3b in the transfer direction is the same as that of the charge transfer device of the first embodiment. Therefore, it is desirable to set the thickness to about 0.1 to 2 μm.

According to the method of manufacturing the charge transfer device of the fourth embodiment, as a sixth effect, in the first manufacturing method, the edge of the N ⁻ type semiconductor offset region 18 on the side of the output gate electrode 10 is Is set in a self-aligned manner with respect to the output gate electrode 10, so that the N ⁻ type semiconductor offset region 1
8, the fluctuation of the floating diffusion capacitance Cfj due to the mask misalignment can be suppressed. Further, in the second manufacturing method,
When the N ⁻ type semiconductor offset region 18 is formed, the N ⁻ type semiconductor offset is implanted into the entire surface of the floating diffusion layer 3 in a self-aligned manner with respect to the output gate electrode 10 and the reset gate electrode 9. Variations in the floating diffusion capacitance Cfj due to mask misalignment in the region 18 can be further suppressed as compared with the first manufacturing method.

Further, the above description is based on the N ⁺
The present invention is applied to a charge transfer device in which the type semiconductor region 3a is formed in the floating diffusion layer 3 in an island shape. The charge transfer device of the fourth embodiment is similar to the charge transfer device of the first embodiment. , N ⁺ type semiconductor region 3 a may be formed in floating diffusion layer 3 so as to extend from output gate electrode 10 to reset gate electrode 9. In this case, the same effect as the fourth effect in the first embodiment can be obtained.

In the charge transfer device of the fourth embodiment, the case where the N-type impurity 22 is ion-implanted into the N ⁻ -type semiconductor offset region 18 of the charge transfer device of the first embodiment has been described. In the charge transfer device of the third embodiment, the N-type impurity 22 may be ion-implanted into the N ⁻ -type semiconductor offset region 18 of the floating diffusion layer 3. The same effect as described above can be obtained.

It should be noted that the present invention is not limited to the configuration and the manufacturing method of each of the above embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

The charge transfer device according to the fourth embodiment of the present invention will be described in more detail. First, the structure of the charge transfer device according to the fourth embodiment of the present invention will be described with reference to FIGS. FIG. 14 is a plan view of the vicinity of the floating diffusion layer 3 of the charge transfer device according to the fourth embodiment, and FIG.
FIG. 16 is a schematic diagram of a cross section along line III-III ′ and a potential distribution, and FIG. 16 is a schematic diagram of a cross section along line IV-IV ′ of FIG.

Each of the reference numerals used in FIGS. 14 to 16 corresponds to the reference numerals in FIGS. 19 to 21, as in the first embodiment. The structure of the charge transfer device according to the fourth embodiment is shown in FIG.
To 16, the N ⁻ type semiconductor offset region 18
The structure is the same as that of the charge transfer device of the first embodiment except for the N-type impurity concentration of the first embodiment. Therefore, only the configuration of the N ⁻ type semiconductor offset region 18 will be described here.

The end of the N ⁻ type semiconductor region 3 b on the side of the output gate electrode 10 is 0.15 from the output gate electrode 10.
It is formed between the P ⁺ -type element isolation region 2 and the N ⁺ -type semiconductor region 3a at a distance of about μm. Further, the N ⁻ type semiconductor offset region 18 is formed in the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3 b, and the N type impurity concentration of this region is An impurity concentration higher than 1 × 10 ¹⁷ atoms / cm ³ (2 × 1
0 ¹⁷ atoms / cm ³ ).

Output gate electrode 10 and N ⁻ type semiconductor region 3
The reason why the gap b, that is, the length (about 0.15 μm) in the transfer direction of the N ⁻ type semiconductor offset region 18 is shorter than that of the charge transfer device of the first embodiment (about 0.3 μm) is N Potential of the N ⁻ -type semiconductor offset region 18 due to the increase in the impurity concentration of the N type (FIG. 16B)
(See Reference). Thus, the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3b is set to 0.15 μm.
And an N-type impurity concentration of 2 × 10 ^{17 at}
By forming the N ⁻ type semiconductor offset region 18 of ms / cm ³ , the potential 19 of the N ⁻ type semiconductor offset region 18 (see FIG. 1) as in the charge transfer device of the first embodiment.
6 (b)) is set to about 12V.

Next, a method of manufacturing the charge transfer device according to the fourth embodiment of the present invention will be described with reference to FIGS. FIGS. 17 and 18 are schematic views of a cross section taken along line IV-IV ′ of FIG. 14 for explaining the manufacturing method according to the fourth embodiment.

Referring to FIGS. 17 and 18, the manufacturing method of the charge transfer device according to the fourth embodiment of the present invention is the same as that of the first embodiment except for the N-type impurity concentration of N ⁻ type semiconductor offset region 18. This is the same as the method of manufacturing the charge transfer device described above. Here, a method of forming the N ⁻ type semiconductor offset region 18 which is the most significant feature of the manufacturing method of the fourth embodiment will be described.

FIG. 17 shows an N ^- type semiconductor offset region 1.
FIG. 9 is a diagram illustrating a first manufacturing method for forming No. 8; The photoresist 20 is formed on the output gate electrode 10 of the floating diffusion layer 3.
It is formed so as to leave a gap of 0.15 μm in one area on the side. Using the photoresist 20 and the output gate electrode 10 as a mask, the N-type impurity 22 is 1 × 10 ¹² at.
By implanting ions at an implantation amount of about oms / cm ^2, an N ⁻ type semiconductor offset having a higher concentration than the N ⁻ type semiconductor region 7 of the charge transfer unit 24 is inserted into the gap between the output gate electrode 10 and the N ⁻ type semiconductor region 3 b. The region 18 can be formed in a self-aligned manner with respect to the output gate electrode 10.

FIG. 18 shows an N ^- type semiconductor offset region 1.
FIG. 9 is a diagram illustrating a second manufacturing method for forming No. 8; No photoresist 20 is formed on the floating diffusion layer 3 and N
The type impurity 22 is 1 × 10 ¹² atoms / cm using the output gate electrode 10 and the reset gate electrode 9 as a mask.
Ion implantation is performed in a self-aligned manner with an implantation amount of about ² . In this, N ^- -type semiconductor region N-type impurity 22 in a region 3b is formed is injected, since the N-type impurity concentration of this portion becomes high, N ^- region -type semiconductor region 3b is formed Is 5 × 10 ¹⁶ atoms in advance.
It is necessary to set a P type of about s / cm ³ .

The above description is applied to the charge transfer device in which the N ⁺ type semiconductor region 3a shown in FIG. 14 is formed in the floating diffusion layer 3 in an island shape, but the charge transfer device according to the fourth embodiment is applied. In the device, similarly to the charge transfer device of the first embodiment, an N ⁺ -type semiconductor region 3a is formed in the floating diffusion layer 3 so as to extend from the output gate electrode 10 to the reset gate electrode 9 with a width of about 1 μm. It may be.

In the charge transfer device of the fourth embodiment, the N ⁻ type impurity 22 of about 1 × 10 ¹² atoms / cm ^{2 is} added to the N ⁻ type semiconductor offset region 18 of the charge transfer device of the first embodiment. Has been described, but the charge transfer devices of the second and third embodiments also have the N ⁻ -type semiconductor offset region 1 of the floating diffusion layer 3.
8 to 1 × 10 ¹² atoms / cm ² of about N-type impurity 2
2 may be ion-implanted.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0090]

According to the present invention having the above-described structure, the N ⁻ type semiconductor region, the P ⁻ type semiconductor region of the floating diffusion layer,
Alternatively, by forming the P ⁺ -type element isolation region away from the output gate electrode, it is possible to reduce the floating diffusion capacitance and at the same time improve the transfer efficiency of charges from the output gate electrode to the floating diffusion layer. .

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration near a floating diffusion layer according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a configuration near a floating diffusion layer according to the first embodiment of the present invention.

FIG. 3 is a schematic view of a cross section taken along line III-III ′ of FIG. 1 and a potential distribution, showing a configuration near a floating diffusion layer according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram of a cross section taken along line IV-IV ′ of FIG. 1 and a potential distribution, showing a configuration near a floating diffusion layer according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram of a cross section taken along line IV-IV ′ of FIG. 1 for describing a first manufacturing method according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view taken along the line IV-IV ′ of FIG. 1 for illustrating a second manufacturing method according to the first embodiment of the present invention.

FIG. 7 is a plan view showing a configuration near a floating diffusion layer according to a second embodiment of the present invention.

FIG. 8 is a schematic view of a cross section taken along line III-III ′ of FIG. 7 and a potential distribution showing a configuration near a floating diffusion layer according to a second embodiment of the present invention.

FIG. 9 is a schematic view of a cross section taken along line IV-IV ′ of FIG. 7 and a potential distribution showing a configuration near a floating diffusion layer according to a second embodiment of the present invention.

FIG. 10 is a plan view showing a configuration near a floating diffusion layer according to a third embodiment of the present invention.

FIG. 11 is a plan view showing a configuration near a floating diffusion layer according to a third embodiment of the present invention.

FIG. 12 is a schematic view of a cross section taken along line III-III ′ of FIG. 10 and a potential distribution showing a configuration near a floating diffusion layer according to a third embodiment of the present invention.

FIG. 13 is a schematic diagram illustrating a cross section taken along line IV-IV ′ of FIG. 10 and a potential distribution, showing a configuration near a floating diffusion layer according to a third embodiment of the present invention.

FIG. 14 is a plan view showing a configuration near a floating diffusion layer according to a fourth embodiment of the present invention.

FIG. 15 is a schematic diagram of a cross section taken along line III-III ′ of FIG. 14 and a potential distribution showing a configuration near a floating diffusion layer according to a fourth embodiment of the present invention.

FIG. 16 is a schematic view of a cross section taken along line IV-IV ′ of FIG. 14 and a potential distribution showing a configuration near a floating diffusion layer according to a fourth embodiment of the present invention.

FIG. 17 is a schematic diagram of a cross section taken along line IV-IV ′ of FIG. 14 for illustrating a first manufacturing method according to the fourth embodiment of the present invention.

FIG. 18 is a schematic diagram of a section along a line IV-IV ′ in FIG. 14 for illustrating a second manufacturing method according to the fourth embodiment of the present invention.

FIG. 19 is a plan view showing a configuration of a charge transfer device in a first conventional example.

FIG. 20 is a cross-sectional view taken along the line II ′ of FIG. 19, showing the configuration of the charge transfer device in the first conventional example.

FIG. 21 is a cross-sectional view taken along the line II-II ′ of FIG. 19, illustrating a configuration of the charge transfer device in the first conventional example.

FIG. 22 is a plan view showing a configuration near a floating diffusion layer in a first conventional example.

FIG. 23 is a schematic view of a cross section taken along line III-III ′ of FIG. 22 and a potential distribution showing a configuration near a floating diffusion layer in the first conventional example.

24 is a schematic view of a cross section taken along line IV-IV ′ of FIG. 22 and a potential distribution showing a configuration near a floating diffusion layer in the first conventional example.

[Explanation of symbols]

1 ... P-type semiconductor substrate 2 ... P ⁺ -type element isolation region 3 ... floating diffusion layer 3a ... floating diffusion layer N ⁺ -type semiconductor region 3b ... floating diffusion layer N ^- -type semiconductor regions 3c ... floating diffusion layer P ^- -type Semiconductor region 3d P ⁺ type element isolation region of floating diffusion layer 4 Reset drain 5 Gate electrode of MOSFET for detection 6 Gate electrode of MOSFET for load 7 N-type semiconductor region of charge transfer section 8 Charge transfer section N ^- type semiconductor region 9 ... reset gate electrode 10 ... output gate electrode 11 ... charge transfer electrode to which charge transfer pulse ФH1 is applied 12 ... charge transfer electrode to which charge transfer pulse ФH2 is applied 13 ... drain power supply of detection circuit 14 ... Signal output terminal 16a: transfer path of signal charge flowing through the center of the channel of the charge transfer section 16b: transfer path of signal charge flowing through the channel end of the charge transfer section 17: output gate Potential barrier at pole 18 N-type semiconductor offset region of floating diffusion layer 19 N-type semiconductor offset region potential 20 Photoresist 21 P-type impurity 22 N-type impurity 23 Channel potential of output gate electrode 24 Charge transfer Department

Claims (15)

[Claims] 1. A floating diffusion layer for receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after detecting the charge. A reset MOSFET including a second conductivity type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. MOSFET, wherein the floating diffusion layer is formed in an island shape in the floating diffusion layer without being in contact with the first conductivity type element isolation region.
A high-concentration second-conductivity-type semiconductor region for connection to an OSFET; a first-conductivity-type element isolation region formed apart from an output gate electrode of the second-conductivity-type charge transfer section; A low conductivity second conductivity type semiconductor region formed between the first conductivity type semiconductor regions, and a second conductivity type semiconductor offset region formed in a gap between the output gate electrode and the low concentration second conductivity type semiconductor region. A charge transfer device. 2. A floating diffusion layer receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after detecting the charge. A reset MOSFET including a second conductivity type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. MOSFET, wherein the floating diffusion layer extends from the output gate electrode of the second conductivity type charge transfer section to the reset gate electrode in the floating diffusion layer without contacting the first conductivity type element isolation region. A high-concentration second-conductivity-type semiconductor region formed to be connected to the detection MOSFET; and a first-conductivity-type element isolation formed apart from the output gate electrode. A low-concentration second-conductivity-type semiconductor region formed between the region and the high-concentration second-conductivity-type semiconductor region; and a gap between the output gate electrode and the low-concentration second-conductivity-type semiconductor region. A charge transfer device comprising a second conductivity type semiconductor offset region. 3. A floating diffusion layer receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after detecting the charge. A reset MOSFET including a second conductivity type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. MOSFET, wherein the floating diffusion layer is formed in an island shape in the floating diffusion layer without being in contact with the first conductivity type element isolation region.
A high-concentration second-conductivity-type semiconductor region for connecting to an OSFET; a first-conduction-type element isolation region formed apart from an output gate electrode of the second-conductivity-type charge transfer section; First formed between the mold semiconductor regions
A charge transfer device comprising: a conductive type semiconductor region; and a second conductive type semiconductor offset region formed in a gap between the output gate electrode and the first conductive type semiconductor region. 4. A floating diffusion layer for receiving signal charges from a second conductivity type charge transfer section formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charges after detecting the charges. A reset MOSFET including a second conductive type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. A floating diffusion layer extending from the output gate electrode of the second conductivity type charge transfer section to the reset gate electrode in the floating diffusion layer without contacting the first conductivity type element isolation region. A high-concentration second-conductivity-type semiconductor region formed to connect to the detection MOSFET; and a first-conductivity-type element isolation formed apart from the output gate electrode. The formed between the band and the second conductive type semiconductor region of the high concentration 1
A charge transfer device comprising: a conductive type semiconductor region; and a second conductive type semiconductor offset region formed in a gap between the output gate electrode and the first conductive type semiconductor region. 5. A floating diffusion layer receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after detecting the charge. A reset MOSFET including a second conductive type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. And a high-concentration second layer formed in the floating diffusion layer in an island shape and connected to the detection MOSFET.
A conductive type semiconductor region and a first conductive type element isolation region formed apart from an output gate electrode of the second conductive type charge transfer unit and formed to have a smaller channel width than the second conductive type charge transfer unit. And a second conductive type semiconductor offset region formed in a gap between the output gate electrode and the first conductive type element isolation region. 6. A floating diffusion layer receiving a signal charge from a second conductivity type charge transfer portion formed on a first conductivity type semiconductor substrate, and a reset drain power supply for removing the signal charge after the charge detection. A reset MOSFET including a second conductive type diffusion layer, a reset gate electrode to which a reset pulse is supplied, and a detection MOSFET connected to the floating diffusion layer and configured to detect a potential change of the floating diffusion layer. A floating diffusion layer formed in the floating diffusion layer so as to extend from the output gate electrode of the second conductivity type charge transfer section to the reset gate electrode and to be connected to the detection MOSFET. And a second conductive type semiconductor region having a high concentration and formed so as to be separated from the output gate electrode and to have a smaller channel width than the second conductive type charge transfer portion. Charge transfer device comprising a first conductive type isolation region, characterized in that it comprises a second conductivity type semiconductor offset region formed in the gap of said output gate electrode and the first conductive type isolation region. 7. The semiconductor device according to claim 1, wherein the floating diffusion layer includes the second conductivity type semiconductor offset region having a higher concentration than the second conductivity type charge transfer portion. Item 10. The charge transfer device according to Item 7. 8. The charge transfer device according to claim 1, wherein a length of the second conductivity type semiconductor offset region in a charge transfer direction is 0.1 μm to 2 μm. 9. The second conductive type semiconductor offset region has at least a part of the depletion region even when the floating diffusion layer stores the maximum amount of signal charge transferred from the second conductive type charge transfer unit. The charge transfer device according to any one of claims 1 to 8, wherein the charge transfer device comprises: 10. A step of forming a second conductive type semiconductor layer in a surface region of a first conductive type semiconductor substrate; and forming a conductive electrode material film on a surface of the second conductive type semiconductor layer via a gate insulating film. Forming; forming a first mask material on the conductive electrode material film; removing at least the first mask material on a region where a floating diffusion layer is to be formed; Removing the conductive electrode material film using a mask material as a mask to form at least an output gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; Forming a second mask material on the entire surface of the conductive electrode material film and the gate insulating film; and covering a boundary between the output gate electrode and the floating diffusion layer, and forming at least the second mask material on the floating diffusion layer. 2) removing the second mask material, and ion-implanting a first conductivity type impurity into the floating diffusion layer using at least the second mask material and the reset gate electrode as a mask. A method for manufacturing a transfer device. 11. A step of forming a second conductive type semiconductor layer in a surface region of a first conductive type semiconductor substrate; and forming a conductive electrode material film on a surface of the second conductive type semiconductor layer via a gate insulating film. Forming; forming a first mask material on the conductive electrode material film; removing at least the first mask material on a region where a floating diffusion layer is to be formed; Removing the conductive electrode material film using a mask material as a mask to form at least an output gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; Forming a second mask material on the entire surface of the conductive electrode material film and the gate insulating film by removing the entirety of the first mask material; and at least the floating diffusion layer, the output gate electrode, Removing the second mask material on a partial region of the reset gate electrode, and outputting the first conductivity type impurity into the floating diffusion layer using at least the output gate electrode and the reset gate electrode as a mask. And implanting ions at an angle from the gate electrode side. 12. A step of forming a second conductivity type semiconductor layer in a surface region of a first conductivity type semiconductor substrate; and forming a conductive electrode material film on a surface of the second conductivity type semiconductor layer via a gate insulating film. Forming; forming a first mask material on the conductive electrode material film; removing at least the first mask material on a region where a floating diffusion layer is to be formed; Removing the conductive electrode material film using a mask material as a mask to form at least an output gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; Forming a second mask material on the entire surface of the conductive electrode material film and the gate insulating film by removing the entire mask material; and at least one of the floating diffusion layers on the output gate electrode side. Removing the second mask material on a region, and ion-implanting a second conductivity type impurity into the floating diffusion layer using at least the second mask material and the output gate electrode as a mask. A method for manufacturing a charge transfer device, comprising: 13. A step of forming a second conductive type semiconductor layer in a surface region of a first conductive type semiconductor substrate; and forming a conductive electrode material film on a surface of the second conductive type semiconductor layer via a gate insulating film. Forming; forming a first mask material on the conductive electrode material film; removing at least the first mask material on a region where a floating diffusion layer is to be formed; Removing the conductive electrode material film by using a mask material as a mask to form at least an output gate electrode and a reset gate electrode, and forming a floating diffusion layer between the output gate electrode and the reset gate electrode; Ion-implanting a second conductivity type impurity into the floating diffusion layer using the output gate electrode and the reset gate electrode as a mask. Law. 14. A step of forming a third mask material on the entire surface of the conductive electrode material film and the gate insulating film after forming a floating diffusion layer between the output gate electrode and the reset gate electrode. Removing the third mask material on at least one region of the floating diffusion layer on the side of the output gate electrode; and using at least the third mask material and the output gate electrode as a mask in the floating diffusion layer. 12. The method according to claim 10, further comprising the step of ion-implanting a second conductivity type impurity. 15. After forming a floating diffusion layer between the output gate electrode and the reset gate electrode, using the output gate electrode and the reset gate electrode as a mask, implant a second conductivity type impurity in the floating diffusion layer. 2. The method according to claim 1, further comprising the step of implanting ions.
12. The method for manufacturing a charge transfer device according to 0 or 11.