KR0167606B1 - Process of fabricating mos-transistor - Google Patents
Process of fabricating mos-transistor Download PDFInfo
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- KR0167606B1 KR0167606B1 KR1019940037669A KR19940037669A KR0167606B1 KR 0167606 B1 KR0167606 B1 KR 0167606B1 KR 1019940037669 A KR1019940037669 A KR 1019940037669A KR 19940037669 A KR19940037669 A KR 19940037669A KR 0167606 B1 KR0167606 B1 KR 0167606B1
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- 238000000034 method Methods 0.000 title claims description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910021645 metal ion Inorganic materials 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 108091006146 Channels Proteins 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000032683 aging Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 얕은 접합을 형성하기 위한 매립형 LDD 구조 트랜지스터 제조방법에 관한 것으로, 반도체기판에 소자분리층, 게이트 및 소스/드레인이 형성되는 트랜지스터 제조방법에 있어서, 게이트전극 측벽에 제1스페이서를 형성한 후 이를 마스크로 상기 반도체기판에 이온주입하는 제1단계; 상기 게이트전극 및 제1스페이서 측벽에 제2스페이서를 형성한 후 이를 마스크로 게이트전극 하부의 반도체기판에 트랜치를 형성하는 제2단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of manufacturing a buried LDD structure transistor for forming a shallow junction. In a transistor manufacturing method in which an isolation layer, a gate, and a source / drain are formed on a semiconductor substrate, a first spacer is formed on a sidewall of a gate electrode. A first step of implanting ions into the semiconductor substrate using a mask; And forming a second spacer on the sidewalls of the gate electrode and the first spacer, and then forming a trench in the semiconductor substrate under the gate electrode using the mask.
Description
제1도는 종래기술에 따라 형성된 LDD구조의 모스 트랜지스터의 단면도.1 is a cross-sectional view of a MOS transistor of an LDD structure formed according to the prior art.
제2a도 내지 제2e도는 본 발명의 일 실시예에 따른 모스 트랜지스터 제조 공정 단면도.2A to 2E are cross-sectional views of a MOS transistor manufacturing process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 필드 산화막21 silicon substrate 22 field oxide film
23 : 게이트 산화막 24 : 도핑된 폴리실리콘막23 gate oxide film 24 doped polysilicon film
25 : 감광막 패턴 26 : N-영역25 photosensitive film pattern 26 N - region
27 : 산화막 스페이서 28 : N+영역27: oxide spacer 28: N + region
29 : 질화막 스페이서 30 : 트렌치29 nitride film spacer 30 trench
31 : 실리사이드막31: silicide film
본 발명은 반도체 제조 분야에 관한 것으로, 특히 모스 트랜지스터 제조방법에 관한 것이며, 더 자세히는 LDD(Lightly Doped Drain) 구조의 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a MOS transistor having a lightly doped drain (LDD) structure.
반도체 장치의 고집적화에 따라 소자 크기 및 셀 영역의 감소가 수반되고 있으며, 이에 따라 모스 트랜지스터의 채널이 짧아지고 있다. 그리고, 채널 길이가 짧아짐에 따라 소위 단채널 효과가 문제점으로 대두되고 있다.The high integration of semiconductor devices is accompanied by reductions in device size and cell area, resulting in shortening of channels of MOS transistors. As the channel length becomes shorter, so-called short channel effects have become a problem.
일반적으로, P형 채널 소자보다는 N형 채널 소자에서 드레인 접합에 대한 세심한 배려가 필요한데, 이는 실리콘 내에서 전자가 정공보다 충돌 이온화율(impact ionization rate)이 더 크고, 전자가 기판(Si)-게이트 산화막(SiO2) 계면에서 산화막 내로 주입되는 에너지 장벽이 더 낮으며, 또한 전자가 더 작은 전장에서 표류속도의 포화(draft velocity saturation) 상태에 도달하기 때문이다.In general, careful consideration of drain junctions is required in N-type channel devices rather than in P-type device devices, where electrons have a higher impact ionization rate than holes in silicon and electrons (Si) -gates. This is because the energy barrier injected into the oxide film at the oxide (SiO 2 ) interface is lower, and electrons reach a draft velocity saturation state at a smaller electric field.
따라서, 고전장 효과는 N채널 소자의 동작과 신뢰성에 더욱 유해하게 된다. 소자의 노쇠(degradation) 현상은 캐리어가 10keV/㎝ 이상의 전장 영역을 지나감에 따라 캐리어가 가열되는 현상과 관련이 있으므로 드레인 접합 끝부분의 전장을 줄이는 것이 N채널 소자에 필수적으로 요구된다.Therefore, the high field effect becomes more detrimental to the operation and reliability of the N-channel element. Degradation of the device is related to the heating of the carrier as the carrier passes over the electric field of 10 keV / cm or more, so it is essential for the N-channel device to reduce the electric field at the end of the drain junction.
LDD(Lightly Doped Drain) 구조의 소자에 있어서, 핫 캐리어(hot carrier) 저항과 전류인가 용량은 N형 불순물 영역의 불순물 농도에 의존적이다. N형 불순물 영역의 불순물 농도가 최적치보다 클 때에는 드레인 접합 끝부분의 전기장은 충분히 작아지지 않게 되고, 반면에 작을 때에는 게이트 산화막에 포획된 핫 캐리어에 기인한 음전하에 의해 표면공핍이 유도되어 소자를 노화시키게 되는 것이다. N형 불순물 영역의 불순물 농도가 증가함에 따라 드레인 포화전류도 증가하게 되는데, 이는 N형 불순물 영역에서의 기생 직렬 저항이 줄어들기 때문이다. 결국, 핫 캐리어에 의한 소자의 노화 현상은 주로 드레인 전극 부근의 게이트 산화막에서 생성되는 계면상태(interface state)에 따라 발생되고, 이는 문턱전압의 증가, 이동도의 감소, 드레인 전류의 감소 등을 유발하게 되므로 이에 대한 적절한 해결 방법이 요구된다.In a device having a lightly doped drain (LDD) structure, the hot carrier resistance and the current application capacitance are dependent on the impurity concentration of the N-type impurity region. When the impurity concentration in the N-type impurity region is larger than the optimum value, the electric field at the end of the drain junction does not become small enough, whereas when it is small, surface depletion is induced by negative charges due to hot carriers trapped in the gate oxide film, thereby aging the device. It is to be made. As the impurity concentration in the N-type impurity region increases, the drain saturation current also increases because the parasitic series resistance in the N-type impurity region decreases. As a result, the aging phenomenon of the device due to the hot carrier is mainly caused by the interface state generated in the gate oxide film near the drain electrode, which causes an increase in the threshold voltage, a decrease in mobility, and a decrease in the drain current. Therefore, an appropriate solution is required.
첨부된 도면 제1도는 종래기술에 따라 형성된 LDD 구조의 모스 트랜지스터의 단면을 도시한 것으로, 이를 참조하여 그 제조 공정을 간략히 살펴본다.1 is a cross-sectional view of a MOS transistor having an LDD structure formed according to the prior art, and a brief description of the manufacturing process will be made with reference to the drawing.
우선, 실리콘 기판(1)의 소정 부분에 필드 산화막(2)을 성장시키고, 게이트 산화막(3), 도핑된 폴리실리콘막(4)을 차례로 형성한 다음, 사진 및 식각 공정을 진행하여 게이트 전극을 형성한다. 계속하여, 이온주입을 실시하여 N-영역(5)을 형성하고, 게이트 전극 측벽에 산화막 스페이서(6)를 형성한 다음, 이온주입을 실시하여 N+영역(7)을 형성한다. 끝으로, 노출된 게이트 전극 상부 및 실리콘 기판(1)상의 N+영역(7) 표면에 선택적인 실리사이드막(8)을 형성한다.First, the field oxide film 2 is grown on a predetermined portion of the silicon substrate 1, the gate oxide film 3 and the doped polysilicon film 4 are sequentially formed, and then the gate electrode is formed by performing a photo and etching process. Form. Subsequently, ion implantation is performed to form the N − region 5, an oxide film spacer 6 is formed on the sidewall of the gate electrode, and ion implantation is then performed to form the N + region 7. Finally, an optional silicide film 8 is formed over the exposed gate electrode and on the surface of the N + region 7 on the silicon substrate 1.
그런데, 상기와 같은 공정을 통해 형성된 종래의 모스 트랜지스터는 전술한 바와 같이 핫 캐리어에 의한 노화 현상과, 그에 따른 문턱전압의 증가, 캐리어 이동도의 감소, 드레인 전류의 감소 등의 문제점을 수반하고 있다.However, as described above, the conventional MOS transistor formed through the above process has the problems of aging caused by hot carriers, an increase in threshold voltage, a decrease in carrier mobility, and a decrease in drain current. .
상기와 같은 종래기술의 문제점을 해결하기 위하여, 본 발명은 얕은 접합을 가지며, 채널 길이를 확보할 수 있는 모스 트랜지스터 제조방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art as described above, an object of the present invention is to provide a MOS transistor manufacturing method having a shallow junction, the channel length can be secured.
상기 목적을 달성하기 위하여, 본 발명의 모스 트랜지스터 제조방법은 소자 분리막이 형성된 반도체 기판 상에 게이트 절연막 및 게이트 전도막을 차례로 형성하는 제1단계; 게이트 전극 형성용 마스크를 사용하여 상기 게이트 전도막을 선택 식각하되, 상기 게이트 전도막의 일부를 잔류시키는 제2단계; 상기 제2단계 수행 후, 전체구조 상부에 제1절연막을 형성하고, 상기 제1절연막을 전면 식각하여 제1게이트 측벽 스페이서를 형성하는 제3단계; 상기 게이트 측벽 스페이서를 이온주입 마스크로 사용하여 제1소오스/드레인 이온주입 영역을 형성하는 제4단계; 상기 제1게이트 측벽 스페이서를 덮는 제2게이트 측벽 스페이서를 형성하는 제5단계; 상기 제2게이트 측벽 스페이서 및 상기 소자 분리막을 식각 마스크로 사용하여 상기 제1소오스/드레인 이온 주입 영역의 일부를 식각하여 트렌치를 형성하는 제6단계; 및 상기 트렌치 내부에 금속원소를 포함하는 전도막을 형성하는 제7단계를 포함한다.In order to achieve the above object, the MOS transistor manufacturing method of the present invention comprises a first step of sequentially forming a gate insulating film and a gate conductive film on a semiconductor substrate on which the device isolation film is formed; Selectively etching the gate conductive layer using a mask for forming a gate electrode, and leaving a portion of the gate conductive layer remaining; A third step of forming a first insulating layer on the entire structure after the second step and forming a first gate sidewall spacer by etching the entire surface of the first insulating layer; A fourth step of forming a first source / drain ion implantation region using the gate sidewall spacer as an ion implantation mask; A fifth step of forming a second gate sidewall spacer covering the first gate sidewall spacer; Forming a trench by etching a portion of the first source / drain ion implantation region using the second gate sidewall spacer and the device isolation layer as an etching mask; And a seventh step of forming a conductive film including a metal element in the trench.
이하, 첨부된 도면 제2a도 내지 제2e도를 참조하여 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings 2A to 2E.
먼저, 제2a도에 도시된 바와 같이 실리콘 기판(21)에 필드 산화막(22)을 형성하고, 50 내지 150Å 두께의 게이트 산화막(23)과, 500 내지 1500Å 두께의 도핑된 폴리실리콘막(24)을 차례로 형성한다. 계속하여, 게이트 전극 형성을 위한 감광막 패턴(25)을 식각 마스크로 사용하여 도핑된 폴리실리콘막(24)을 건식 식각한다. 이때, 건식 식각은 소오스/드레인 영역 상에 50 내지 100Å의 폴리실리콘막(24)이 잔류되도록 타겟을 설정하여 실시한다.First, as shown in FIG. 2A, a field oxide film 22 is formed on the silicon substrate 21, a gate oxide film 23 having a thickness of 50 to 150 microseconds, and a doped polysilicon film 24 having a thickness of 500 to 1500 microseconds. Form in turn. Subsequently, the doped polysilicon film 24 is dry-etched using the photosensitive film pattern 25 for forming the gate electrode as an etching mask. At this time, the dry etching is performed by setting the target so that the polysilicon film 24 of 50 to 100 상 에 remains on the source / drain region.
이어서, 감광막 패턴(25)을 제거한 다음, 제2b도에 도시된 바와 같이 게이트 전극의 양쪽으로 소정의 각도로 기울여서 2회의 P(인) 이온주입을 실시하여 N-영역(26)을 형성한다. 이때, 이온주입은 50 내지 80keV의 이온주입 에너지, 1×1012내지 1×1015원자/㎠의 도즈량으로 실시한다.Subsequently, the photoresist pattern 25 is removed, and then two P (phosphorus) ions are implanted at both sides of the gate electrode at a predetermined angle as shown in FIG. 2B to form the N − region 26. At this time, ion implantation is carried out with an ion implantation energy of 50 to 80 keV and a dose amount of 1 × 10 12 to 1 × 10 15 atoms / cm 2.
계속해서, 제2c도에 도시한 바와 같이 전체구조 상부에 1000 내지 2000Å 두께의 TEOS 산화막을 증착하고 이를 전면 건식 식각하여 게이트 전극 측벽 부분에 산화막 스페이서(27)를 형성한다. 이때, 도핑된 폴리실리콘막(24) 상부에 100Å 내외의 TEOS 산화막이 잔류되도록 할 수도 있다. 이 경우, 잔류된 TEOS 산화막이 후속 건식 식각시에 게이트 전극 보호막으로 작용하게 된다. 계속하여, 50 내지 80keV의 이온주입 에너지와, 1×1014내지 1×1018원자/㎠의 도즈량으로 As(비소) 이온주입을 실시하여 N+영역(28)을 형성한다.Subsequently, as shown in FIG. 2C, a TEOS oxide film having a thickness of 1000 to 2000 micrometers is deposited on the entire structure, and dry etching is performed on the entire surface to form an oxide spacer 27 on the sidewall portion of the gate electrode. At this time, the TEOS oxide film of about 100 kV may be left on the doped polysilicon film 24. In this case, the remaining TEOS oxide film serves as a gate electrode protective film during subsequent dry etching. Subsequently, As (arsenic) ion implantation is performed at an ion implantation energy of 50 to 80 keV and a dose amount of 1x10 14 to 1x10 18 atoms / cm 2 to form the N + region 28.
이어서, 제2d도에 도시된 바와 같이 전체구조 상부에 500 내지 1000Å 두께의 질화막을 증착하고, 이를 전면 건식 식각하여 산화막 스페이서(27)를 덮는 질화막 스페이서(29)를 형성한 다음, 필드 산화막(22) 및 질화막 스페이서(29)를 식각 마스크로 사용하여 도핑된 폴리실리콘막(24) 및 실리콘 기판(21)을 건식 식각함으로써 트렌치(30)를 형성한다. 이때, 게이트 전극을 이루는 도핑된 폴리실리콘막(24) 상부의 일부가 함께 식각되어 이후 실리사이드 공정시의 마진을 확보할 수 있게 된다.Subsequently, as illustrated in FIG. 2D, a nitride film having a thickness of 500 to 1000 에 is deposited on the entire structure, and the surface is dry-etched to form the nitride spacer 29 covering the oxide spacer 27, and then the field oxide layer 22. And the doped polysilicon film 24 and the silicon substrate 21 by dry etching using the nitride film spacer 29 as an etching mask. In this case, a portion of the upper portion of the doped polysilicon layer 24 forming the gate electrode may be etched together to secure a margin during the subsequent silicide process.
끝으로, 제2e도에 도시된 바와 같이 노출된 실리콘 기판(21) 및 게이트 전극을 이루는 폴리실리콘막(24) 상에 선택적인 실리사이드막(31)을 형성한다.Finally, as illustrated in FIG. 2E, an optional silicide film 31 is formed on the exposed silicon substrate 21 and the polysilicon film 24 constituting the gate electrode.
상기와 같이 이루어지는 본 발명은 얕은 접합 깊이를 가지며, 셀 영역을 증가시키지 않으면서 채널 길이를 확보하는 LDD 구조의 모스 트랜지스터를 형성함으로써 문턱전압의 증가, 이동도의 감소, 드레인 전류 감소 등의 문제점을 개선하는 효과가 있으며, 이로 인하여 반도체 장치의 신뢰도를 향상시킬 수 있다.The present invention as described above has a shallow junction depth, and by forming a MOS transistor of the LDD structure to secure the channel length without increasing the cell area, there is a problem such as increasing the threshold voltage, reduced mobility, reduced drain current, etc. There is an effect to improve, thereby improving the reliability of the semiconductor device.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백한 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It is obvious to one with ordinary knowledge.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100438665B1 (en) * | 1996-12-30 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for manufacturing embedded memory device using dual insulating spacer with different etching selectivity |
| KR100885787B1 (en) * | 2006-10-31 | 2009-02-26 | 주식회사 하이닉스반도체 | Manufacturing method of nonvolatile memory device |
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1994
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100438665B1 (en) * | 1996-12-30 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for manufacturing embedded memory device using dual insulating spacer with different etching selectivity |
| KR100885787B1 (en) * | 2006-10-31 | 2009-02-26 | 주식회사 하이닉스반도체 | Manufacturing method of nonvolatile memory device |
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