JP2001256060A - Control equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a CPU possible to perform other processing even when external interruption input is generated by exceeding its specification. SOLUTION: In this control equipment with the CPU 2 to perform a control operation so that an external interruption processing 14 is put before other processings 11, 12, the CPU can perform other processings even when the external interruption input is generated by exceeding the specification by starting the external interruption processing in accordance with the external interruption input, inhibiting the external interruption input exceeding the specification during inhibition time of external interruption in fixed time and afterward by inhibiting the external interruption processing for the fixed time and enabling the other processings even in the inhibition time of the external interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device such as a counter and a timer, and more particularly, to a control device having a CPU for performing a control operation so that an external interrupt process has priority over other processes.

[0002]

2. Description of the Related Art In a CPU of this type of counter,
When there is an external interrupt input, processing for the external interrupt input (external interrupt processing) is given priority over other processing, such as main processing such as display and key operation, and timer interrupt processing. There is something.

[0003]

In the above-described counter, specifications are applied to the external interrupt processing, other processing such as main processing and timer interrupt processing.

Therefore, in such a counter, when an external interrupt input exceeding its specification is continuously generated, other processing such as main processing such as display update and key processing cannot be performed. Is not updated, the key operation becomes ineffective, the timer cannot be interrupted, and the CPU runaway detection processing cannot be performed.

Accordingly, the present invention provides a control device in which an external interrupt takes precedence over another process so that the CPU can perform another process even if an external interrupt input exceeding its specification occurs. It is a common issue to be solved.

[0006]

(1) The first control device of the present invention is a control device including a CPU that performs a control operation so that an external interrupt process has priority over other processes.
Starts external interrupt processing in response to an external interrupt input, and prohibits external interrupt processing for a certain period of time, thereby prohibiting external interrupt input exceeding the specification for a certain period thereafter. Other processes can be executed within the fixed time.

According to the first aspect of the present invention, since an external interrupt input is continuously generated beyond its specification and the CPU can perform other processing even when the external interrupt is present, the CPU can perform the external interrupt operation as in the prior art. By giving priority to the processing, for example, in the case of a counter, the display of the count value is not updated due to an external interrupt input exceeding its specification, and the display of the count value remains stopped or the key operation becomes ineffective, etc. It becomes an easy counter.

(2) The second control device of the present invention includes a CPU which controls the external interrupt processing to take priority over the timer interrupt processing and to perform a CPU runaway detection processing periodically in the timer interrupt processing. Control equipment provided with the CPU
The runaway detection process is enabled not only in the timer interrupt process but also in the external interrupt process.

According to the second aspect of the present invention, for example, when a CPU runaway detection process is periodically performed by refreshing a watchdog timer by a timer interrupt, when there is an external interrupt input, a process for the external interrupt input is performed. , The watchdog timer can be refreshed in the external interrupt processing even if the priority is given to the timer interrupt, so that the CPU runaway detection is not performed erroneously, and the counter becomes easy for the user to use.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments showing details of the present invention.

In this embodiment, the present invention is applied to a counter as a control device. However, the present invention can be similarly applied to other control devices such as a timer.

FIGS. 1 to 4 relate to an embodiment of the present invention, and FIG. 1 is an overall circuit diagram of a counter according to the present embodiment.
FIG. 2 is a circuit diagram functionally showing the inside of the CPU of FIG. In FIG. 2, the CPU is described in terms of hardware, but is actually software that performs a program operation. FIG. 3 is a program flowchart for explaining the operation of the CPU, and FIG. 4 is a timing chart for explaining the operation of the CPU.

Referring to FIGS. 1 and 2, the counter 1 comprises a CPU 2, a display circuit 3 for processing data from the CPU 2 for display, an LCD and an LED, etc., and responds to a display input from the display circuit 3. Display unit 4 that performs display operation
A key input 5 for performing input corresponding to a plurality of externally operated keys, an input circuit 6 for processing a signal input from a sensor (not shown) or the like and inputting it to the CPU 2 as an external interrupt input; The data is processed into data for communication with an external communication device such as a personal computer, and vice versa.
A communication circuit 7 for inputting to the PU 2, an output circuit 8 for processing data from the CPU 2 and outputting the processed data to a device such as a relay, and an EEPRO for storing data from the CPU 2
M9.

Each of the above-described units is appropriately selected for the counter 1 except for the CPU 2 and the input circuit 6. Reference numeral 10 denotes a power supply for the counter 1.
Of course, the power supply 10 may be built in the counter 1.

The CPU 2 serves as a main processing section 11 for controlling processing of the respective sections, for example, updating the display on the display section 4, processing a key signal from the key input 5, and controlling the communication circuit 7.
Communication processing with an external communication device via the output circuit 8, output processing to a device such as a relay via the output circuit 8, and the like. The watchdog timer 13 is periodically refreshed in the timer interrupt processing. When the watchdog timer 13 is not refreshed in the timer interrupt processing unit 12, the runaway detection processing is performed if the CPU 2 is running away. It has a basic processing function to perform.

The CPU 2 also has an external interrupt processing unit 14 which has priority over the above-mentioned processes and which has priority over other processes when there is an external interrupt input from the input circuit 6.

When there is an external interrupt input, the CPU 2 causes the external interrupt processing unit 14 to start counting the external interrupt prohibition time (T + t) as a fixed time for the timer 15. When the counting of the external interrupt prohibition time (T + t) by the timer 15 ends, the timer 15 causes the external interrupt processing unit 14 to input an external interrupt permission.

In this case, the timer 15 is started via the external interrupt processing unit 14 in response to the external interrupt input, but the timer 15 is started directly from the external interrupt input as shown by a broken line A. You may make it do.

The timer 15 is built in the CPU 2, but may be a timer 15a external to the CPU 2.

The watchdog timer 13 is refreshed by the timer interrupt processing unit 12, but may be refreshed by the external interrupt processing unit 14.

Referring to FIG. 3 and FIG. 4, the operation of the CPU 2 will be described focusing on the external interrupt processing. CPU2
Before describing the operation of the first embodiment, the specification regarding the external interrupt input processing of the counter 1 of the embodiment will be described. In the specification of the counter 1, the external interrupt input is input to the CPU 2 via the input circuit 6 at a frequency interval of 5 kHz. It is supposed to be. Actually, it is assumed that an external interrupt input having a frequency exceeding 5 kHz, such as noise exceeding its specification, is input to the counter 1. That is, in the case of an external interrupt input of 5 kHz, even if the external interrupt processing has priority over the main processing or the timer interrupt processing, the CPU runaway detection processing by the watchdog timer in the main processing or the timer interrupt processing is possible. .

In the embodiment, 5 exceeding the specification of the counter 1
It is assumed that an external interrupt input having a frequency exceeding kHz is input to the CPU 2. Hereinafter, processing of an external interrupt input exceeding the specification will be described.

FIG. 4A shows the state of the CPU 2 via the input circuit 6.
When an external interrupt input... Exceeding the specification is input, the CPU 2 executes the external interrupt processing flow and the timer processing flow shown in FIG.

That is, in the external interrupt processing flow,
When the external interrupt process is started in step n1, the CPU 2 responds to the input of the external interrupt input in step n1.
By prohibiting the external interrupt in step 2, the input of other external interrupt inputs is prohibited.

Then, in step n3, the CPU 2 starts the timer 15 to count the external interrupt prohibition time (T + t), and performs an external interrupt process in step n4.

Here, the time T is an external interrupt processing time as shown in FIG.
Is an additional time required for other processing such as main processing and CPU runaway detection processing as shown in FIG.

When the timer 15 starts and the external interrupt processing time T elapses, the external interrupt processing ends at step n5.

Within this external interruption processing time T, the CPU 2 may perform the CPU runaway detection processing by refreshing the watchdog timer 13 or the like.

After starting the timer 13, the CPU 2 starts the timer processing in the timer processing flow in step n6. When the timer process starts, it is determined in step n7 whether or not the external interrupt inhibition time (T + t) has elapsed. If not, the process proceeds to step n9.
When the time has elapsed, the external interrupt input is permitted in step n8, and then the process proceeds to step n9.

In step n9, a timer process such as a main process and a CPU runaway detection process is performed. When the timer process ends, the timer process flow ends in step n10.

[0031]

According to the first aspect of the present invention, even if an external interrupt input occurs beyond its specification, the CPU can perform other processing, so that an external interrupt input exceeding its specification is continuously generated. Also,
Since the CPU can perform other processing, for example, main processing such as display updating and key processing, as in the conventional case, for example, in the case of a counter, the display of the count value is not updated due to an external interrupt input exceeding its specification and stopped. It is possible to eliminate the problem that the key operation is not performed or that the key operation is not effective, so that the user can easily use the counter.

According to the second aspect of the present invention, for example, when the CPU runaway detection process is periodically performed by refreshing the watchdog timer by a timer interrupt, when there is an external interrupt input, and when there is an external interrupt input, Even if the process has priority over the timer interrupt, the watchdog timer can be refreshed in the external interrupt process, so that the CPU runaway detection is not performed erroneously, and the counter is easy for the user to use.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of a counter according to an embodiment.

FIG. 2 is an internal circuit diagram of the CPU of FIG. 1;

FIG. 3 is a program flowchart for explaining the operation of a CPU.

FIG. 4 is a timing chart for explaining the operation of the CPU;

[Explanation of symbols]

 1 Counter 2 CPU 11 Main processing 12 Timer interrupt processing 13 Watchdog timer 14 External interrupt processing 15 Timer

Claims (2)

[Claims] 1. A control device comprising a CPU that performs a control operation so that an external interrupt process has priority over another process, wherein the CPU starts an external interrupt process in response to an external interrupt input, and performs a predetermined process. Time, by prohibiting external interrupt processing, prohibiting external interrupt input exceeding the specification for the fixed time thereafter, enabling the other processing to be executed within the fixed time, A control device characterized by that: 2. A control device comprising: a CPU that performs a control so that an external interrupt process has priority over a timer interrupt process and periodically performs a CPU runaway detection process in the timer interrupt process. A control device wherein runaway detection processing is enabled not only in the timer interrupt processing but also in the external interrupt processing.