JPH08194570A - Key scanning circuit - Google Patents

Abstract

PURPOSE: To reduce erroneous key recognitions due to chattering by suppressing the current consumption in the key scan circuit which detects the state of the key. CONSTITUTION: An interruption judgement/generation circuit 4 judges when which key is pushed, during it is being pushed, and when it is left based on the input line state of m pieces of key matrix 3 and generates an interruption signal for each state. An interruption status circuit 5 is provided with information on permitting and inhibiting the generation of interruption signals, information on timer control which is built in the circuit 4, information on releasing the interruption signal, and information on recognizing the state of the interruption signal. Thus, the key scanning is performed only when the interruption signal is generated and the consumption current is suppressed as possible. The interruption signal is generated periodically by using a timer so as to perform key scanning, resulting in eliminating the influence of the chattering of a switch part and improving the reliability of scanning.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key scan circuit used in a telephone or the like, and particularly to a key scan circuit which is effective in reducing power consumption and in a device in which chattering in a switch portion having a key matrix structure is a problem. Regarding the scan circuit.

[0002]

2. Description of the Related Art In a conventional key scan circuit, in order to determine that a key in a key matrisk is pressed,
The key scan was performed regularly, and a specific current was constantly consumed (see FIG. 3). In addition, the key may be erroneously recognized due to chattering in the switch unit having the key matrix configuration.

A conventional key scan circuit will be described below with reference to the drawings. FIG. 4 is a block diagram of a conventional key scan circuit. In FIG. 4, reference numeral 7 is a shift register having n outputs and 8 is an input latch circuit having m inputs. The shift register 7 and the input latch circuit 8 constitute an n × m key matrix 12. Reference numeral 9 is a pulse generating circuit, which is a shift register 7 and an input latch circuit 8.
The pulse signal is sent to the counter 10 as well as to the counter 10. A determination circuit 11 determines the output of the counter 10 and the output of the input latch circuit 8 and outputs output data and a signal indicating that a key has been pressed.

The operation of the conventional key scan circuit configured as described above will be described below with reference to FIG. First, only one of n outputs of the shift register 7 is active, and the other n-1 lines are non-active. The output of this active state is sequentially shifted using the output of the pulse generation circuit 9, and the states of m input lines intersecting the output line of the active state are input to the input latch circuit 8. In addition, the output of the pulse generating circuit 9 is also input to the counter 10 and the key matrix 12
It counts which of the n output lines of is active. The determination circuit 11 determines which key of the key matrix 12 is pressed from the output of the counter 10 and the output of the input latch circuit 8 and outputs it as data and also outputs a key press signal (interrupt signal to CPU).

[0005]

However, in the above-described operation, the key scan operation (see FIG. 3) is regularly performed even when no key is pressed, and the key matrix is constructed. Only after all the switch parts have been scanned, it is judged that no key is pressed. That is, it is necessary to periodically perform the key scan operation even when the key is not pressed (in most cases), so that a specific current is always consumed. When used in a device which is expected to have low power consumption such as a battery-powered portable device, the current consumption becomes a problem. Further, since chattering occurs in the switch part having the key matrix configuration (see FIG. 3), if one key scan operation immediately after pressing the key overlaps with the chattering period, which key is pressed due to the influence. There was also a problem of misrecognizing when judging.

The present invention solves the above problems and provides a key scan circuit which can minimize the current to be discharged and can eliminate the influence of chattering in the switch section to improve the reliability of scanning. To aim.

[0007]

In order to solve the above-mentioned problems, the key scan circuit according to the present invention operates in a key scan operation when a key is not pressed in order to minimize current consumption due to the key scan operation. Stop and generate an interrupt signal for each state when one of the keys is pressed, while it is being pressed, and when it is released.
U is recognized, and the key scan operation is performed only when an interrupt signal is generated while the key is pressed. Also, in order to prevent erroneous recognition of the key due to chattering of the switch section when the key is pressed, an internal timer is provided During this period, the CPU performs a key scan operation by software by periodically generating an interrupt signal to the CPU at a preset time interval of the timer (time in consideration of chattering time). It is the one.

[0008]

Therefore, in the circuit according to the present invention, the signal in the circuit does not change in the key input waiting state, and the consumed current is suppressed to the minimum. Further, in consideration of chattering time having different characteristics for each switch, a timer that can be set arbitrarily performs scanning after generating a periodic interrupt signal, so that there is little risk of malfunction due to chattering.

[0009]

1 is a block diagram of a key scan circuit according to an embodiment of the present invention. A configuration example of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an output n key scan register, 2 is an input m key sense register, and the key scan register 1 and the key sense register 2 form an n × m key matrix 3. Composed. Reference numeral 4 denotes an interrupt determination / generation circuit, which determines from the state of the m input lines of the key matrix 3
When any one of the keys is pressed, while the key is pressed, and when the key is released, an interrupt signal is generated for each state. Reference numeral 5 denotes an interrupt status circuit, which is information indicating permission / prohibition of interrupt signal generation, information indicating control of a timer provided in the interrupt determination / generation circuit 4, information indicating cancellation of the interrupt signal, and an interrupt signal It has information for recognizing the state. Reference numeral 6 is a pull-up resistor for m input lines.

The operation of the above configuration will be described below with reference to the timing chart of the key scan process of FIG. By allowing the interrupt status circuit 5 of FIG. 1 to generate a push interrupt signal (FIG. 2: push interrupt enable flag ON state), the interrupt determination / generation circuit 4 enables a push interrupt generation state (waiting for key input). become.

In the key input waiting state, all n output lines from the key scan register 1 are active. When any key is pressed here, one of the m input lines to the key sense register 2 becomes active, the interrupt judgment / generation circuit 4 judges that the key has been pressed, and the CPU Generates a push interrupt signal (Fig. 2: push interrupt signal).

The CPU receives this push interrupt signal and starts software processing. The interrupt status circuit 5 reads the information indicating the state of the push interrupt signal, and recognizes that the signal generated by the interrupt determination / generation circuit 4 is the push interrupt signal. Subsequently, the interrupt status circuit 5 is written with data to prohibit the generation of a key press interrupt signal by another key in the interrupt determination / generation circuit 4 (hereinafter, until another key press interrupt signal generation is enabled, another key Generation of push interrupt signal is prohibited Fig. 2: Push interrupt enable flag is OFF state and generation of timer interrupt signal is permitted (timer interrupt signal can be generated in the interrupt judgment / generation circuit 4) Fig. 2: Timer Interrupt enable flag O
After N state), the timer start information is activated (Fig. 2:
Set the timer start flag to ON) and clear the push interrupt signal.

When the timer start information becomes active, the timer in the interrupt determination / generation circuit 4 is started, and the timer time interval (time interval considering the chattering of the switch) set in advance is set to a constant time. After that, a timer interrupt signal (FIG. 2: timer interrupt signal) is generated for the CPU.

The CPU receives this timer interrupt signal and starts software processing. The interrupt status circuit 5 reads the information indicating the state of the timer interrupt signal, and recognizes that the signal generated by the interrupt determination / generation circuit 4 is the timer interrupt signal. Then, the CPU performs a key scan process (writes data to the key scan register 1 and sequentially activates one of n output lines one by one, and the state of the key switches arranged in a matrix is changed from the key sense register 2 to The key code is memorized by reading each time) and the key code is stored.
After that, data is written to the interrupt status circuit 5, and generation of a timer interrupt signal in the interrupt determination / generation circuit 4 is prohibited (prohibition of generation of a timer interrupt signal in the interrupt determination / generation circuit 4. FIG. 2: timer The interrupt enable flag is turned off), and the generation of the key release interrupt signal is enabled (the interrupt determination / generation circuit 4 can generate the release interrupt signal. Fig. 2: the release interrupt enable flag is turned on), and the timer interrupt signal is turned on. clear.

By allowing the generation of the key release interrupt signal, the key release waiting state is entered. When the key is released, the interrupt determination / generation circuit 4 generates a release interrupt signal (FIG. 2: release interrupt signal) to the CPU.

The CPU receives this separation interrupt signal and starts software processing. The interrupt status circuit 5 reads the information indicating the state of the separation interrupt signal and recognizes that it is the separation interrupt signal. Subsequently, data is written to the interrupt status circuit 5 to inhibit the generation of the key release interrupt signal (prohibit the generation of the release interrupt signal in the interrupt determination / generation circuit 4. FIG. 2: release interrupt enable flag OFF state),
After enabling the generation of the key press interrupt signal (the press interrupt signal can be generated in the interrupt determination / generation circuit 4. Fig. 2: the press interrupt enable flag is ON), the key release interrupt signal is cleared to the initial state ( Wait for key input).

Further, as another usage example, the timer scanning signal is not limited to being generated once while the key is being pressed, but is generated n times, so that the key scanning process is also performed n times. It is also possible to make such software.

The above-mentioned embodiment shows an example of the present invention, and the present invention should not be limited to this.

[0019]

As described above, according to the present invention, the key scan operation is performed only when the timer interrupt signal is generated while the key is being pressed, so that the current consumption can be minimized as compared with the prior art. You can Furthermore, since the key scan operation is performed at fixed time intervals (which can be arbitrarily determined) by the timer interrupt signal, chattering of the switch unit can be eliminated (see FIG. 2), and the reliability of scanning can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a key scan circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of hardware processing and software processing in the key scan circuit according to the embodiment of the present invention.

FIG. 3 is a comparison diagram of a conventional key scan operation interval and a key scan operation interval according to the present invention.

FIG. 4 is a block diagram of a conventional key scan circuit.

[Explanation of symbols]

 1 Key scan register 2 Key sense register 3 Key matrix 4 Interrupt judgment / generation circuit 5 Interrupt status circuit 6 Pull-up resistor

Claims (2)

[Claims] 1. A key scan circuit for detecting a key state, wherein an interrupt determination is made to generate an interrupt signal for each state when any key is pressed, while being pressed, and when being released. / Generating circuit, and an interrupt status circuit having information indicating the state of the interrupt signal and information indicating permission / prohibition of generation of the interrupt signal, and only when the interrupt signal is generated while the key switch is pressed. A key scan circuit characterized by performing a key scan operation. 2. The interrupt determination / generation circuit is provided with a timer internally so that an interrupt signal can be generated periodically while a key switch is being pressed, and the time of the timer can be arbitrarily set. The key scan circuit according to claim 1, which is characterized in that.