JP2001249361A - Electro-optical device, method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

(57) [Problem] To provide an electro-optical device such as an active matrix driving type liquid crystal device even if the pixel pitch is reduced.
A sufficient storage capacitance can be added to a pixel electrode, and the diameter of a contact hole leading to the pixel electrode can be reduced. A liquid crystal device includes a TFT array substrate (10).
The TFT (30), the data line (6a), and the scanning line (3
a), a capacitor line (3b) and a pixel electrode (9a).
The pixel electrode and the TFT are electrically connected by two contact holes (8a, 8b) via the barrier layer (80). Part of the semiconductor layer and the capacitance line sandwich the first dielectric film (2) to form a first storage capacitor (70a), and part of the capacitance line and the barrier layer form the second dielectric film (81). The second storage capacitor (70b) is sandwiched therebetween.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device of an active matrix driving system and a method of manufacturing the same, and more particularly, to a device for providing a storage capacitor for adding a storage capacitor and for switching a pixel electrode and a pixel. Thin Film Transistor:
The present invention belongs to the technical field of an electro-optical device including a conductive layer called a barrier layer for obtaining good electrical conduction between the device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in an electro-optical device of an active matrix driving system by TFT driving, a large number of scanning lines and data lines arranged vertically and horizontally and a large number of TFTs corresponding to their intersections are formed on a TFT array substrate. It is provided in. In each TFT, a gate electrode is connected to a scanning line, a source region of a semiconductor layer is connected to a data line, and a drain region of the semiconductor layer is connected to a pixel electrode. Here, in particular, since the pixel electrode is provided on various layers constituting the TFT and the wiring and on an interlayer insulating film for insulating the pixel electrode from each other, the pixel electrode is provided through a contact hole formed in the interlayer insulating film. Connected to the drain region of the semiconductor layer forming the TFT. When a scanning signal is supplied to the gate electrode of the TFT via a scanning line, the TFT is turned on, and an image signal supplied to the source region of the semiconductor layer via the data line is supplied to the source-drain of the TFT. It is supplied to the pixel electrode through the space. Supply of such an image signal is performed only for an extremely short time for each pixel electrode via each TFT. For this reason, in order to hold the voltage of the image signal supplied via the TFT which has been turned on for an extremely short time for a much longer time than the time which has been turned on, each pixel electrode is In general, a storage capacitor is formed in parallel with a liquid crystal capacitor. On the other hand, in this type of electro-optical device, a source region and a drain region of a pixel switching TFT and a channel region therebetween are constituted by a semiconductor layer formed on a TFT array substrate. The pixel electrode has a scanning line, a capacitance line,
It is necessary to connect to the drain region of the semiconductor layer via a wiring such as a data line and a plurality of interlayer insulating films for electrically insulating these from each other. Here, especially in the case of a positive stagger type or coplanar type polysilicon TFT having a top gate structure in which a gate electrode is provided on a semiconductor layer when viewed from the TFT array substrate side, particularly from a semiconductor layer to a pixel electrode in a multilayer structure. Is 100, for example.
Since the length is about 0 nm or longer, it is difficult to form a contact hole for electrically connecting the two. More specifically, the etching accuracy is reduced as the etching is performed deeper, and there is a possibility that a hole may be formed through the target semiconductor layer. It is extremely difficult to open the holes. For this reason, dry etching and wet etching are combined, but this time, the diameter of the contact hole becomes large due to wet etching, and it is difficult to lay out wiring and electrodes as necessary in a limited area on the substrate. It becomes difficult.

Therefore, recently, when an electrical contact between a data line and a source region is established by opening a contact hole reaching a source region of a semiconductor layer in an interlayer insulating film formed on a scanning line, A contact hole reaching the drain region of the semiconductor layer is opened to form a relay conductive layer called a barrier layer made of the same layer as the data line on the interlayer insulating film. A technique has been developed for forming a contact hole from a pixel electrode to the barrier layer in an interlayer insulating film formed on the barrier layer. In this way, by electrically connecting the pixel layer to the drain region by relaying the barrier layer formed of the same layer as the data line, it is possible to form a contact hole from the pixel electrode to the semiconductor layer at once. In addition, the contact hole opening step and the like can be facilitated, and the diameter of each contact hole can be reduced.

[0004]

In this type of electro-optical device, there is a strong demand for a higher quality display image, which is achieved by increasing the definition of the image display area or the pixel pitch. And a high pixel aperture ratio (ie, in each pixel, a non-pixel aperture region through which display light does not pass)
It is extremely important to increase the ratio of the pixel opening area through which the display light is transmitted.

However, as the pixel pitch becomes finer, the electrode size, the wiring width, the contact hole diameter, and the like are inherently limited due to the manufacturing technology.
Since the ratio of these wirings and electrodes occupying the image display area is relatively increased, there is a problem that the pixel aperture ratio is reduced.

Further, as the pixel pitch becomes finer as described above, it becomes difficult to make the above-mentioned storage capacitance, which must be formed in a limited area on the substrate, sufficiently large. Here, in particular, according to the technique using the above-described barrier layer, the barrier layer is formed of the same conductive film made of the same Al (aluminum) film as the data line, and thus the barrier layer depends on the position and material of the barrier layer. Therefore, the degree of freedom in opening the contact hole is poor, and it is extremely difficult to use the barrier layer for applications other than the relay function, for example, to increase the storage capacity. However, it is not possible to make the most of each layer in order to simplify the device configuration and increase the efficiency of the manufacturing process. Furthermore, according to this technique, a chemical reaction occurs due to the contact between the Al film constituting the barrier layer and the ITO (Indium Tin Oxide) film constituting the pixel electrode, and the easily ionized Al film is corroded. As a result, the electrical connection between the barrier layer and the pixel electrode is impaired, so that good electrical connection between the first barrier layer made of an Al film and the ITO film can be obtained.
It is necessary to use a high-melting-point metal film such as an i (titanium) film as the second barrier layer, which causes a problem that the layer structure and its manufacturing process are complicated.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and uses a relatively simple structure even if the pixel pitch is reduced, so that a pixel electrode and a thin film transistor are satisfactorily relayed. An object of the present invention is to provide an electro-optical device which can have a configuration and a configuration in which a storage capacity is increased, and is capable of displaying high-quality images, and a method for manufacturing the same.

In order to solve the above-mentioned problems, a first electro-optical device according to the present invention includes a substrate, a plurality of scanning lines and a plurality of data lines, a thin film transistor connected to the scanning line and the data line, and the thin film transistor. An electro-optical device having a pixel electrode and a storage capacitor connected to the first interlayer insulating film formed above the scanning line and one electrode of the storage capacitor; The semiconductor device includes a conductive layer formed above and a second interlayer insulating film formed above the conductive layer, and the data line is formed on the second interlayer insulating film.

According to the first electro-optical device of the present invention, the scanning line and one electrode of the storage capacitor, the first interlayer insulating film, the conductive layer, the second interlayer insulating film, and the data line are formed on the substrate in this order. ing. Therefore, the conductive layer interposed between the scanning line and the data line can be used for various purposes. For example, first, the conductive layer and the semiconductor layer are electrically connected through the first contact hole, and the conductive layer and the pixel electrode are electrically connected through the second contact hole. As a result, a configuration in which the semiconductor layer and the pixel electrode are electrically connected can be realized. Alternatively, by providing a part of the conductive layer as another part of the semiconductor layer or another storage capacitor electrode opposed to one electrode of the storage capacitor via the dielectric film, a storage capacitor is provided to the pixel electrode. A configuration is also possible. Alternatively, by forming the conductive layer from a light-shielding film, a configuration in which at least a part of the opening region of the pixel is defined by the conductive layer is also possible. Further, a structure in which a data line, a scanning line, or another wiring except a capacitor line for forming one electrode of a storage capacitor is formed from the conductive layer, or a redundant structure of the data line, the scanning line, and the capacitor line from the conductive layer. A configuration in which a wiring is formed is also possible.

According to one aspect of the first electro-optical device of the present invention, the substrate further includes a third interlayer insulating film formed above the data line, and the pixel electrode includes The conductive layer is formed on a third interlayer insulating film and is electrically connected to the conductive layer via a contact hole formed in the second and third interlayer insulating films. It is electrically connected.

According to this structure, the pixel electrode is formed above the data line via the third interlayer insulating film.
The pixel electrode is electrically connected to the conductive layer via a contact hole formed in the second and third interlayer insulating films,
The conductive layer is connected to the semiconductor layer. Therefore, a configuration is obtained in which the semiconductor layer and the pixel electrode are electrically connected via the conductive layer.

In order to solve the above-mentioned problems, a second electro-optical device according to the present invention includes: a substrate, a plurality of scanning lines and a plurality of data lines, a thin film transistor connected to each of the scanning lines and each of the data lines; A pixel electrode connected to the thin film transistor, a semiconductor layer forming source and drain regions and a first storage capacitor electrode of the thin film transistor, an insulating thin film formed on the semiconductor layer, and a semiconductor layer formed on the insulating thin film A gate electrode of the thin film transistor that is formed and is part of the scanning line; a second storage capacitor electrode of the storage capacitor formed on the insulating thin film; and a gate electrode of the scanning line and the second storage capacitor electrode. A first interlayer insulating film formed above, a conductive layer formed above the first interlayer insulating film, and a second interlayer insulating film formed above the conductive layer. Ri, the data line, the second
It is formed on an interlayer insulating film and is electrically connected to a source region of the semiconductor layer via a contact hole formed in the insulating thin film and the first and second interlayer insulating films.

According to the second electro-optical device of the present invention, the substrate includes the scanning line and the second storage capacitor electrode, the first interlayer insulating film,
A conductive layer, a second interlayer insulating film, and a data line are formed in this order, and the pixel electrode is further formed thereon. The data line is electrically connected to a source region of the semiconductor layer via a contact hole formed in the first and second interlayer insulating films. In addition to these, a source region and a drain region are formed from part of the semiconductor layer,
A gate insulating film of the thin film transistor is formed from a part of the insulating thin film, and a gate electrode of the thin film transistor is formed on a part of the scanning line on the insulating thin film. On the other hand, a first storage capacitor electrode is formed from a part of the semiconductor layer, a dielectric film of the storage capacitor is formed from a part of the insulating thin film, and further, a part of the capacitor line is formed on the insulating thin film. A second storage capacitor electrode is formed. Therefore, the thin film transistor is arranged below the scanning line, and the
A structure in which the storage capacitor is arranged below the storage capacitor electrode is obtained. Therefore, in a configuration in which such a storage capacitor is provided alongside a thin film transistor, a conductive layer interposed as a layer between a scanning line and a data line can be used for various purposes. For example, first, a part of the conductive layer is
By forming a third storage capacitor electrode opposed to the storage capacitor electrode with the first interlayer insulating film interposed therebetween, that is, the first interlayer insulating film serves as a dielectric film of the storage capacitor at this location, and a part of the conductive layer and the second By arranging the storage capacitor electrode in opposition, it is possible to provide a configuration in which a storage capacitor is additionally provided to the pixel electrode (in addition to the storage capacitor including the first storage capacitor electrode and the second storage capacitor electrode). Alternatively, the first of the present invention described above.
As in the case of the electro-optical device, a configuration in which the semiconductor layer and the pixel electrode are electrically connected via the conductive layer, a configuration in which at least a part of the opening area of the pixel is defined by the conductive layer, , And other wirings other than the capacitance line for forming the second storage capacitor, or a configuration in which these redundant wirings are formed.

According to one aspect of the second electro-optical device of the present invention, the conductive layer is connected to a drain region of the semiconductor layer via a contact hole formed in the first interlayer insulating film and the insulating thin film. It is electrically connected.

According to this structure, the data line is electrically connected to the source region of the semiconductor layer via the contact thin film formed in the insulating thin film and the first and second interlayer insulating films, and The layer is electrically connected to the drain region of the semiconductor layer via a contact hole formed in the first interlayer insulating film and the insulating thin film. Therefore, the configuration in which the conductive layer is used as an electrode of the storage capacitor connected to the pixel electrode can be easily achieved, and at the same time, the configuration in which the pixel electrode and the drain region are electrically connected via the conductive layer is also facilitated. It becomes possible.

According to another aspect of the second electro-optical device of the present invention, the substrate further includes a third interlayer insulating film formed above the data line, and the pixel electrode includes It is formed on the third interlayer insulating film and is electrically connected to the conductive layer via a contact hole formed in the second and third interlayer insulating films.

According to this structure, the pixel electrode is formed above the data line via the third interlayer insulating film.
The pixel electrode is electrically connected to the conductive layer via a contact hole formed in the second and third interlayer insulating films. Therefore, a configuration in which the pixel electrode and the drain region are electrically connected to each other via the conductive layer can be easily achieved.

In order to solve the above-mentioned problems, a third electro-optical device according to the present invention has a plurality of pixel electrodes and thin film transistors arranged in a matrix on a substrate, and a thin film transistor connected to the thin film transistors via an interlayer insulating film. A scanning line and a data line that three-dimensionally intersect are interposed between a semiconductor layer forming the thin film transistor and the pixel electrode, and are electrically connected to a drain region of the semiconductor layer through a first contact hole. A conductive layer electrically connected to the pixel electrode via a second contact hole; a first storage capacitor electrode formed of the same film as the semiconductor layer portion; and a second storage capacitor electrode disposed on the first storage capacitor electrode. A first dielectric film interposed between the storage capacitor electrode and a second dielectric film interposed between the second storage capacitor electrode and a third storage capacitor electrode that is a part of the conductive layer; Obtain.

According to the third electro-optical device of the present invention, a plurality of scanning lines and a plurality of data lines are three-dimensionally intersecting with each other via an interlayer insulating film on a substrate, and a storage capacitor is connected to a plurality of pixel electrodes. Are separately provided. The conductive layer is interposed between the semiconductor layer and the pixel electrode. On the other hand, the conductive layer is electrically connected to the drain region of the semiconductor layer via the first contact hole. They are electrically connected via two contact holes. Therefore, the diameter of the contact hole can be reduced as compared with the case where one contact hole is formed from the pixel electrode to the drain region. That is, since the etching accuracy decreases as the contact hole is opened deeper, dry etching that can reduce the diameter of the contact hole is stopped halfway to prevent punch-through in a thin semiconductor layer, and finally the semiconductor is etched by wet etching. The process must be designed to open the layers. For this reason, the diameter of the contact hole must be increased by wet etching without directivity. On the other hand, in the present invention, it is only necessary to connect the pixel electrode and the drain region of the semiconductor layer by two serial first and second contact holes, so that each contact hole can be opened by dry etching. Or at least the distance for opening by wet etching can be shortened. As a result, the diameter of each of the first and second contact holes can be reduced, and the depressions and irregularities formed on the surface of the conductive layer in the first contact holes can be reduced. Is promoted. Further, since the depressions and irregularities formed on the surface of the pixel electrode in the second contact hole can be small, flattening of the pixel electrode portion is promoted. As a result, defects such as disclination in an electro-optical material such as a liquid crystal due to depressions and irregularities on the pixel electrode surface are reduced.

A first storage capacitor electrode in which the first dielectric film is formed of the same film as the semiconductor layer portion constituting the drain region of the semiconductor layer, and a second storage capacitor electrode disposed on the first storage capacitor electrode The first storage capacitor is added by these three to the pixel electrode electrically connected to the drain region of the semiconductor layer. In addition, since the second dielectric film is interposed between the second storage capacitor electrode and the third storage capacitor electrode formed of a part of the conductive layer, the second storage capacitor is connected to the pixel electrode by these three components. Will be added. Therefore, the first and second conductive layers are connected in parallel above and below the conductive layer.
Is formed. A three-dimensional storage capacitor can be constructed in such a limited area on the substrate. Here, in particular, each of the first and second dielectric films is formed of a dielectric film of a different layer from the second interlayer insulating film interposed between the scanning lines and the data lines that three-dimensionally intersect. Therefore, in order to suppress the parasitic capacitance between the scanning line and the data line which causes a voltage drop of the image signal which causes flicker or the like, these second interlayer insulating films are required to have a certain thickness regardless of the thickness of the second interlayer insulating film. The first and second dielectric films can be made as thin as possible to the technical limit. In the above-described prior art in which a barrier layer (corresponding to a conductive layer in the present invention) is formed from the same conductive layer as the data line, the data line and the scan are formed by using this barrier layer as one electrode of the storage capacitor. Assuming that an interlayer insulating film between lines is used as a dielectric film, this dielectric film needs to have a thickness of about 800 nm so that parasitic capacitance between data lines and scanning lines does not matter. Therefore, it is fundamentally difficult to construct a large-capacity storage capacitor using the barrier layer. On the other hand, according to the present invention, by using a dielectric film that can be configured to be thin, it is possible to extremely efficiently increase the capacitance value of the storage capacitor that is inversely proportional to the thickness of the dielectric film.

Furthermore, since the diameter of the first contact hole can be further reduced by forming the dielectric film thinner in this way, the above-mentioned depressions and irregularities of the conductive layer in the first contact hole can be further reduced. Flattening of the pixel electrode located above it is further promoted. Therefore, defects of the electro-optical material due to the depressions and irregularities in the pixel electrode are reduced, and ultimately higher quality image display is possible.

In the structure of the present invention, the conductive layer and the second dielectric film are replaced by or in addition to the function of adding a storage capacitor in the conductive layer, with emphasis on the light shielding function and the layout of contact holes in the conductive layer. In the case where the second dielectric film is formed over the scanning line, the second dielectric film may be formed so thick that the parasitic capacitance between the conductive layer and the scanning line does not matter. Therefore, in this case, it is difficult to increase the storage capacitance by configuring the second dielectric film as thin as technically possible as described above. However, if a sufficient storage capacity can be added according to the device specifications, it is not necessary to further reduce the thickness of the second dielectric film, so that other additional functions such as the light shielding function of the conductive layer are promoted. It is more advantageous to configure the electro-optical device as a whole. In short, in consideration of the specific device specifications individually, the conductive layer is designed so that the original relay function, the function of adding the necessary storage capacity, and other additional functions such as the light shielding function can be sufficiently exhibited. What is necessary is just to set the planar layout of the conductive layer, the thickness of the second dielectric film, and the like.

In one aspect of the third electro-optical device according to the present invention, the first storage capacitor electrode and the second storage capacitor electrode overlap at least partially via the first dielectric film in plan view, At least a part of the second storage capacitor electrode and the third storage capacitor electrode may be overlapped with the second dielectric film interposed therebetween.

According to this structure, the first and third storage capacitor electrodes are formed in parallel above and below the second storage capacitor electrode with the second storage capacitor electrode as the center. A three-dimensional storage capacitor can be constructed in such a limited area on the substrate.

In one aspect of the third electro-optical device of the present invention, the first dielectric film and the insulating thin film are made of the same film, and the scanning line and the second storage capacitor electrode are made of the same film. The second interlayer insulating film is formed on the scanning line and the conductive layer.

According to this structure, since the first dielectric film and the insulating thin film of the thin film transistor are formed of the same film, these insulating films can be formed in the same step, and the scanning line and the second storage capacitor electrode are formed of the same film. , These conductive films can be formed in the same step. The second interlayer insulating film is formed on the scanning lines and the conductive layers, and further has data lines formed thereon. Therefore, the storage capacitance can be increased by forming the first and second dielectric films thin, and the parasitic capacitance between the scanning lines and the data lines can be reduced by forming the second interlayer insulating film thick. As a result, a high-quality image can be displayed using a relatively simple configuration.

In another aspect of the third electro-optical device according to the present invention, the first interlayer insulating film and the second dielectric film are formed of the same film.

According to this structure, the first interlayer insulating film and the second dielectric film can be formed in the same step.
This is advantageous without increasing the number of steps.

In another aspect of the first, second, or third electro-optical device of the present invention, the conductive layer is made of a conductive light-shielding film.

According to this structure, each pixel opening region can be at least partially defined by the conductive layer made of a conductive light-shielding film. Thus, a part or all of the built-in light-shielding film (that is, the conductive layer formed of the light-shielding film) is formed on the substrate (usually a TFT array substrate) instead of the light-shielding film formed on the other substrate (usually, the opposite substrate). The configuration provided is extremely advantageous in that the pixel aperture ratio does not decrease due to the displacement between the substrate and the counter substrate in the manufacturing process.

In the aspect in which the conductive layer is formed of a light-shielding film, the conductive layer has a planar shape extending between the adjacent data lines along the scanning line on the substrate and is formed in an island shape for each pixel electrode. It may be.

When the conductive layer is formed in an island shape, not only the effect of the stress of the film constituting the conductive layer can be reduced, but also a part or all of the side of the pixel opening region along the scanning line can be reduced. Can be specified by In particular, when the parasitic capacitance between the scanning line and the conductive layer becomes a problem depending on the specific circuit design, the conductive layer is not provided on the scanning line,
It is preferable that the side along the scanning line of the pixel opening region on the side where the capacitor line and the pixel electrode are adjacent is defined by the conductive layer.

In the aspect in which the island-shaped light-shielding film is provided as a conductive layer, the adjacent data lines and the conductive layer may overlap at least partially in plan view.

With this configuration, there is no need to form a gap through which light is transmitted between the end of the island-shaped conductive layer and the edge of the data line when viewed in plan. That is, if the edge of the data line coincides with or slightly overlaps the end of the conductive layer, display defects such as light leakage at this portion can be prevented.

In the embodiment in which the conductive layer is formed of a light-shielding film,
The conductive layer may be formed so as to overlap with the scanning line when viewed in plan.

According to this structure, the side of the pixel opening region along the scanning line can be defined by the conductive layer formed of the light shielding film that at least partially covers both the scanning line and the capacitance line. .

In the embodiment in which the conductive layer is formed of a light-shielding film,
The conductive layer may include a high melting point metal.

According to this structure, the conductive layer can be prevented from being broken or melted by the high-temperature treatment performed after the step of forming the conductive layer formed of the light shielding film. For example, the light-shielding film is made of an opaque refractory metal such as Ti, Cr (chromium), W (tungsten), Ta (tantalum), and Mo.
(Molybdenum) and at least one of Pb (lead), a metal simple substance, an alloy, a metal silicide, or the like.

In another aspect of the first, second, or third electro-optical device according to the present invention, the conductive layer is formed of a conductive polysilicon film.

With this structure, the conductive layer made of a conductive polysilicon film does not function as a light-shielding film, but can sufficiently exhibit the function of increasing the storage capacity and the function of relaying. In this case, stress due to heat or the like is less likely to be generated between the conductive layer and the interlayer insulating film.

In another aspect of the first, second, or third electro-optical device of the present invention, the conductive layer is formed of a laminated film of two or more layers of a conductive polysilicon film and a high melting point metal. I have.

With this configuration, the conductive layer made of a conductive polysilicon film does not function as a light-shielding film, but can sufficiently exhibit the function of increasing the storage capacity and the function of relaying. Further, when the semiconductor layer and the conductive polysilicon film are electrically connected to each other, if the same polysilicon film is used, the contact resistance can be significantly reduced.
Further, if a high melting point metal is laminated on such a conductive polysilicon film, the function as a light shielding film can be exhibited and the resistance can be further reduced.

In another aspect of the first, second or third electro-optical device according to the present invention, the electro-optical device is provided on the substrate at a position covering at least a channel region of the semiconductor layer as viewed from the substrate side. It further includes a light shielding film.

According to this structure, the light-shielding film provided on the side closer to the substrate than the thin film transistor, that is, below the thin film transistor allows return light and the like from the substrate side to pass through the channel region of the thin film transistor and an LDD (Lightly Doped Drain).
It is possible to prevent the light from entering the region beforehand, and it is possible to prevent the characteristics of the thin film transistor from being changed or deteriorated due to the generation of a photocurrent caused by the incident. Further, it is possible to define a part or the whole of the pixel opening region by the light shielding film.

In the aspect having the light-shielding film, at least the light-shielding film may extend under the scanning line and be connected to a constant potential source.

According to this structure, it is possible to prevent the potential of the light-shielding film from fluctuating, thereby changing or deteriorating the characteristics of the thin-film transistor provided above the light-shielding film via the base insulating film.

Alternatively, in the aspect including the light-shielding film, the light-shielding film is provided with the second storage capacitor through a contact hole formed in a base insulating film interposed between the light-shielding film and the semiconductor layer. It may be electrically connected to the electrode.

With this configuration, the potentials of the second storage capacitor electrode and the light-shielding film can be made equal, and if one of the second storage capacitor electrode and the light-shielding film is set to a predetermined potential,
The other potential can also be a predetermined potential. At this time, if the light-shielding film is a capacitor line, the second storage capacitor electrode is connected to the capacitor line, and a constant potential can be given to the second storage capacitor electrode. As a result, it is possible to reduce adverse effects due to potential fluctuations in the second storage capacitor electrode and the light shielding film.

In another aspect of the third electro-optical device according to the present invention, the second storage capacitor electrode extends and is a capacitor line.

With this configuration, the potential of the capacitor line can be made constant, and the potential of the second storage capacitor electrode can be stabilized. In that case, the capacitor line and the scanning line can be formed of the same film.

In another aspect of the third electro-optical device according to the present invention, the capacitance line is electrically connected to the light-shielding film via the base insulating film.

With this configuration, the potentials of the capacitance line and the light-shielding film can be made equal, and if one of the capacitance line and the light-shielding film is set to the predetermined potential, the other potential can also be set to the predetermined potential. As a result, it is possible to reduce adverse effects due to potential fluctuations in the capacitance line and the light shielding film. Further, the wiring formed of the light-shielding film and the capacitance line can be made to function as a redundant wiring mutually.

In another aspect of the third electro-optical device of the present invention, the conductive layer and the light-shielding film may overlap at least partially in plan view.

According to this structure, since the conductive layer and the light-shielding film are formed so as to sandwich the channel region of the semiconductor layer, light intrusion from the substrate side into the channel region and light penetration from the other side can be prevented. Can be prevented. As a result, it is possible to prevent the characteristics of the thin film transistor from changing or deteriorating, and it is possible to prevent the occurrence of crosstalk, the reduction of the contrast ratio, and the deterioration of the flicker level.

In another aspect of the first, second, or third electro-optical device according to the present invention, a base insulating film is provided between the substrate and the thin film transistor, and the base insulating film is provided above the data line and below the pixel electrode. A third interlayer insulating film provided, wherein at least one of the substrate, the base insulating film, the second interlayer insulating film, and the third interlayer insulating film includes the thin film transistor, the scanning line, and the data line. , And at least a part of the region corresponding to the storage capacitor is formed so as to be concave, so that the underlying surface of the pixel electrode is substantially flattened.

According to this structure, at least one of the substrate and the plurality of interlayer insulating films includes a thin film transistor,
Since at least a part of the region corresponding to the scanning line, the data line, and the storage capacitor is formed to be concavely concave, the region where the thin film transistor, the scanning line, the storage capacitor, and the like are formed over the data line and the other region Steps are reduced. Since the lower surface of the pixel electrode is almost flattened in this way, the pixel electrode can be further flattened, and disclination and the like in an electro-optical material such as liquid crystal caused by depressions and irregularities on the surface of the pixel electrode. Defects are reduced, and finally high-quality image display becomes possible.

In another aspect of the third electro-optical device of the present invention, the first contact hole and the second contact hole are formed at different plane positions on the substrate.

Since the conductive layer at the plane position where the first contact hole is opened has some depressions and irregularities,
If the second contact hole is further opened just above this, the unevenness is amplified, and it becomes difficult to establish a good electrical connection. Therefore, if the plane positions of the two are slightly shifted from each other as in this embodiment, good electrical connection can be expected.

In another aspect of the first, second, or third electro-optical device of the present invention, the conductive layer has a thickness of 50 nm or more and 5 nm or more.
00 nm or less.

With this configuration, the thickness of the conductive layer is
Since the thickness is 50 nm or more and 500 nm or less, there is little or no adverse effect (for example, poor alignment of liquid crystal) due to a step on the pixel electrode surface due to the presence of the conductive layer, or an interlayer insulating film located above the conductive layer. It is possible to remove the influence of such a step by the flattening process in. In addition, various benefits can be obtained by the conductive layer as described above, while reducing the adverse effects of the conductive layer.

In another aspect of the second electro-optical device of the present invention, the thickness of the one interlayer insulating film is 10 nm or more and 200 n or more.
m or less.

According to this structure, the thickness of the first interlayer insulating film is 10 nm or more and 200 nm or less, and is a relatively thin insulating film. Therefore, using the first interlayer insulating film as a dielectric film, as described above, an additional storage capacitor formed by arranging the second storage capacitor electrode and the conductive layer to face each other with the first interlayer insulating film interposed therebetween. , A large storage capacity can be obtained according to the thickness.

In another aspect of the third electro-optical device of the present invention, the thickness of the second dielectric film is 10 nm or more and 200 n or more.
m or less.

With this configuration, the thickness of the second dielectric film is not less than 10 nm and not more than 200 nm, and is a relatively thin insulating film. For this reason, the storage capacitor in which the second storage capacitor electrode and the third storage capacitor electrode are arranged to face each other with the second dielectric film interposed therebetween has a large capacity according to the thinness.

In the embodiment of the present invention in which the conductive layer is formed of a light-shielding film, the conductive layer may be configured to define at least a part of the opening region of the pixel.

With this configuration, it is possible to define the opening area of the pixel with the conductive layer alone or together with the data line and the light-shielding film formed on the other substrate. In particular, if the opening region is defined without forming the light-shielding film on the other substrate, it is possible to reduce the number of steps in the manufacturing process and also to prevent a reduction or variation in the pixel aperture ratio due to misalignment between the pair of substrates. It is possible and advantageous.

In order to solve the above-described problems, a method of manufacturing an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, a thin film transistor connected to the scanning lines and the data lines, and a thin film transistor connected to the thin film transistors. In a method of manufacturing an electro-optical device having a pixel electrode and a storage capacitor, a source region, a channel region, and a drain region of the thin film transistor and a semiconductor layer serving as a first storage capacitor electrode of the storage capacitor are formed on a substrate. Forming an insulating thin film on the semiconductor layer, forming the scanning line and a second storage capacitor electrode of the storage capacitor on the insulating thin film, respectively, and forming a second storage capacitor electrode on the second storage capacitor electrode. Forming a first interlayer insulating film; opening the first contact hole in the gate insulating film and the first interlayer insulating film; Forming a conductive layer on the first interlayer insulating film so as to be electrically connected to the semiconductor layer through a via hole; forming a second interlayer insulating film on the conductive layer; Forming the data line on the second interlayer insulating film, forming the third interlayer insulating film on the data line, and opening the second contact hole in the second and third interlayer insulating films. And forming a pixel electrode so as to be electrically connected to the conductive layer via the second contact hole.

According to the method for manufacturing an electro-optical device of the present invention, the device can be manufactured using relatively simple steps.

In one embodiment of the method for manufacturing an electro-optical device according to the present invention, a step of forming a light-shielding film in a region of the substrate facing the channel region, and a step of forming a base insulating film on the light-shielding film In the step of forming the semiconductor layer, the semiconductor layer is formed on the base insulating film.

According to this structure, an electro-optical device in which a light-shielding film is provided below a thin film transistor can be manufactured with a relatively small number of steps and using relatively simple steps.

In one embodiment of the method of manufacturing an electro-optical device according to the present invention, at least one of the substrate, the base insulating film, the second interlayer insulating film, and the third interlayer insulating film is formed by using the thin film transistor and the scanning line. , At least a part of the region corresponding to the data line and the storage capacitor.

According to this embodiment, the lower surface of the pixel electrode can be flattened by forming a part of the region corresponding to the thin film transistor, the scanning line, the data line, and the storage capacitor in a concave shape. Defects such as ligation can be reduced. The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0073]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 2 shows an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. 2 shows a data line, a scanning line, a pixel electrode, a light-shielding film, and the like. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate, and FIG. 3 is a sectional view taken along line AA ′ of FIG. In FIG. 3, the scale of each layer and each member is different so that each layer and each member have a size that can be recognized in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix and constituting an image display area of the liquid crystal device according to the present embodiment have TFTs 3 for controlling a pixel electrode 9a.
A plurality of 0s are formed in a matrix, and the data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. The pixel electrode 9a and the TFT 30
It is arranged corresponding to the intersection of the scanning line 3a and the data line 6a. The image signals S1, S2,
, Sn may be supplied line-sequentially in this order.
A plurality of adjacent data lines 6a may be supplied for each group. The scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1 and G are pulsed to the scanning line 3a at a predetermined timing.
, Gm are applied line-sequentially in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30 and has a switching element TF
By closing the switch for a certain period of time T30, the image signals S1, S2,
..., Sn is written at a predetermined timing. Pixel electrode 9a
Image signal S of a predetermined level written on the liquid crystal through
1, S2,..., Sn are held for a certain period of time between a counter electrode (described later) formed on a counter substrate (described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. The liquid crystal device emits light having a contrast corresponding to the image signal as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is set to be three times longer than the time during which the source voltage is applied.
It is held by 0. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a made of a polysilicon film or the like via the contact hole 5, and the pixel electrode 9a is a region shown by oblique lines rising to the right in the figure. And a conductive layer 80 (hereinafter, referred to as a barrier layer) that functions as a buffer.
And is electrically connected to a drain region of the semiconductor layer 1a via a first contact hole 8a and a second contact hole 8b. In addition, the semiconductor layer 1
The scanning line 3a is disposed so as to face the channel region 1a '(a hatched region on the right in the figure) of the line a, and the scanning line 3a functions as a gate electrode. As described above, at the intersections of the scanning lines 3a and the data lines 6a, the TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the figure) along the data line 6a from a portion intersecting the data line 6a. And

Further, a first light-shielding film 11 a is provided in a region shown by a thick line in the drawing so as to pass below the scanning line 3 a, the capacitance line 3 b and the TFT 30, respectively. More specifically, in FIG. 2, the first light-shielding films 11a
Are formed in a striped shape along with the data line 6a, and a portion intersecting with the data line 6a is formed wide downward in the figure, and the channel portion 1a 'of each TFT is formed by the wide portion.
It is provided at a position to cover each as viewed from the T array substrate side.

Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device comprises a TFT array substrate 10 which constitutes an example of one transparent substrate, and an example of another transparent substrate which is arranged to face the TFT array substrate. And the opposing substrate 20. The TFT array substrate 10 is made of, for example, a quartz substrate, and has a counter substrate 20.
Is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is made of a transparent conductive thin film such as an ITO film. Also, alignment film 1
6 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 may be provided with a second light-shielding film 23 in a non-opening region of each pixel. Therefore, the incident light does not enter the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Further, the second light shielding film 23
It has a function of improving contrast and preventing color mixture of color materials when a color filter is formed.

The space between the TFT array substrate 10 and the opposing substrate 20, which is configured as described above and in which the pixel electrode 9a and the opposing electrode 21 face each other, is placed in a space surrounded by a sealing material described later. A liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around them,
A gap material, such as glass fiber or glass beads, for adjusting the distance between the two substrates to a predetermined value is mixed.

Further, as shown in FIG. 3, a first light-shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing the pixel switching TFT 30, respectively. First light shielding film 1
1a is Ti, C, preferably an opaque refractory metal
It is composed of a single metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo and Pb. With such a material, the first light-shielding film 11a is not broken or melted by high-temperature processing in the step of forming the pixel switching TFT 30 performed after the step of forming the first light-shielding film 11a on the TFT array substrate 10. I can do it. Since the first light shielding film 11a is formed, reflected light (return light) from the side of the TFT array substrate 10 is formed.
Pixel switching TFTs that are easily excited by light
30 can be prevented from entering the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c, and the characteristics of the pixel switching TFT 30 change due to the generation of a photocurrent resulting from this. It does not deteriorate.

Further, a base insulating film 12 is provided between the first light-shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 is formed by forming the semiconductor layer 1a constituting the pixel switching TFT 30 into a first light shielding film 11a.
It is provided to electrically insulate from the surface. Further, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the pixel switching TFT 30 is formed.
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the array substrate 10 during polishing, dirt remaining after cleaning, and the like. The base insulating film 12 is made of, for example, NSG (non-doped silicate glass), PSG
(Phosphorus silicate glass), high insulating glass such as BSG (boron silicate glass), BPSG (boron phosphor silicate glass), or a silicon oxide film, a silicon nitride film, or the like. The first light-shielding film 1 is formed by the base insulating film 12.
It is also possible to prevent a situation in which 1a contaminates the pixel switching TFT 30 and the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The first storage capacitor 70a is formed by extending the second dielectric film 2 from the position facing the scanning line 3a to form a first dielectric film sandwiched between these electrodes. Further, a part of the barrier layer 80 facing the second storage capacitor electrode is used as a third storage capacitor electrode, and a first interlayer insulating film 81 is provided between these electrodes. The first interlayer insulating film 81 also functions as a second dielectric film, and the second storage capacitor 70b is formed. The first storage capacitor 70a and the second storage capacitor 70b are connected in parallel via the first contact hole 8a to form the storage capacitor 70.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is extended below the data line 6a and the scanning line 3a to form a pixel switching TFT 30, and the high-concentration drain region 1e is connected to the data line 6a and the scanning line 3a. Capacitance line 3 extending along
b, the first dielectric film 2
This is the storage capacitor electrode 1f. In particular, the first dielectric film 2 is a TFT 3 formed on a polysilicon film by high-temperature oxidation or the like.
Since it is nothing but the insulating thin film 2 of 0, it can be a thin and high withstand voltage insulating film, and the first storage capacitor 70a can be configured as a large-capacity storage capacitor with a relatively small area. Also, the second
Since the dielectric film 81 can be formed as thin as the insulating thin film 2, the second storage capacitor 70b is relatively small by using the region between the adjacent data lines 6a as shown in FIG. The area can be configured as a large storage capacity. Therefore,
The three-dimensional storage capacitor 70 composed of the first storage capacitor 70a and the second storage capacitor 70b has an area under the data line 6a and an area where liquid crystal disclination occurs along the scanning line 3a (that is, the capacity). Region where line 3b is formed)
By effectively utilizing the space outside the pixel opening region, a large-capacity storage capacitor with a small area can be formed.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes a scanning line 3a, a channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, a scanning line 3a and the semiconductor layer 1.
a, the insulating thin film 2, the data line 6a, and the semiconductor layer 1
a low concentration source region 1b and low concentration drain region 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
To e, a corresponding one of the plurality of pixel electrodes 9a is connected via the barrier layer 80. The low-concentration source region 1b and the high-concentration source region 1d, and the low-concentration drain region 1c and the high-concentration drain region 1e are, as described later,
The semiconductor layer 1a is formed by doping an n-type or p-type impurity at a predetermined concentration depending on whether an n-type or p-type channel is formed. T for n-type channel
The FT has an advantage that the operation speed is fast, and is often used as the pixel switching TFT 30 which is a pixel switching element. In the present embodiment, in particular, the data line 6a is formed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. On the barrier layer 80 and the second dielectric film (first interlayer insulating film) 81, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8b leading to the barrier layer 80 are formed respectively. An interlayer insulating film 4 is formed. Via the contact hole 5 to the high-concentration source region 1d, the data line 6a is connected to the high-concentration source region 1d.
Is electrically connected to Further, a third interlayer insulating film 7 in which a contact hole 8b to the barrier layer 80 is formed is formed on the data line 6a and the second interlayer insulating film 4. The pixel electrode 9 is formed through the contact hole 8b.
a is electrically connected to the barrier layer 80, and is further connected to the high-concentration drain region 1e via the contact hole 8a via the barrier layer 80. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.

The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c.
A self-aligned TFT in which impurities are implanted at a high concentration by using a gate electrode which is a part of the TFT as a mask to form high-concentration source and drain regions in a self-aligned manner may be used.

In the present embodiment, a single gate structure in which only one gate electrode which is a part of the scanning line 3a of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e is used. Two or more gate electrodes may be arranged between them. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced, and a stable switching element can be obtained.

As shown in FIGS. 2 and 3, in the liquid crystal device of this embodiment, the data lines 6 a and the scanning lines 3 b are three-dimensionally arranged on the TFT array substrate 10 via the second interlayer insulating film 4. It is provided so as to intersect. The barrier layer 80 is interposed between the semiconductor layer 1a and the pixel electrode 9a, and connects the high-concentration drain region 1e and the pixel electrode 9a to each other.
Electrical connection is made via the contact hole 8a and the second contact hole 8b.

Therefore, the pixel electrode 9a is connected to the semiconductor layer 1a
The diameter of the first contact hole 8a and the diameter of the second contact hole 8b can be reduced as compared with the case where one contact hole is formed up to the drain region. That is, when one contact hole is opened, if the selectivity at the time of etching is low, the etching accuracy decreases as the contact hole is opened deeper, so that penetration through a very thin semiconductor layer 1a of, for example, about 50 nm is prevented. In order to do so, it is necessary to stop dry etching which can reduce the diameter of the contact hole halfway, and finally to form a step to open the semiconductor layer 1a by wet etching. Alternatively, it becomes necessary to separately provide a polysilicon film for preventing penetration through dry etching.

On the other hand, in the present embodiment, the pixel electrode 9
a and the high-concentration drain region 1e may be connected by two serial first contact holes 8a and second contact holes 8b.
And the second contact hole 8b can be opened by dry etching. Or,
This makes it possible to shorten at least the opening distance by wet etching. However, in order to slightly taper each of the first contact hole 8a and the second contact hole 8b, a relatively short wet etching may be performed after the dry etching.

As described above, according to the present embodiment, the diameters of the first contact hole 8a and the second contact hole 8b can be reduced, and the dents and irregularities formed on the surface of the barrier layer 80 in the first contact hole 8a can be reduced. Therefore, the flattening of the portion of the pixel electrode 9a located thereabove is promoted. Further, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the second contact hole 8b can be small, flattening of the pixel electrode 9a is promoted. As a result, disclination in the liquid crystal layer 50 due to depressions and irregularities on the surface of the pixel electrode 9a is reduced, and finally, a high-quality image can be displayed by the liquid crystal device. For example, the second interlayer insulating film 4 interposed between the barrier layer 80 and the pixel electrode 9a
If the total film thickness of the third interlayer insulating film 7 is suppressed to about several hundred nm, the second contact hole 8 that directly affects the above-described depressions and irregularities on the surface of the pixel electrode 9a.
The diameter of b can be made very small.

In this embodiment, since the barrier layer 80 is made of a high melting point metal film or an alloy film thereof, the selectivity in etching between the metal film and the interlayer insulating film is greatly different. There is almost no possibility of penetration of the barrier layer 80 by etching.

In the present embodiment, in particular, in the storage capacitor 70 three-dimensionally constructed with the barrier layer 80 at the center, the first
Each of the dielectric film 2 and the second dielectric film 81 is provided on a layer different from the second interlayer insulating film 4 interposed between the data line 6a and the scanning line 3b which are three-dimensionally intersecting with each other. It is a body membrane. Therefore, in order to suppress a parasitic capacitance between the data line 6a and the scanning line 3a which causes a voltage drop of an image signal causing flicker or the like, the barrier layer 80 is provided via a layer different from the second interlayer insulating film 4. In the case of the present embodiment, the first dielectric film 2 and the second dielectric film 81 can be thinned to a technical limit in order to add a storage capacitor. As a result, particularly in the second storage capacitor 70b, the capacitance value that is inversely proportional to the thickness of the second dielectric film 81 can be increased very efficiently. In particular, when the insulating film 2 is formed to be too thin such as the insulating thin film 2 in the pixel switching TFT 30, a specific phenomenon such as a tunnel effect does not occur. An extremely thin second layer having a thickness of 10 nm or more and 50 nm or less,
By forming the dielectric film 81, it is possible to form the second storage capacitor 70a having a very large capacity in a relatively small area. This not only suppresses the occurrence of flicker, but also increases the voltage holding capability,
A high-contrast electro-optical device can be provided.

According to experiments and studies conducted by the inventors of the present application, in the above-described prior art in which a barrier layer is formed from the same conductive layer as the data line 6a, this barrier layer is used as one electrode of a storage capacitor. Assuming that an interlayer insulating film between the data line 6a and the scanning line 3a is used as a dielectric film, in order to prevent the parasitic capacitance between the data line 6a and the scanning line 3a from becoming a problem, the dielectric film ( The film corresponding to the second interlayer insulating film of the present embodiment) needs a thickness of about 800 nm. Therefore, in the present embodiment, the second storage capacitor 70b having a capacitance value several times to tens of times or more in the same area can be realized, which is extremely advantageous.

Note that another one or a plurality of barrier layers are further laminated between the barrier layer 80 and the pixel electrode 9a with an interlayer insulating film interposed therebetween, so that the limited TFT array substrate 10 is formed.
It is also possible to further increase the storage capacity three-dimensionally using the upper region.

As described above, the second dielectric film 81 forming the second storage capacitor 70b may be a silicon oxide film, a silicon nitride film, or the like, or may be a multilayer film in which a plurality of these films are stacked. Various known techniques generally used for forming the insulating thin film 2 (low pressure CVD, normal pressure CVD, plasma CVD, thermal oxidation, sputtering, ECR
The second dielectric film 81 can be formed by a plasma method, a remote plasma method, or the like. However, instead of or in addition to the storage capacitance adding function of the barrier layer 80, emphasis is placed on the light shielding function of the barrier layer 80 made of a light shielding film, the layout of the first contact holes 8a and the second contact holes 8b, and the like. In the case where the barrier layer 80 and the second dielectric film 81 are formed up to the scanning line 3a, the second dielectric film 81 is so thick that the parasitic capacitance between the barrier layer 80 and the scanning line 3a does not matter. Preferably, it is formed.

On the other hand, the thickness of the barrier layer 80 is, for example, 50
It is preferable that the thickness be approximately from 500 nm to 500 nm. 50
If the thickness is about nm, the possibility of penetration when the second contact hole 8b is opened in the manufacturing process is low. If the thickness is about 500 nm, the unevenness on the surface of the pixel electrode 9a does not matter or is relatively easy. This is because flattening is possible.

Further, in this embodiment, by forming the first interlayer insulating film (second dielectric film) 81 thin in this way, the diameter of the first contact hole 8a can be further reduced. The depressions and irregularities of the barrier layer 80 in the holes 8a can be further reduced, and the planarization of the pixel electrodes 9a located above the barrier layers 80 is further promoted. Therefore, the discnation of the liquid crystal due to the depressions and irregularities in the pixel electrode 9a is reduced, and ultimately, a higher quality image display can be performed by the liquid crystal device.

In the structure of the liquid crystal device according to the present embodiment, the second interlayer insulating film 4 interposed between the scanning line 3b and the data line 6a also suffers from the problem of the parasitic capacitance between the two wirings. Thickness (for example, 800
(thickness of about nm).

In the present embodiment configured as described above, in particular, the first light-shielding film 11a formed in a stripe shape extends under the scanning line 3a and is electrically connected to a constant potential source or a large-capacity portion. May be connected. According to this structure, the pixel switching TFT is disposed opposite to the first light shielding film 11a.
30 does not adversely affect the potential change of the first light-shielding film 11a. In this case, as the constant potential source, a constant potential source such as a negative power supply or a positive power supply supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, or the like) for driving the liquid crystal device, a ground power supply And a constant potential source supplied to the counter electrode 21.

The capacitance line 3b and the scanning line 3a are made of the same polysilicon film, and the first storage capacitor 70a has the first storage capacitor 70a.
The dielectric film 2 and the insulating thin film 2 of the pixel switching TFT 30 are made of the same high-temperature oxide film or the like. The first storage capacitor electrode 1f and the channel region 1a 'of the pixel switching TFT 30, the low concentration source region 1b, the low concentration Drain region 1
c, the high-concentration source region 1d, the high-concentration drain region 1e, etc. are composed of the same semiconductor layer 1a. For this reason, TFT
The laminated structure formed on the array substrate 10 can be simplified,
Furthermore, in the method of manufacturing an electro-optical device described later, the capacitor line 3b and the scanning line 3a can be formed simultaneously in the same thin film forming step, and the first dielectric film and the insulating thin film 2 of the storage capacitor 70a can be formed simultaneously.

In this embodiment, in particular, the barrier layer 80 is made of a conductive light-shielding film. Therefore, the barrier layer 80
It is possible to at least partially define each pixel opening area. In addition, the TFT array substrate 10 having a light-shielding wiring such as the data line 6a by the barrier layer 80 or the like.
By defining the pixel opening in combination with the light-shielding film formed on the second substrate, the second light-shielding film on the counter substrate 20 side can be omitted. The second on the opposing substrate 20
The configuration in which the barrier layer 80 is provided as a built-in light-shielding film on the TFT array substrate 10 instead of the light-shielding film 23 is extremely low in that the pixel aperture ratio does not decrease due to the displacement between the TFT array substrate 10 and the counter substrate 20 in the manufacturing process. It is advantageous.

The second light-shielding film 23 on the counter substrate 20 is
Mainly to suppress the temperature rise of the liquid crystal device due to incident light,
It may be configured to be small (narrow) so that the pixel opening area is not defined. In this case, the second light shielding film 23 is made of Al
If it is formed of a material having high reflectivity such as a film, the temperature rise can be suppressed more efficiently. Thus, the second light shielding film 2
If 3 is formed smaller than the light-shielding region in the TFT array substrate, the pixel opening region does not need to be small due to a slight displacement between the two substrates in the manufacturing process.

The barrier layer 80 made of a light shielding film is, for example,
Opaque refractory metals Ti, Cr, W, Ta, Mo
And at least one of Pb and Pb. With such a configuration, the barrier layer 80 can be prevented from being broken or melted by the high-temperature treatment performed after the barrier layer 80 forming step.

Further, the refractory metal and the pixel electrode 9a
Since the refractory metal does not melt due to the difference in ionization rate even if the ITO film constituting the pixel electrode 9a contacts the barrier layer 80 and the pixel electrode 9a via the second contact hole 8b.
Good electrical connection can be established between them.

In this embodiment, in particular, as shown in FIG. 2, the barrier layer 80 made of a light-shielding film extends along the scanning line 3a between the data lines 6a whose plane shapes on the TFT array substrate 10 are adjacent to each other. , Are formed in an island shape for each pixel unit. As a result, the stress due to the light shielding film can be reduced. Further, part or all of the sides of the pixel opening region along the scanning line 3a can be defined by the barrier layer 80. Here, if the parasitic capacitance between the scanning line 3a and the barrier layer 80 poses a problem depending on the specific circuit design, the barrier layer 8 is provided on the scanning line 3a as in this embodiment.
It is preferable that the barrier layer 80 defines the side along the scanning line 3a of the pixel opening region on the side where the capacitor line 3b and the pixel electrode 9a are adjacent to each other without providing 0. Or,
According to the specific circuit design, the scanning line 3a and the barrier layer 80
If the parasitic capacitance between them does not matter, the barrier layer 8
0 may also be formed at a position facing the scanning line 3a via the second dielectric film 81. With this configuration, the light-shielding barrier layer 80 that at least partially covers both the scanning line 3a and the capacitor line 3b defines a larger portion of the side of the pixel opening region along the scanning line 3a. It becomes possible. In other words, in the case of such a configuration, it is preferable to configure the second dielectric film 81 to be thick enough that the parasitic capacitance of the scanning line 3a and the barrier layer 80 does not matter. Alternatively, to keep this parasitic capacitance small,
It is preferable that the barrier layer 80 covers the scanning line 3a only in an area necessary for defining the pixel opening area.

The scanning line 3a in the pixel opening region on the side (lower side in FIG. 2) where the scanning line 3a and the pixel electrode 9a are adjacent to each other.
May be defined by the first light-shielding film 11 a and the second light-shielding film 23. The side of the pixel opening region along the data line 6a may be defined by the data line 6a made of Al or the like or the first light shielding film 11a or the second light shielding film 23.

Further, as shown in FIG. 2, the island-shaped barrier layer 8 is formed.
It is preferable that each end of the 0 scanning line 3a in the direction and the edge of the data line 6a be slightly overlapped in a plan view. With this configuration, it is unnecessary to form a gap between the two so that the incident light can pass therethrough, and it is possible to prevent a display defect such as light leakage in this portion. Here, the data line 6a, the barrier layer 80 and the first light shielding film 11a or the data line 6a
The pixel opening can be defined by a light-shielding film such as the barrier layer 80 and the like. In such a case, it is not necessary to form the second light-shielding film 23 on the counter substrate 20, so that the step of forming the second light-shielding film 23 on the counter substrate 20 can be reduced. Further, it is possible to prevent the pixel aperture ratio from being lowered or varied due to misalignment between the counter substrate 20 and the TFT array substrate 10. In the case where the second light shielding film 23 is provided on the opposing substrate 20, the TFT array substrate 10
However, as described above, the pixel opening is defined by the light-shielding film formed on the TFT array substrate 10 such as the data line 6a and the barrier layer 80 as described above. The pixel aperture can be defined, and the aperture ratio can be improved as compared with the case where the pixel aperture is determined by the second light shielding film 23 provided on the counter substrate 20.

As described above, in this embodiment,
Although various advantages are obtained because the barrier layer 80 is made of a conductive light-shielding film, the barrier layer 80 may be made of, for example, a conductive polysilicon film doped with phosphorus or the like, instead of a high-melting-point metal film. Good. With this configuration, the barrier layer 80 does not function as a light-shielding film, but can sufficiently exhibit the function of increasing the storage capacitance 70 and the inherent relay function of the barrier layer. Further, stress due to heat or the like is less likely to be generated between the barrier layer 8 and the second interlayer insulating film 4.
It is useful for preventing cracks at and around zero. On the other hand,
Light shielding for defining the pixel opening region may be separately performed by the first light shielding film 11a and the second light shielding film 23.

In the present embodiment, a part or the whole of the pixel opening region may be defined by the first light-shielding film 11a formed below the TFT 30. For example, the first light shielding film 11
2 are arranged next to or slightly overlap with the barrier layer 80 in a plan view in FIG. 2, the first light-shielding film 11a and the barrier layer 80 allow the side of the pixel opening region along the scanning line 3a to be formed. Can be defined.

In the present embodiment, in particular, as shown in FIGS. 2 and 3, the first contact hole 8a and the second contact hole 8b are opened at different plane positions on the TFT array substrate 10. ing. Therefore, the first contact hole 8a and the second contact hole 8
It is possible to avoid the situation where the unevenness generated at the plane position where b is opened overlaps and the unevenness is amplified. Therefore, good electrical connection in these contact holes can be expected.

The plane shapes of the contact holes 8a, 8b and 5 may be circular, square or other polygonal shapes, but the circular shape is particularly useful for preventing cracks in the interlayer insulating film around the contact holes. Then, in order to obtain good electrical connection, wet etching is performed after dry etching to form these contact holes 8.
Preferably, a, 8b and 5 each have a slight taper.

(Manufacturing Process in First Embodiment of Electro-Optical Device) Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 4 to 7 show each layer on the TFT array substrate side in each step, as in FIG.
It is a process drawing shown corresponding to -A 'cross section.

First, as shown in step (1) of FIG. 4, a TFT array substrate 10 such as a quartz substrate, hard glass, or silicon substrate is prepared. Here, the heat treatment is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and the TFT is formed in a high-temperature process performed later.
The pre-processing is performed so that distortion generated in the array substrate 10 is reduced. That is, the TFT array substrate 10 is preliminarily adjusted to the highest temperature at the highest temperature in the manufacturing process.
Is heat-treated at the same temperature or higher. Then, a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal alloy film such as metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering or the like to a thickness of about 100 to 500 nm. Thick, preferably about 20
A light-shielding film 11 having a thickness of 0 nm is formed. The light shielding film 11
An anti-reflection film such as a polysilicon film may be formed thereon to reduce surface reflection.

Next, as shown in step (2), a resist mask corresponding to the pattern of the first light-shielding film 11a (see FIG. 2) is formed on the formed light-shielding film 11 by a photolithography step. Light shielding film 11 through a mask
The first light shielding film 11a is etched by etching
To form

Next, as shown in the step (3), a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl・ Boat rate) Gas, T
The underlying insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using MOP (tetramethyl oxyphosphate) gas or the like. The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm. In the case where the return light from the back surface of the TFT array substrate 10 does not matter, it is not necessary to form the first light shielding film 11a.

Next, as shown in step (4), a temperature of about 450 to 550 ° C., preferably about 500
Flow rate of about 400 to 600 cc /
An amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like for min. Thereafter, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, by performing a heat treatment for 4 to 6 hours, the polysilicon film 1 is solid-phase grown to a thickness of about 50 to 200 nm, preferably about 100 nm. As a method for solid phase growth, RTA (Rapid Thermal Anne) is used.
al) or a laser heat treatment using an excimer laser or the like.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG.
V such as b (antimony), As (arsenic), and P (phosphorus)
The impurity of the group element may be slightly doped by ion implantation or the like. When the pixel switching TFT 30 is of a p-channel type, impurities of a group III element such as B (boron), Ga (gallium), and In (indium) may be slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the film amorphous once, and then recrystallizing the film by a heat treatment or the like.

Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed by a photolithography step, an etching step, or the like.

Next, as shown in the step (6), the semiconductor layer 1a constituting the pixel switching TFT 30 is reduced to about 900
Thermal oxidation at a temperature of about 1300 ° C., preferably about 1000 ° C. to form a thermally thin silicon oxide film 2a having a relatively small thickness of about 30 nm, and further, as shown in step (7), low pressure CVD. An insulating film 2b made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a method or the like, and a pixel switching having a multilayer structure including the thermal silicon oxide film 2a and the insulating film 2b The first dielectric film 2 for forming a storage capacitor is formed simultaneously with the insulating thin film 2 of the TFT 30 for use. As a result, the thickness of the semiconductor layer 1a is about 30 to 150 nm, preferably about 35 to 50 nm, and the thickness of the insulating thin film (first dielectric film) 2 is about 20 to 150 nm. Thickness, preferably about 30-100 nm. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the insulating thin film 2 having a single-layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Next, as shown in a step (8), a resist layer 50 is formed by a photolithography step, an etching step and the like.
0 is the semiconductor layer 1 excluding the portion serving as the first storage capacitor electrode 1f
After forming on P.a, for example, P ions are dosed at about 3 × 1
The resistance of the first storage capacitor electrode 1f may be reduced by doping at 0 ¹² / cm ² .

Next, as shown in step (9), after the resist layer 500 is removed, a polysilicon film 3 is deposited by a low pressure CVD method or the like, and P is thermally diffused to form a polysilicon film 3.
Is made conductive. Alternatively, a doped polysilicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. The thickness of the polysilicon film 3 is about 100 to 500 n.
m, preferably about 300 nm.

Next, as shown in a step (10) of FIG. 5, by a photolithography step using a resist mask, an etching step and the like, a scanning line 3a and a capacitor line 3b having a predetermined pattern as shown in FIG. 2 are formed. . The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in the step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, the semiconductor layer 1a first has a low-concentration source region 1b and a low-concentration source region 1b. In order to form the concentration drain region 1c, an impurity of a group V element such as P is doped at a low concentration (for example, P ions are 1 to 3 × 10 ¹³ / cm 3) using a gate electrode which is a part of the scanning line 3a as a mask. Doping at a dose of ² ). Thereby, the semiconductor layer 1a below the scanning line 3a becomes the channel region 1a '.

Next, as shown in step (12), the high-concentration source region 1d constituting the pixel switching TFT 30
In order to form the high-concentration drain region 1e, a resist layer 600 is formed on the scanning line 3a with a mask wider than the scanning line 3a. , P ions from 1 to 3 × 10 ¹⁵ / cm
Doping at a dose of ² ). When the pixel switching TFT 30 is a p-channel type, the semiconductor layer 1
a, a lightly doped source region 1b and a lightly doped drain region 1
In order to form c and the high-concentration source region 1d and the high-concentration drain region 1e, doping is performed using an impurity of a group III element such as B. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping.
Using a as a mask, a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like. By doping this impurity, the capacitance line 3b and the scanning line 3
a is further reduced in resistance.

Incidentally, in parallel with the element forming process of these TFTs 30, an n-channel TFT and a p-channel TFT
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of the TFT array substrate may be formed in the peripheral portion on the TFT array substrate 10. As described above, if the semiconductor layer 1a constituting the pixel switching TFT 30 in this embodiment is formed of a polysilicon film, a peripheral circuit can be formed in substantially the same process when the pixel switching TFT 30 is formed. It is advantageous.

Next, as shown in a step (13), after the resist layer 600 is removed, a low pressure CVD method, a plasma CVD method, and the like are formed on the capacitance line 3b, the scanning line 3a, and the insulating thin film (first dielectric film) 2. High-temperature silicon oxide film (HTO)
Film) or a first interlayer insulating film 81 made of a silicon nitride film.
It is deposited to a relatively thin thickness of 0 nm or more and 200 nm or less. However, as described above, the first interlayer insulating film 81 may be formed of a multilayer film, or the first interlayer insulating film 81 may be formed by various known techniques generally used for forming an insulating thin film of a TFT. It can be formed. In the case of the first interlayer insulating film 81, if the thickness is too small as in the case of the second interlayer insulating film 4, the parasitic capacitance between the data line 6a and the scanning line 3a will not increase, and the insulating thin film in the TFT 30 will not increase. When it is configured to be too thin as in 2, no specific phenomenon such as a tunnel effect will occur. Also, the first interlayer insulating film 81
Is a second storage capacitor electrode and a barrier layer 8 which are part of a capacitor line.
Between 0, it functions as a second dielectric film. And the second
Since the second storage capacitor 70b becomes larger as the dielectric film 81 becomes thinner, an ultrathin insulating film having a thickness of 50 nm or less, which is thinner than the insulating thin film 2, on condition that no defects such as film breakage occur. When the second dielectric film 81 is formed so as to be as described above, the effect of the present embodiment can be increased.

Next, as shown in step (14), a contact hole 8a for electrically connecting the barrier layer 80 and the high-concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching. It is formed by etching. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be formed. Alternatively, wet etching which is advantageous for preventing the contact hole 8a from penetrating through the semiconductor layer 1a may be used together. This wet etching is also effective from the viewpoint of providing a taper for making better electrical connection to the contact hole 8a.

Next, as shown in step (15), Ti, Cr, W, Ta, and Ti are formed on the entire surface of the high-concentration drain region 1e viewed through the first interlayer insulating film 81 and the contact hole 8a.
A metal such as Mo and Pb or a metal alloy film such as metal silicide is deposited by sputtering or the like, and 50 to 500 nm
A conductive film 80 'having a film thickness of about the same is formed. If the thickness is about 50 nm, there is almost no possibility that the second contact hole 8b will be penetrated when the second contact hole 8b is later formed. The conductive film 8
An antireflection film such as a polysilicon film may be formed on 0 ′ to reduce surface reflection. Also, the conductive film 80 '
May use a doped polysilicon film or the like for stress relaxation. At this time, a doped polysilicon film (conductive polysilicon film) is used as a lower layer, and a metal film is used as an upper layer.
A stacked conductive film 80 'having a plurality of layers may be formed. Further, three layers may be formed by sandwiching a metal film between two layers of polysilicon films. As described above, when the conductive film 80 'and the high-concentration drain region 1e are electrically connected to each other, if they are formed of the same polysilicon film, the contact resistance can be significantly reduced.

Next, as shown in step (16) of FIG. 6, a resist mask corresponding to the pattern of the barrier layer 80 (see FIG. 2) is formed on the formed conductive film 80 ′ by photolithography. Conductive film 8 via resist mask
The barrier layer 80 including the third storage capacitor electrode is formed by performing etching on 0 ′.

Next, as shown in step (17), NS or NS gas is used to cover the first interlayer insulating film 81 and the barrier layer 80 using, for example, normal pressure or reduced pressure CVD, TEOS gas, or the like.
A second interlayer insulating film 4 made of a silicate glass film such as G, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the parasitic capacitance between the data line 6a and the scanning line 3a causes little or no problem.

Next, in the step (18), a heat treatment at about 1000 ° C. is performed for about 20 minutes in order to activate the high-concentration source region 1d and the high-concentration drain region 1e. The hole is opened. Also,
A contact hole for connecting the scanning line 3a and the capacitor line 3b to a wiring (not shown) in the peripheral region of the TFT array substrate 10 can be formed in the second interlayer insulating film 4 in the same process as the contact hole 5.

Next, as shown in a step (19), a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed on the second interlayer insulating ~ 500 nm thickness, preferably about 300
nm.

Next, as shown in a step (20), the data lines 6 are formed by a photolithography step, an etching step and the like.
a is formed.

Next, as shown in step (21) of FIG. 7, for example, normal pressure or reduced pressure CV is applied so as to cover the data line 6a.
NSG, PSG, BS using D method or TEOS gas
A third interlayer insulating film 7 made of a silicate glass film such as G or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 7 is about 500 to 1500
nm is preferred.

Next, as shown in step (22), a contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80 is formed by dry etching such as reactive ion etching or reactive ion beam etching. Form. Further, wet etching may be used to form a tapered shape.

Next, as shown in step (23), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Further, as shown in a step (24), the pixel electrode 9a is formed by a photolithography step, an etching step, or the like. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing treatment is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3) is formed.

On the other hand, as for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and the second light-shielding film 23 and a third light-shielding film as a frame described later are formed by sputtering metal chromium, for example. It is formed through a lithography process and an etching process. These second and third light-shielding films are made of metal materials such as Cr, Ni, and Al,
It may be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist. If the data line 6a, the barrier layer 80, the first light shielding film 11a and the like define a light shielding area on the TFT array substrate 10, the second light shielding film 23 and the third light shielding film on the counter substrate 20 can be omitted. it can.

Thereafter, a transparent conductive thin film of ITO or the like is deposited on the entire surface of
The counter electrode 21 is deposited to a thickness of 200 nm.
To form Furthermore, after applying a coating liquid for a polyimide-based alignment film to the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

Finally, the T on which each layer is formed as described above
The FT array substrate 10 and the counter substrate 20 are adhered to each other with a sealing material described later so that the alignment films 16 and 22 face each other. For example, a plurality of types of nematic liquid crystals are mixed in a space between the two substrates by vacuum suction or the like. The liquid crystal thus formed is sucked to form a liquid crystal layer 50 having a predetermined thickness.

(Second Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
T on which data lines, scanning lines, pixel electrodes, light shielding films, etc. are formed
FIG. 9 is a plan view of a plurality of pixel groups adjacent to each other on the FT array substrate, and FIG. 9 is a cross-sectional view taken along the line BB ′ of FIG. Note that in the second embodiment shown in FIGS. 8 and 9, the same components as those in the first embodiment shown in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 9, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawing.

8 and 9, in the second embodiment, unlike the first embodiment, the first light shielding film 11b covers the scanning lines 3a, the capacitance lines 3b, and the data lines 6a when viewed from the TFT array substrate 10 side. That is, it is provided in the entire area of the lattice-shaped non-opening area surrounding each pixel. Further, the base insulating film 1
2 is provided with a contact hole 15 for electrically connecting the capacitance line 3b and the first light shielding film 11b. The capacitance line 3b and the first light-shielding film 11b
Connected to constant potential wiring. Other configurations are the same as those in the first embodiment.

Therefore, according to the second embodiment, the first light-shielding film 11b not only has a function of defining the pixel opening area, but also has a function as a constant potential wiring or a redundant wiring of the capacitance line 3b, and also has a function of defining the capacitance line itself. Resistance can be reduced, and the image quality can be improved. With such a configuration, it is possible to define the pixel opening region by the first light shielding film 11b alone. Further, the potential of the capacitor line 3b and the first light-shielding film 11b can be set to the same constant potential, and the adverse effect on the image signal and the TFT 30 due to the potential fluctuation in the capacitor line 3b and the first light-shielding film 11b can be reduced. Further, the first light shielding film 11b and the semiconductor layer 1a
The underlying insulating film 12 interposed therebetween is used as a dielectric film, and a storage capacitor can be further added.

When the first light-shielding film 11b is used as a capacitor line, the capacitor line 3 formed in the same step as the scanning line 3a is formed.
b may be provided in the form of an island as a storage capacitor electrode for each pixel unit. With such a configuration, it is possible to improve the pixel aperture ratio.

Incidentally, such a first light-shielding film 11b serves as a first light-shielding film.
In the manufacturing process according to the embodiment, it can be formed by changing the pattern of the resist mask in the step (2). The contact hole 15 is formed by performing dry etching or wet etching such as reactive ion etching or reactive ion beam etching between the steps (8) and (9) during the manufacturing process in the first embodiment. A hole may be formed.

(Third Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG.
FIG. 9 is a cross-sectional view of the third embodiment corresponding to a cross section taken along line BB ′ of the plan view of FIG. 8 in the embodiment. In the third embodiment shown in FIG. 10, the same components as those in the second embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 10, the scale of each layer and each member is made different in order to make each layer and each member a recognizable size in the drawing.

In FIG. 10, the third embodiment is different from the second embodiment in that the upper surface of the third interlayer insulating film 7 ′ is formed flat. As a result, the third interlayer insulating film 7 '
The pixel electrode 9a and the alignment film 16 having the base film as the base film are also flattened. Other configurations are the same as those of the second embodiment.

Therefore, according to the third embodiment, a step with respect to another region where the scanning line 3a, the TFT 30, the capacitor line 3b, and the like are formed so as to overlap the data line 6a is reduced.
Since the pixel electrode 9a is thus flattened,
The occurrence of disclination of the liquid crystal layer 50 can be reduced according to the degree of the flattening. As a result, according to the third embodiment, it is possible to display a higher quality image, and it is possible to widen the pixel opening area.

The flattening of the third interlayer insulating film 7 'can be performed, for example, by performing a CMP (Chemical Mechanical Polish) process in the step (21) in the manufacturing process of the first embodiment.
ing) treatment, spin coating treatment, reflow method, or the like, or organic SOG (Spin On Glass), inorganic SOG, polyimide film, or the like. Even if the thickness of the third interlayer insulating film 7 ′ is increased for planarization as described above, the barrier layer 80 is formed of a film having a high selectivity, and therefore does not penetrate the film during etching.

(Fourth Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a fourth embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG.
FIG. 10 is a cross-sectional view of the fourth embodiment corresponding to a cross section taken along line BB ′ of the plan view of FIG. 8 in the embodiment. In the fourth embodiment shown in FIG. 10, the same components as those in the second embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted. Further, in FIG. 11, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawing.

In FIG. 11, the fourth embodiment differs from the second embodiment in that the upper surface of the TFT array substrate 10 'has a concave portion facing the data line 6a, the scanning line 3a and the capacitor line 3b. It is formed as a depression. As a result, the pixel electrode 9a and the alignment film 16 formed on the TFT array substrate 10 'via these wirings and the interlayer insulating film are also flattened. Other configurations are the same as those of the second embodiment.

Therefore, according to the fourth embodiment, the level difference between the region where the scanning line 3a, the TFT 30, the capacitor line 3b, and the like is formed and the region where the scanning line 3a and the capacitor line 3b are not formed is reduced. In this manner, the pixel electrode 9a is almost flattened only by burying at least a part of the non-opening region of the pixel, and the occurrence of disclination of the liquid crystal layer 50 can be reduced according to the degree of flattening. As a result, according to the fourth embodiment, it is possible to display a higher quality image, and it is also possible to widen the pixel opening area.

Incidentally, such a TFT array substrate 10 ′
For example, before the step (1) in the manufacturing process of the first embodiment, etching may be performed on a region where a concave depression is to be formed.

As described above, in the third embodiment, the upper surface of the third interlayer insulating film is flattened. In the fourth embodiment, wiring and element portions are formed by forming a concave groove on the substrate and finally forming Although the pixel electrode is flattened, the same flattening effect can be obtained even if the second interlayer insulating film 4 or the base insulating film 12 is formed to be concave. In this case, as a method of forming each interlayer insulating film in a concave shape, each interlayer insulating film has a two-layer structure, a thin portion composed of only one layer is a concave depression portion, and a two-layer thick portion is a concave bank portion. The thin film may be formed and etched as described above. Alternatively, each interlayer insulating film may have a single-layer structure, and a concave depression may be opened by etching. In these cases, when dry etching such as reactive ion etching or reactive ion beam etching is used, there is an advantage that a concave portion can be formed as designed. On the other hand, if at least wet etching is used alone or in combination with dry etching, the side wall surface of the concave depression can be formed in a tapered shape,
Since the remaining of the polysilicon film, the resist, and the like formed in the concave depression in the post-process in the periphery of the side wall can be reduced, there is obtained an advantage that the yield is not reduced.

(Fifth Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a fifth embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG. 12 is a fifth view corresponding to the AA ′ cross-sectional view of FIG. 2 in the first embodiment.
It is a sectional view of an embodiment. In the fifth embodiment shown in FIG. 12, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. Only different points from the first embodiment will be described.

In the fifth embodiment, a second contact hole 8b for electrically connecting the barrier layer 80 and the pixel electrode 9a is formed on the capacitance line 3b. By forming the second contact hole 8b on the capacitor line 3b as described above, the area under the region of the second contact hole 8b can also function as a capacitor, and the capacity can be increased accordingly.

(Overall Configuration of Electro-Optical Device) The overall configuration of a liquid crystal device, which is an example of the electro-optical device in each embodiment configured as described above, will be described with reference to FIGS. 13 is a plan view of the TFT array substrate 10 together with components formed thereon as viewed from the counter substrate 20, and FIG. 14 is a cross-sectional view taken along the line HH 'of FIG.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 1 are provided in a region outside the sealing material 52.
02 is provided along one side of the TFT array substrate 10, and supplies a scanning signal to the scanning line 3a at a predetermined timing to drive the scanning line 3a.
4 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area.
For example, the odd-numbered data lines 6a supply image signals from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG.
Counter substrate 2 having substantially the same contour as sealing material 52 shown in FIG.
0 is fixed to the TFT array substrate 10 by the sealing material 52. Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of data lines 6
a, a precharge circuit for supplying a precharge signal of a predetermined voltage level prior to an image signal, an inspection circuit for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or shipping may be formed. Good. According to the present embodiment,
The second light-shielding film 23 on the counter substrate 20 is the TFT array substrate 1
What is necessary is just to form it smaller than 0 light-shielding area. Further, the second light shielding film 23 can be easily removed depending on the use of the liquid crystal device.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, TN (Twisted) is provided on each of the side of the opposite substrate 20 where the projection light is incident and the side where the emission light of the TFT array substrate 10 is emitted.
Nematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

Since the electro-optical device in each of the embodiments described above is applied to a color display projector or the like, three electro-optical devices are used as light valves for R (red), G (green), and B (blue). Each of the light valves is used, and light of each color separated through a dichroic mirror for RGB color separation is incident on each light valve as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, the second
An RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the light-shielding film 23 is not formed, together with its protective film. Or TF
It is also possible to form a color filter layer with a color resist or the like below the pixel electrode 9a facing the RGB on the T array substrate 10. In this way, the electro-optical device according to each embodiment can be applied to a direct-view or reflection-type color liquid crystal television other than the projector. Further, the counter substrate 20
A microlens may be formed so as to correspond to one pixel above. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

In the electro-optical device according to each of the embodiments described above, incident light is incident from the side of the counter substrate 20 as in the related art. However, since the first light shielding film 11a is provided, the TFT array substrate 10 Incident light from the side of
The light may be emitted from the counter substrate 20 side. That is, even if the electro-optical device is attached to the liquid crystal projector, light can be prevented from being incident on the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a. Can be displayed. Here, conventionally, the TFT array substrate 1
0 to prevent reflection on the back side of
Although it was necessary to separately arrange a polarizing plate coated with R (Anti Reflection) or attach an AR film, in each embodiment, the surface of the TFT array substrate 10 and the semiconductor layer 1 a
Between the channel region 1a 'and the lightly doped source region 1b and the lightly doped drain region 1c.
a is formed, such an AR-coated polarizing plate or AR film may be used, or the TFT array substrate 10 may be used.
This eliminates the need to use a substrate that has been AR processed. Therefore, according to each of the embodiments, the material cost can be reduced, and the yield is not significantly reduced due to dust, scratches or the like when attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel is described as a normal stagger type or coplanar type polysilicon TFT.
The embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

(Electronic Apparatus) Next, an embodiment of an electronic apparatus including the above-described electro-optical device 100 will be described with reference to FIGS.

First, FIG. 15 shows the electro-optical device 1
1 shows a schematic configuration of an electronic device provided with an external device 00.

In FIG. 15, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a driving circuit 1.
004, electro-optical device 100, clock generation circuit 100
8 and a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Memory).
y), a memory such as a random access memory (RAM), an optical disk device, and the like, a tuning circuit that tunes and outputs an image signal, and the like, and displays an image signal in a predetermined format based on a clock signal from a clock generation circuit 1008. The information is output to the display information processing circuit 1002. The display information processing circuit 1002 includes an amplification / polarity inversion circuit, a serial-
It is configured to include a variety of well-known processing circuits such as a parallel conversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and sequentially generates digital signals from display information input based on a clock signal, and together with the clock signal CLK. Output to the driving circuit 1004. Drive circuit 1004
Drives the electro-optical device 100. Power supply circuit 1010
Supplies a predetermined power to each of the above-described circuits. The driving circuit 1004 may be mounted on the TFT array substrate constituting the electro-optical device 100. In addition, the display information processing circuit 1002 may be mounted.

Next, FIGS. 16 to 17 show specific examples of the electronic apparatus thus configured.

In FIG. 16, a projector 1100, which is an example of electronic equipment, has a drive circuit
Three light valves including the electro-optical device 100 mounted on a T-array substrate are prepared, and each is configured as a projector used as the light valves 100R, 100G, and 100B for RGB. In the projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1
106 and two dichroic mirrors 1108 separate the light components R, G, and B corresponding to the three primary colors of RGB, and the light valves 100R and 100G corresponding to the respective colors.
And 100B. In this case, in particular, the B light is incident on the incident lens 1122 to prevent light loss due to a long optical path.
The light is guided through a relay lens system 1121 including a relay lens 1123 and an emission lens 1124. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are combined again by the dichroic prism 1112, and then projected as a color image on the screen 1120 via the projection lens 1114.

In FIG. 17, a laptop personal computer (PC) 1200 compatible with multimedia, which is another example of electronic equipment, is the same as the electro-optical device 10 described above.
0 is provided in the top cover case.
U, memory, modem, etc.
02 is incorporated in the main body 1204.

In addition to the electronic devices described above with reference to FIGS. 16 to 17, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, an engineering machine, etc. A workstation (EWS), a mobile phone, a video phone, a POS terminal, a device having a touch panel, and the like are examples of the electronic apparatus shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices having an electro-optical device capable of displaying a high-quality image with high manufacturing efficiency.

[0175]

As described above, according to the first electro-optical device of the present invention, the display quality of the electro-optical device can be improved from various viewpoints by the conductive layer formed at a specific position in the laminated structure. In addition, it is possible to increase the degree of freedom in layout, improve the stability and reliability of the device, and simplify the manufacturing process.

According to the second electro-optical device of the present invention, a conductive film formed at a specific position in a laminated structure including a thin film transistor below a scanning line and a storage capacitor below a capacitor line at a position aligned with the thin film transistor. The layers improve the display quality of the electro-optical device and increase the degree of freedom in layout from various viewpoints,
It is possible to improve the stability and reliability of the device and to simplify the manufacturing process.

According to the third electro-optical device of the present invention, the second dielectric film, which can be made thin regardless of the parasitic capacitance between the data line and the scanning line, can be simply and efficiently stored. The capacity can be increased. For this reason, it is possible to reduce the flicker caused by the shortage of the storage capacity and to improve the contrast ratio, and it is possible to add a sufficient storage capacity even in high definition and ultra-miniaturization. In addition, the buffer function of the conductive layer facilitates electrical connection between the pixel electrode and the drain region, not only reduces the diameter of the contact hole, but also reduces the thickness of the first or second dielectric film. Since the hole diameter can be made even smaller,
It is possible to improve the pixel aperture ratio and prevent the occurrence of disclination of the electro-optical material due to the presence of the contact hole. Furthermore, the second contact hole is
In a region where the data line does not exist and the conductive layer exists in a plan view, the hole can be opened at an arbitrary plane position,
Since the degree of freedom in the position where the second contact hole is opened is significantly increased, the degree of freedom in designing a planar layout is greatly increased, which is very convenient in practice.

Further, according to the method of manufacturing an electro-optical device of the present invention, the electro-optical device of the present invention can be manufactured using a relatively small number of steps and using relatively simple steps.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area in a liquid crystal device according to a first embodiment of the electro-optical device.

FIG. 2 shows a data line in the liquid crystal device according to the first embodiment;
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a scanning line, a pixel electrode, a light shielding film, and the like are formed.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 5 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 6 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 7 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 8 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed in a liquid crystal device according to a second embodiment of the electro-optical device.

9 is a sectional view taken along the line B-B 'of FIG.

FIG. 10 is a sectional view of a liquid crystal device according to a third embodiment of the electro-optical device.

FIG. 11 is a sectional view of a liquid crystal device according to a fourth embodiment of the electro-optical device.

FIG. 12 is a sectional view of a liquid crystal device which is a fifth embodiment of the electro-optical device.

FIG. 13 is a plan view of the TFT array substrate in the liquid crystal device of each embodiment together with the components formed thereon as viewed from the counter substrate side.

FIG. 14 is a sectional view taken along line H-H ′ of FIG.

FIG. 15 is a block diagram illustrating a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 16 is a cross-sectional view illustrating a projector as an example of an electronic apparatus.

FIG. 17 is a front view illustrating a personal computer as another example of the electronic apparatus.

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First storage capacitor electrode 2 Insulating thin film (first dielectric film) 3a: scanning line 3b: capacitor line 4: second interlayer insulating film 5: contact hole 6a: data line 7: third interlayer insulating film 8a: first contact hole 8b: second contact hole 9a: pixel electrode 10: TFT Array substrate 11a, 11b First light-shielding film 12 Base insulating film 15 Contact hole 16 Alignment film 20 Counter-substrate 21 Counter electrode 22 Alignment film 23 Second light-shielding film 30 TFT 50 Liquid crystal layer 52 Sealing material 53 Third light-shielding film 70 Storage capacitance 70a First storage capacitance 70b Second storage capacitance 80 Barrier layer 81 First interlayer insulating film (second dielectric) Film: 101: data line driving circuit 104: scanning line driving circuit

Continued on front page F-term (reference) 2H091 FA02Y FA34Z FB08 FC02 FD04 GA07 GA13 HA07 JA02 LA03 MA07 2H092 GA48 GA51 GA59 HA25 HA28 JA25 JA46 JB24 JB53 JB54 JB56 JB58 JB64 JB69 KA04 KA05 KA10 KA22 MA25 MA05 MA41 NA07 NA22 PA08 PA09 QA07 QA15 RA05 5C094 AA05 AA43 AA45 BA03 BA43 CA19 DA15 DB04 EA03 EA04 EA07 EA10 ED15 FB02 FB12 FB16 FB19 GB01 5F110 AA16 BB01 BB02 CC02 DD02 DD03 DD05 DD12 EE03 FF03 DD05 DD12 DD13 FF02 GG13 GG25 GG32 GG47 GG52 HJ01 HJ04 HL02 HL03 HL04 HL05 HL08 HL11 HL12 HL23 HM14 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN27 NN35 NN36 NN44 NN46 NN47 NN72 PP02 PP03

Claims (32)

[Claims] 1. A plurality of scanning lines and a plurality of data lines on a substrate, a thin film transistor connected to the scanning line and the data line, a pixel electrode connected to the thin film transistor, and a storage capacitor connected to the pixel electrode. An electro-optical device comprising: a first interlayer insulating film formed above the scanning line and one electrode of the storage capacitor; a conductive layer formed above the first interlayer insulating film; An electro-optical device, comprising: a second interlayer insulating film formed above the conductive layer; wherein the data line is formed on the second interlayer insulating film. 2. The semiconductor device according to claim 1, further comprising a third interlayer insulating film formed above the data line on the substrate, wherein the pixel electrode is formed on the third interlayer insulating film and the second interlayer insulating film is formed on the second interlayer insulating film. And electrically connected to the conductive layer via a contact hole formed in a third interlayer insulating film, wherein the conductive layer is electrically connected to the semiconductor layer. 2. The electro-optical device according to 1. 3. A plurality of scan lines and a plurality of data lines on a substrate, a thin film transistor connected to each of the scan lines and each of the data lines, a pixel electrode connected to the thin film transistor, a source region of the thin film transistor, A semiconductor layer forming a drain region and a first storage capacitor electrode;
An insulating thin film formed on the semiconductor layer, a gate electrode of the thin film transistor formed on the insulating thin film and being part of the scanning line, and a second storage formed on the insulating thin film A capacitor electrode, a first interlayer insulating film formed above the scanning line and the second storage capacitor electrode, a conductive layer formed above the first interlayer insulating film, and formed above the conductive layer And a contact hole formed in the insulating thin film and the first and second interlayer insulating films while being formed on the second interlayer insulating film. An electro-optical device which is electrically connected to a source region of the semiconductor layer via a semiconductor layer. 4. The semiconductor device according to claim 1, wherein the conductive layer is electrically connected to a drain region of the semiconductor layer via a contact hole formed in the first interlayer insulating film and the insulating thin film. 4. The electro-optical device according to 3. 5. The semiconductor device further comprising a third interlayer insulating film formed above the data line on the substrate, wherein the pixel electrode is formed on the third interlayer insulating film and the second electrode is formed on the second interlayer insulating film. 5. The electro-optical device according to claim 3, wherein the electro-optical device is electrically connected to the conductive layer via a contact hole formed in the third interlayer insulating film. 6. A thin film transistor comprising: a plurality of pixel electrodes and thin film transistors arranged in a matrix on a substrate; scanning lines and data lines connected to the thin film transistors and intersecting three-dimensionally via an interlayer insulating film; Interposed between the semiconductor layer and the pixel electrode, electrically connected to the drain region of the semiconductor layer via a first contact hole, and electrically connected to the pixel electrode via a second contact hole. A first storage capacitor electrode formed of the same film as the semiconductor layer constituting the drain region, and a second storage capacitor electrode disposed on the first storage capacitor electrode. A dielectric film;
An electro-optical device comprising: a second dielectric film interposed between a storage capacitor electrode and a third storage capacitor electrode that is a part of the conductive layer. 7. The first storage capacitor electrode and the second storage capacitor electrode at least partially overlap with each other via the first dielectric film in plan view, and the second storage capacitor electrode and the third storage capacitor are overlapped. The electro-optical device according to claim 6, wherein at least a part of the electrode overlaps with the second dielectric film interposed therebetween. 8. The first dielectric film and the insulating thin film are formed of the same film, the scan line and the second storage capacitor electrode are formed of the same film, and the second interlayer insulating film is formed of the scan line. The electro-optical device according to claim 6, wherein the electro-optical device is formed on the conductive layer. 9. The electro-optical device according to claim 6, wherein the first interlayer insulating film and the second dielectric film are made of the same film. 10. The electro-optical device according to claim 1, wherein the conductive layer is made of a conductive light-shielding film. 11. The conductive layer, wherein a planar shape on the substrate extends between adjacent data lines along the scanning line, and is formed in an island shape for each pixel electrode. Item 11. The electro-optical device according to item 10. 12. The electro-optical device according to claim 11, wherein the adjacent data lines and the conductive layer overlap at least partially in plan view. 13. The semiconductor device according to claim 1, wherein the conductive layer overlaps the scanning line at least partially when viewed in plan.
The electro-optical device according to 0. 14. The electro-optical device according to claim 10, wherein the conductive layer contains a high melting point metal. 15. The semiconductor device according to claim 1, wherein the conductive layer is formed of a conductive polysilicon film.
The electro-optical device according to any one of the above. 16. The electro-optical device according to claim 1, wherein the conductive layer is formed of a laminated film of two or more layers of a conductive polysilicon film and a high melting point metal. apparatus. 17. The light-emitting device according to claim 1, further comprising a light-shielding film provided on the substrate so as to cover at least a channel region of the semiconductor layer in plan view.
The electro-optical device according to any one of claims 6 to 13. 18. The electro-optical device according to claim 17, wherein the light shielding film extends at least below the scanning line and is connected to a constant potential source. 19. The light-shielding film is electrically connected to the second storage capacitor electrode via a contact hole formed in a base insulating film interposed between the light-shielding film and the semiconductor layer. The electro-optical device according to claim 17, wherein: 20. The electro-optical device according to claim 19, wherein the second storage capacitor electrode extends and is a capacitor line. 21. The electro-optical device according to claim 20, wherein the capacitance line is electrically connected to the light shielding film via the base insulating film. 22. The light-shielding film according to claim 1, wherein the conductive layer and the light-shielding film overlap at least partially in plan view.
22. The electro-optical device according to any one of 7 to 21. 23. A semiconductor device comprising: a base insulating film between the substrate and the thin film transistor; and a third interlayer insulating film provided on the data line and below the pixel electrode. And at least one of the base insulating film, the second interlayer insulating film, and the third interlayer insulating film is formed so as to be concave in at least a part of a region corresponding to the thin film transistor, the scanning line, the data line, and the storage capacitor. 23. The electro-optical device according to claim 1, wherein the lower surface of the pixel electrode is substantially flattened. 24. The first contact hole and the second contact hole.
The electro-optical device according to any one of claims 6 to 9, wherein the contact holes are opened at different plane positions on the substrate. 25. The conductive layer has a thickness of 50 nm or more and 5 nm or more.
25. The structure according to claim 1, wherein the thickness is not more than 00 nm.
The electro-optical device according to any one of the above. 26. A film thickness of the first interlayer insulating film is 10 n
4. The structure according to claim 3, wherein the thickness is not less than m and not more than 200 nm.
The electro-optical device according to any one of claims 1 to 5, wherein 27. The film thickness of the second dielectric film is 10 nm.
The electro-optical device according to any one of claims 6 to 9, wherein the thickness is not less than 200 nm and not more than 200 nm. 28. The electro-optical device according to claim 10, wherein the conductive layer defines at least a part of an opening region of a pixel. 29. A plurality of scanning lines, a plurality of data lines,
In the method of manufacturing an electro-optical device having a thin film transistor disposed corresponding to the intersection of each of the scanning lines and the data lines, and a pixel electrode and a storage capacitor connected to the thin film transistor, a substrate includes a source region of the thin film transistor,
Forming a channel layer, the drain region, and a semiconductor layer serving as a first storage capacitor electrode of the storage capacitor; forming an insulating thin film on the semiconductor layer; and forming the scanning line and the storage on the insulating thin film. Forming a second storage capacitor electrode of a capacitor; forming a first interlayer insulating film on the second storage capacitor electrode; forming a first contact hole for the insulating thin film and the first interlayer insulating film; Forming a conductive layer on the first interlayer insulating film so as to be electrically connected to the semiconductor layer via the first contact hole; and forming a second conductive layer on the conductive layer. Forming an interlayer insulating film; forming the data line on the second interlayer insulating film; forming a third interlayer insulating film on the data line; and forming the second and third interlayer insulating films. Against 2. A method for manufacturing an electro-optical device, comprising: a step of forming two contact holes; and a step of forming a pixel electrode so as to be electrically connected to the conductive layer via the second contact hole. . 30. The method according to claim 30, further comprising: forming a light-shielding film in a region of the substrate facing the channel region; and forming a base insulating film on the light-shielding film. 30. The method according to claim 29, wherein the semiconductor layer is formed on the base insulating film. 31. A region corresponding to the thin film transistor, the scanning line, the data line, and the storage capacitor, wherein at least one of the substrate, the base insulating film, the second interlayer insulating film, and the third interlayer insulating film is formed. 31. The method of claim 30 further comprising the step of recessing at least a portion of
3. The method for manufacturing an electro-optical device according to claim 1. 32. An electronic apparatus comprising the electro-optical device according to claim 1. Description: