JP2000267596A - Electro-optical device and method of manufacturing the same - Google Patents

Abstract

(57) An electro-optical device which has a light-shielding layer having a sufficient light-shielding property, does not reduce the pixel aperture ratio even when the pixel pitch is reduced, and is capable of displaying high-quality images. The manufacturing method is provided. A liquid crystal device includes a TFT array substrate (10).
The TFT (30), the data line (6a), and the scanning line (3
a), a capacitor line (3b) and a pixel electrode (9a).
A light-shielding conductive layer made of a material different from the material forming the data lines is provided in the non-opening region of the pixel extending between the adjacent data lines on the first interlayer insulating film 4 and extending along the scanning lines and the capacitance lines. 80a are provided in an island shape. The pixel electrode and the TFT are electrically connected to a part of the semiconductor layer 1a through two conductive holes (8a, 8b) via the conductive layer 80a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device such as a liquid crystal device of a thin film transistor (hereinafter, referred to as TFT) active matrix driving method and a method of manufacturing the same, and in particular, a TFT substrate on which a TFT is formed. The present invention belongs to the technical field of an electro-optical device including a light-shielding film disposed thereon and a capacitance line for adding a storage capacitor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal panel of an active matrix driving system by TFT driving, a large number of scanning lines and data lines arranged vertically and horizontally and a large number of TFTs corresponding to their intersections are formed on a TFT array substrate. It is provided in. In each TFT, a gate electrode is connected to a scanning line, a source electrode is connected to a data line, and a drain electrode is connected to a pixel electrode. Here, in particular, the pixel electrode is T
Since it is provided on an interlayer insulating film layer for mutually insulating the various layers constituting the FT and the wiring and the pixel electrodes,
TF via a contact hole opened in the interlayer insulating film
It is connected to the drain electrode of T. When a scanning signal is supplied to the gate electrode of the TFT via the scanning line,
The TFT is turned on, and an image signal supplied to a source electrode (or a drain electrode) of the TFT via a data line is supplied to a pixel electrode via a source and a drain of the TFT. Supply of such an image signal is performed only for an extremely short time for each pixel electrode via each TFT. For this reason, in order to hold the voltage of the image signal supplied via the TFT which has been turned on for an extremely short time for a much longer time than the time which has been turned on, each pixel electrode is In general, a storage capacitor is formed in parallel with a liquid crystal capacitor. In general, a storage capacitor is formed by extending a semiconductor layer forming a drain electrode on a side connected to a pixel electrode in a TFT to serve as a first storage capacitor electrode, and using a part of a capacitor line formed along a scanning line as a second storage electrode. A storage capacitor electrode is formed for each pixel electrode by arranging these two storage capacitor electrodes facing each other via an insulating film (that is, a dielectric film). Alternatively, in this configuration, the scan line is added by using the preceding scanning line as the second storage capacitor electrode instead of the capacitor line.

With the storage capacitor having such a configuration, it is possible to maintain the voltage of the image signal at the pixel electrode for a time that is, for example, about three digits longer than the ON time of the pixel switching TFT, and the duty ratio is reduced. Even if it is small, a good image display with a high contrast ratio can be performed.

On the other hand, in this type of electro-optical device,
From the semiconductor layer formed on the TFT array substrate, a source electrode and a drain electrode of a TFT for pixel switching and a channel region therebetween are formed. The pixel electrode is connected to a drain electrode (or a source electrode) of a semiconductor layer through wirings such as a scanning line, a capacitor line, and a data line having a stacked structure and a plurality of interlayer insulating films for electrically insulating these from each other. Need to be connected. Here, particularly in the case of a positive stagger type or coplanar type polysilicon TFT having a top gate structure in which a gate electrode is provided on a semiconductor layer when viewed from the TFT array substrate side, the pixel electrode is shifted from the semiconductor layer in the multilayer structure. Since the interlayer distance up to about 1000 nm or more is long, it is difficult to form a contact hole for electrically connecting the two. More specifically, as the etching is performed deeper, the etching accuracy decreases, and there is a possibility that a hole may be formed through the target semiconductor layer. It is extremely difficult to open a hole. For this reason, dry etching and wet etching are combined, but this time, the diameter of the contact hole becomes large due to wet etching, and it is difficult to lay out wiring and electrodes as necessary in a limited area on the substrate. It becomes difficult.

Therefore, recently, when a contact hole reaching a source region is opened in an interlayer insulating film formed on a scanning line to make an electrical connection between a data line and a source region, the contact hole reaches a drain region. A contact hole is opened and a relay metal or barrier layer made of the same material and the same material (usually aluminum) as the data line and a relay conductive layer called a barrier layer are formed on the interlayer insulating film. A technique has been developed for forming a contact hole from a pixel electrode to the barrier metal in a line and an interlayer insulating film formed on the barrier metal. In this way, if a configuration is adopted in which the electrical connection from the pixel electrode to the drain region is made by relaying the barrier metal formed of the same layer as the data line, a contact hole from the pixel electrode to the semiconductor layer at once can be formed. In addition, the contact hole opening step and the like can be facilitated, and the diameter of each contact hole can be reduced. Therefore, recently, one or a plurality of relay conductive layers called barrier metals or barrier layers are interposed between a semiconductor layer forming a TFT in a laminated structure and an ITO film forming a pixel electrode, thereby forming two layers. Alternatively, a technique has been proposed in which contact holes having more than them are provided in series in the layer thickness direction.

Further, Al (aluminum), which is usually used as a material of a data line, and ITO (Indium Tin Oxide) film, which is usually used as a material of a pixel electrode, have poor compatibility with each other. Since electrolytic corrosion occurs, it is necessary to avoid contact between wirings and electrodes made of an Al film and wirings and electrodes made of an ITO film. Therefore, a technique of laminating a layer of titanium (Ti) or the like on the above-described relay conductive layer (Al) when connecting a wiring, an electrode, or the like composed of two incompatible films has been proposed. .

Recently, a conductive film of Al or the like forming a data line is used as a barrier layer between a semiconductor layer and a pixel electrode, and at the same time, a part of the barrier layer is connected to a scanning line via an interlayer insulating film. A technology has been proposed in which a storage line is additionally provided by disposing the storage line opposite to a capacitor line made of the same polysilicon or the like. According to this technique, since the same barrier layer is used for the relay wiring and used as the electrode for the storage capacitor, both the relay wiring and the electrode for the storage capacitor can be formed in the same process. Therefore, this technique is advantageous not only in the manufacturing process but also in effective use of the limited area on the substrate.

[0008]

In this type of electro-optical device, there is a strong demand for higher quality of a display image. For this purpose, a higher definition of an image display area or a pixel pitch (that is, a pixel pitch) is required. , Scanning line pitch and data line pitch)
Miniaturization and high pixel aperture ratio (ie, in each pixel,
It is extremely important to increase the ratio of the pixel opening area where the display light is transmitted to the non-pixel opening area where the display light is not transmitted.

However, as the pixel pitch becomes finer, a light-shielding film formed on the other substrate (usually a counter substrate) usually called a black matrix or a black mask and one substrate (usually a TFT array substrate) The margin of the alignment accuracy (margin) becomes smaller, the pixel aperture ratio decreases due to the misalignment with the black mask on the opposing substrate, and further, light is transmitted from the opposing substrate side to the TFT thin film transistor due to the misalignment. When this occurs, photocurrent leakage occurs, which causes flickering of the screen, disturbance of black and white contrast, crosstalk, and the like.

A data line usually formed of aluminum also functions as a light-shielding film on the TFT substrate side, but aluminum does not have sufficient light-shielding properties. Further, in some cases, a hillock, which is a phenomenon in which aluminum gathers when heat is applied to form a projection, breaks an insulating film and causes a short circuit. Further, since the etching solution for the data line made of aluminum and the pixel electrode made of ITO are the same, the data line may be etched when the pixel electrode is etched.

Although the above-described relay conductive layer can be used as a light-shielding film, Al which is a material of the relay conductive layer can be used.
And Ti and the like do not have sufficient light-shielding properties.

Further, by providing a light-shielding film such as tungsten silicide on the transparent substrate on which the thin film transistor is formed and below the thin film transistor, return light and the like from the TFT substrate side can be applied to the channel region of the thin film transistor or an LDD (Lightly Doped). Although there is a technique for preventing the incident state on the (Drain) region beforehand, the light-shielding property of this light-shielding film is not sufficient. Specifically, the light-shielding film made of tungsten silicide is usually formed by room-temperature sputtering, and is a film having a high light-shielding property in an amorphous state at the time of film formation.
Heat of about 000 ° C. is applied to form a crystallized film. On this occasion,
If Si / W = 2, there is no problem because WSi2 is light-shielding. However, Si / W = 2.7 to 2.8 because Si / W = 2 is likely to cause film peeling. ,
Light-shielding WSi2 and transmissive Si are generated, and light is slightly transmitted as a whole, so that the light-shielding property is not sufficient.

Further, as the pixel pitch becomes finer, the size of the electrode, the width of the wiring, and the diameter of the contact hole and the like are inherently limited due to the manufacturing technology. However, since the ratio of occupying the image display area increases, there is a problem that the pixel aperture ratio decreases.

Further, as the pixel pitch becomes finer as described above, it becomes difficult to make the above-mentioned storage capacitance, which must be formed in a limited area on the substrate, sufficiently large. For this reason, at the time of projection, flickering of the screen, disturbance of black and white contrast, crosstalk, and the like occur.

The present invention has been made in view of the above-mentioned problems, and has a light-shielding layer having a sufficient light-shielding property on a first interlayer insulating film so as to reduce a pixel aperture ratio even when a pixel pitch is reduced. Another object of the present invention is to provide an electro-optical device capable of displaying high-quality images and a method of manufacturing the same.

[0016]

In order to solve the above problems, an electro-optical device according to the present invention comprises a substrate having a plurality of scanning lines and a plurality of data lines, and a thin film transistor connected to the scanning lines and the data lines. An electro-optical device comprising: a pixel electrode connected to the thin film transistor; a semiconductor layer serving as a source region and a drain region of the thin film transistor; and a gate electrode disposed on the semiconductor layer via a gate insulating film. A first interlayer insulating film formed on the gate electrode, and a second interlayer insulating film disposed on the first interlayer insulating film, wherein the data line is formed on the first interlayer insulating film. And a second contact hole disposed on the data line so as to be connected to the data line through the first contact hole. Conductive layer is disposed, the first
A second conductive layer made of the same layer as the conductive layer is connected to a drain region of the semiconductor layer through a second contact hole disposed in the first interlayer insulating film;
It is arranged in an island shape so as to be connected to the pixel electrode via a third contact hole formed in the interlayer insulating film.

According to this aspect of the invention, the second conductive layer formed of the same layer as the first conductive layer is connected to the drain of the semiconductor layer via the second contact hole formed in the first interlayer insulating film. And is connected to the pixel electrode via a third contact hole formed in the second interlayer insulating film, and is arranged in an island shape. A configuration in which the semiconductor layer and the pixel electrode are electrically connected can be realized.

According to one aspect of the electro-optical device of the present invention, the first and second conductive layers have a light shielding property.

According to this aspect of the present invention, the conductive layer is provided in an island shape at a predetermined position on the first interlayer insulating film.
Since it has sufficient light-shielding properties on the interlayer insulating film, a light-shielding film such as a black matrix on the opposite substrate side can be omitted, or the black matrix on the opposite substrate side can be formed to have a smaller planar shape than the light-shielding layer. Can be avoided even if the pixel size is miniaturized. In particular, if the opening area is defined without forming a light-shielding film on the opposing substrate, it is possible to reduce the number of steps in the manufacturing process and to prevent a reduction or variation in the pixel aperture ratio due to misalignment between the pair of substrates. Is advantageous.

A light-shielding layer made of a material different from the material for forming the data lines may be provided on the first interlayer insulating film and in a frame region around the screen where the data lines are not formed.

According to another aspect of the electro-optical device of the present invention, the electro-optical device has a storage capacitor connected to the thin film transistor, and the storage capacitor extends from a semiconductor layer forming the drain region. A first storage device having an insulating thin film formed of the same layer as the gate insulating film between a storage capacitor electrode and a second storage capacitor electrode formed of a part of a capacitor line made of the same material as the gate electrode. And a second storage capacitor having the first interlayer insulating film between the second storage capacitor electrode and the second conductive layer.

According to this aspect, with respect to the pixel electrode,
Since the first and second storage capacitors can be added, the storage capacity can be increased.

The electro-optical device according to the present invention is characterized in that the first and second conductive layers are made of a different material from the data lines.

According to such a configuration, a light-shielding layer having a sufficient light-shielding property can be formed on the data line. For example, the light-shielding property becomes more complete by being formed over the Al data line. When a conductive light-shielding layer is formed on the data line, the reliability of the wiring is improved. Further, for example, by forming a hard light-shielding layer on the Al data line, a short circuit caused by hillocks of aluminum can be prevented, and since etching is not performed with an etching solution of ITO or SiO ₂ , these etching solutions are used. The Al data line can be protected during the used etching.

According to one aspect of the first and second electro-optical devices of the present invention, the light-shielding layer or the conductive light-shielding layer is mainly made of metal silicide.

According to this embodiment, for example, W (tungsten), Mo (molybdenum), Ta (tantalum), Cr
A metal silicide containing at least one of (chromium), Ti (titanium), and Pb (lead) has a sufficient light-shielding property, and has a sufficient conductivity as a relay conductive layer or a storage capacitor electrode. . These metal silicides are preferably in a non-single-crystal state (amorphous state) from the viewpoint of light-shielding properties. After forming these metal silicides, the upper limit temperature in the subsequent processes is about 400 ° C., so that the light-shielding property does not decrease due to crystallization.

In particular, WSi ₂ (tungsten silicide)
Is hard, so by forming it on the Al data line,
Shorts caused by aluminum hillocks can be prevented. Further, since tungsten silicide is not etched by the etching solution for the pixel electrode made of ITO, there is no possibility that the data line is etched when the pixel electrode is etched.

According to another aspect of the electro-optical device of the present invention, the first interlayer insulating film is made of an insulating high dielectric constant material.

According to this aspect, since the first interlayer insulating film is made of an insulating high dielectric constant material, the first interlayer insulating film is composed of the second storage capacitor electrode and the third storage capacitor electrode made of the third conductive layer. The storage capacity of the second storage capacity can be increased. Since the first interlayer insulating film needs a certain thickness, it is advantageous to use a high dielectric constant material having a large relative dielectric constant to increase the storage capacitance. Examples of the insulating high dielectric constant material include barium titanate, BST, RuO ₂ , silicon oxynitride, tantalum oxide, silicon nitride, silicon oxide, and the like. These may be used alone or in combination. You may use it. The insulating ferroelectric material layer can be formed by a chemical or physical thin film forming method such as CVD or PVD.

According to another aspect of the electro-optical device of the present invention, the second contact hole and the third contact hole are formed at different plane positions on the one substrate.

According to this aspect, the diameter of the contact hole can be reduced as compared with the case where one contact hole is formed at the same plane position from the pixel electrode to the drain region. In other words, the deeper the contact hole is, the lower the etching accuracy is. Therefore, in order to prevent punch-through in a thin semiconductor layer, dry etching that can reduce the diameter of the contact hole is stopped halfway, and finally the semiconductor is wet-etched. The process must be designed to open the layers. For this reason, the diameter of the contact hole must be increased by wet etching without directivity. On the other hand, in the present embodiment, since the pixel electrode and the drain electrode may be connected by two serial second and third contact holes, it is possible to open each contact hole by dry etching. Alternatively, it is possible to shorten at least the opening distance by wet etching. As a result, the second and third
Since the diameters of the contact holes can be made smaller, and the dents and irregularities formed on the surface of the conductive light-shielding layer in the second contact holes can be made smaller, flattening of the pixel electrode portion located above the second contact hole is promoted. Furthermore, since the depressions and irregularities formed on the surface of the pixel electrode in the third contact hole can be small, flattening of the pixel electrode portion is promoted. As a result, defects such as disclination in an electro-optical material such as a liquid crystal due to depressions and irregularities on the surface of the pixel electrode are reduced.

According to another aspect of the electro-optical device of the present invention, the second contact hole and the third contact hole may be formed at the same position on the one substrate.

According to this aspect, since the contact holes are opened at the same position, it is possible to prevent a reduction in the opening area due to the formation of the contact holes.

In the electro-optical device according to the present invention, as shown in FIG. 5, a conductive light-shielding layer 80a formed on the first interlayer insulating layer 4 and a pixel formed on the second interlayer insulating layer 7 are formed. The contact between the electrode 9a and the semiconductor layer 1a is made via the contact hole 8a and the contact hole 8b as shown in FIG.
They can be formed at the same plane position as shown in (1) and FIG. 5 (2), and can also be formed at different plane positions as shown in FIG. 5 (3). In the embodiment shown in FIG. 5B, the contact holes 8 are different from the embodiment shown in FIG.
The width of a and 8b can be reduced. In the embodiment shown in FIG. 5 (3), the diameters of the contact holes 8a and 8b can be reduced, and the responsiveness to miniaturization of the pixel pitch is excellent, and the manufacturing is easy.

According to another aspect of the electro-optical device of the present invention, a base light-shielding film is further provided between the substrate and the semiconductor layer so as to cover at least a channel region of the semiconductor layer. I do.

According to this aspect, the situation in which return light from one substrate side or the like is incident on the channel region or the LDD (Lightly Doped Drain) region of the thin film transistor can be prevented beforehand by the base light shielding film. It is possible to prevent deterioration of the characteristics of the thin film transistor due to the generation of the photocurrent. Then, it is also possible to define a part or the whole of the pixel opening region by the base light-shielding film. Note that although the underlying light-shielding film may have a reduced light-shielding property due to heating in a subsequent process, a more sufficient light-shielding layer of the present invention formed in an island shape on a data line, a scanning line, and a capacitor line is sufficient. Light shielding properties can be secured.

In a mode in which a base light-shielding film is provided below the thin film transistor, the base light-shielding film may extend below the scanning line and be connected to a constant potential source. With this configuration, it is possible to prevent a situation in which the characteristics of the thin film transistor provided above the base light-shielding film via the interlayer insulating film are degraded due to a change in the potential of the base light-shielding film. Alternatively, in the aspect including the base light-shielding film, the base light-shielding film may be connected to the capacitor line via a contact hole formed in another interlayer insulating film interposed between the base light-shielding film and the semiconductor film. May be electrically connected. With this configuration, the potential of the capacitor line and the underlying light-shielding film can be made equal, and if one of the capacitor line and the underlying light-shielding film is set to the predetermined potential, the other potential can be set to the predetermined potential. As a result,
It is possible to reduce adverse effects due to potential fluctuations in the capacitance line and the underlying light-shielding film. In addition, the wiring made of the underlying light-shielding film and the capacitance line can be made to function as a redundant wiring mutually.

According to another aspect of the present invention, there is provided a method of manufacturing an electro-optical device, the method comprising: a plurality of scanning lines and a plurality of data lines on a substrate; a thin film transistor connected to the scanning line and the data line; A method for manufacturing an electro-optical device having a pixel electrode connected to
Forming a source / drain region and a semiconductor layer serving as the first storage capacitor electrode on the substrate; and an insulating thin film forming a gate insulating film of the thin film transistor and a dielectric film of the storage capacitor on the semiconductor layer. Forming a first interlayer insulating film above the scanning line and the capacitor line; forming the first interlayer insulating film above the scanning line and the capacitor line; First and second first and second insulating films are formed on the first interlayer insulating film on the drain region.
Forming a contact hole; forming the data line so as to be connected to the source region via the first contact hole; and forming a first conductive layer on the data line so as to be connected to the data line. Forming a layer and forming an island-shaped second conductive layer so as to be connected to the drain region; forming a second interlayer insulating film on the first and second conductive layers; Forming a third contact hole in the second interlayer insulating film on the second conductive layer; and forming the pixel electrode so as to be connected to the second conductive layer via the third contact hole. It is characterized by having.

According to such a configuration, the above-described electro-optical device of the present invention can be manufactured with a relatively small number of steps and using relatively simple steps. In particular, the first and second contact holes for forming the second conductive layer and the data line can be formed at the same time, and the electro-optical device can be manufactured with a small number of steps.

According to one aspect of the method of manufacturing an electro-optical device of the present invention, the first and second conductive layers are made of a material different from a data line.

According to this aspect, the first conductive layer is formed on the data line simultaneously with the island-shaped second conductive layer formed in the predetermined region using a material different from the material for forming the data line. Yes, efficient. That is, first, after forming a film for forming a data line, the film is patterned to form a data line, and then, after forming a conductive layer, the film is patterned to form a first and second film. There is a method of forming a conductive layer.
In this case, in the data line forming step, a non-opening region (hereinafter, appropriately referred to as an island region) of a pixel extending between the adjacent data lines on the first interlayer insulating film and extending along the scanning line and the capacitance line. Thus, the island-shaped second conductive layer made of the same material as the data line forming material can be left.

In the first method, as for the data lines, for example, as shown in FIG.
(1)), the light shielding layer 80b covers the side surface of the data line 6a (FIG. 2B), and the light shielding layer 80b covers only the upper surface of the data line 6a (FIG. 3C). 6 (2) and (3) have the effects of preventing short circuit due to aluminum hillocks and protecting the Al data line from the etching solution of ITO or SiO _2. These effects are shown in FIG. Mode (3) is higher. On the other hand, as for the island region, as shown in FIG. 7, when only the light shielding layer 80a is used (FIG. 7A), the light shielding layer is formed up to the side surface of the island light shielding film 6c made of the same material as the data line forming material. There is a mode in which the light shielding layer 80a covers only the upper surface of the island-shaped light shielding film 6c made of the same material as the data line forming material (FIG. 3 (3)). FIG. 7 (2) and (3)
In the aspect described above, since the resistance of aluminum or the like is low, the contact resistance can be reduced.

Secondly, there is a method in which a film for forming a data line and a film for forming a light-shielding layer or a conductive light-shielding layer are laminated and then patterned.

In this case, regarding the data line, FIG.
7 (3) with respect to the island region.

Third, after forming a film for forming a data line, this film is patterned to form only a data line (not formed in an island region). Then, a conductive light shielding layer and a semiconductor layer are formed. Then, a film for forming a conductive light-shielding layer is formed, and then the film is patterned to form a conductive light-shielding layer. In this case, since the contact hole between the conductive light-shielding layer and the semiconductor layer is formed separately from the contact hole for the data line, it is possible to prevent AlSi from being generated from the semiconductor layer and the aluminum and adversely affecting the semiconductor layer.

In the first to third methods, a film for forming a light-shielding layer or a conductive light-shielding layer is formed first, and a film for forming a data line is formed later. You can also. That is, in the above-described first to third methods, if the "data line" and the "light-shielding layer or conductive light-shielding layer" are interchanged and read, a method in which the front-back or up-down relationship is reversed becomes possible.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0048]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 2 shows an equivalent circuit of various elements, wiring, and the like in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. 2 shows a data line, a scanning line, a pixel electrode, a light-shielding film, and the like. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate, FIG. 3 is a partial plan view of FIG. 2, and FIG. 4 is a cross-sectional view taken along line BB 'of FIG. In addition, FIG.
In FIG. 4, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the liquid crystal device according to the present embodiment are provided with TFTs 3 for controlling a pixel electrode 9a.
A plurality of 0s are formed in a matrix, and the data line 6a to which an image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Also, T
The scanning line 3a is electrically connected to the gate of the FT 30, and is configured to apply the scanning signals G1, G2,..., Gm in a pulsed manner to the scanning line 3a in this order at a predetermined timing. ing. The pixel electrode 9a is a TFT 30
Of the TFT 30 which is a switching element, which is electrically connected to the drain of the data line 6a.
1, S2,..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are supplied to a counter substrate (described later).
Is maintained for a certain period of time with a counter electrode (to be described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the case of the normally white mode, incident light is not allowed to pass through this liquid crystal portion according to the applied voltage, and in the case of the normally black mode,
In accordance with the applied voltage, incident light can pass through the liquid crystal portion, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by a dotted line portion 9a '), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected via a contact hole 5 to a source region described later in the semiconductor layer 1a made of a polysilicon film or the like.

In this embodiment, in particular, as shown in FIG. 3, a conductive light-shielding layer 80b (hereinafter, referred to as a conductive light-shielding layer) indicated by oblique lines on the lower right in FIG. Further, a conductive light-shielding layer 80a is formed in an island-like region indicated by oblique lines rising upward in the drawing.

In FIG. 2, a pixel electrode 9a is connected to a contact hole 8a and a contact hole 8a via a conductive light-shielding layer 80a formed in each of the island-shaped regions shown in FIG.
The semiconductor layer 1a is electrically connected to a drain region to be described later in the semiconductor layer 1a via the line b. In addition, the scanning line 3a is arranged so as to face the channel region 1a '(the hatched region on the right in the figure) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. As described above, at the intersections of the scanning lines 3a and the data lines 6a, the channel regions 1a 'are respectively provided.
The scanning line 3a of which is opposed to each other as a gate electrode
30 are provided.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the figure) along the data line 6a from a position intersecting the data line 6a. And

In particular, each of the rectangular conductive light-shielding layers 80a
It is electrically connected to the drain region of the semiconductor layer 1a by the contact hole 8a, and is electrically connected to the pixel electrode 9a by the contact hole 8b, and serves as a relay conductive layer or buffer between the drain region and the pixel electrode 9a. It is functioning. The conductive light-shielding layer 80a will be described later in detail.

A first light-shielding film 11a is provided in a region indicated by oblique lines rising to the right in the figure so as to pass under the scanning line 3a, the capacitance line 3b and the TFT 30, respectively. More specifically, in FIG. 2, the first light-shielding films 11a
Positions are formed in stripes along the scanning lines 3a and the capacitance lines 3b and along the data lines 6a, and cover the channel regions 1a 'of each TFT as viewed from the TFT array substrate side. It is provided in.

Next, as shown in the cross-sectional view of FIG. 4, the liquid crystal device comprises a TFT array substrate 10 which constitutes an example of one transparent substrate, and an example of another transparent substrate which is arranged to face the TFT array substrate. And the opposing substrate 20. The TFT array substrate 10 is made of, for example, a quartz substrate, and has a counter substrate 20.
Is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is composed of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode (common electrode). Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 22
Consists of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that performs switching control of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 4, the opposing substrate 20 is further provided with a second light-shielding film 23 called a black mask or a black matrix in a non-opening region of each pixel. Therefore, the incident light does not enter the channel region 1a 'or the LDD regions 1b and 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the side of the counter substrate 20. Further, the second light-shielding film (underlying light-shielding film) 23 has a function of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.

A sealing material to be described later (see FIGS. 13 and 14) is provided between the TFT array substrate 10 and the opposing substrate 20, which are configured as described above and in which the pixel electrode 9a and the opposing electrode 21 face each other. The liquid crystal which is an example of the electro-optical material is sealed in the space surrounded by the parentheses, and the liquid crystal layer 50 is formed. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 when no electric field is applied from the pixel electrode 9a. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the two substrates 10 and 20 around them, and a glass for setting a distance between the two substrates to a predetermined value. A gap material (spacer) such as fiber or glass beads is mixed.

Further, as shown in FIG. 4, a first light-shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each of the pixel switching TFTs 30. First light shielding film 1
1a is preferably an opaque refractory metal Ti, C
It is composed of a simple metal, an alloy, a metal silicide, or the like containing at least one of r, W, Ta, Mo, and Pb. With such a material, the first light-shielding film 11a is not broken or melted by the high-temperature treatment in the step of forming the pixel switching TFT 30 performed after the step of forming the first light-shielding film 11a on the TFT array substrate 10. Can be. Since the first light shielding film 11a is formed, reflected light (return light) from the side of the TFT array substrate 10 is formed.
Pixel switching TFTs that are easily excited by light
The incident on the channel region 1a 'and the LDD regions 1b and 1c of the TFT 30 can be prevented beforehand, and the characteristics of the pixel switching TFT 30 are not degraded due to the generation of a photocurrent due to this.

Further, an interlayer insulating film 12 is provided between the first light-shielding film 11a and the plurality of pixel switching TFTs 30. The interlayer insulating film 12 is formed by forming the semiconductor layer 1a constituting the pixel switching TFT 30 into a first light shielding film 11a.
It is provided for electrical insulation from Further, the interlayer insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the pixel switching TFT 30 is formed.
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the array substrate 10 during polishing, dirt remaining after cleaning, and the like. The interlayer insulating film 12 is made of, for example, a highly insulating glass such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), a silicon oxide film, or silicon nitride. It is composed of a film or the like. The first light-shielding film 11 a is formed by the interlayer insulating film 12.
Can prevent the pixel switching TFT 30 and the like from being contaminated.

In this embodiment, the semiconductor film 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The first storage capacitor 70a is formed by extending the film 2 from a position facing the scanning line 3a to form a first dielectric film sandwiched between these electrodes. Further, a part of the conductive light-shielding layer 80a facing the second storage capacitor electrode is used as a third storage capacitor electrode, and the first interlayer insulating film 4 is interposed between these electrodes, so that the second storage capacitor 70b is formed. Is formed. Then, the first and second storage capacitors 70a and 70b are
The storage capacitor 70 is connected in parallel through the line a. That is, the storage capacitance can be increased by the conductive light shielding layer 80a.

More specifically, the high-concentration drain region 1e of the semiconductor layer 1a is extended below the data line 6a and the scanning line 3a to form a pixel switching TFT 30. Similarly, the high-concentration drain region 1e is connected to the data line 6a and the scanning line 3a. Capacitance line 3 extending along
The first storage capacitor electrode 1f is disposed opposite to the portion b with the insulating film 2 interposed therebetween, and the insulating film 2 functions as a dielectric film. In particular, the insulating film 2 as the first dielectric film of the first storage capacitor 70a is a thin and high withstand voltage insulating film because it is nothing but the gate insulating film 2 of the TFT 30 formed on the polysilicon film by high-temperature oxidation. The first storage capacitor 70a can be configured as a large-capacity storage capacitor with a relatively small area. In addition, as shown in FIG. 3, the second storage capacitor 70b can be configured as a storage capacitor having a relatively small area by using a region between adjacent data lines. Therefore, the three-dimensional storage capacitor 70 composed of the first and second storage capacitors 70a and 70b has an area under the data line 6a and the scanning line 3a.
The area outside the pixel opening area, that is, the area where the liquid crystal disclination occurs (that is, the area where the capacitance line 3b is formed) is effectively used, and a large-capacity storage capacitor with a small area is formed. .

In FIG. 4, the pixel switching TFT
Reference numeral 30 denotes a scanning line 3a, a channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, a scanning line 3a and the semiconductor layer 1.
a, a low concentration source region (source-side LDD region) 1b of the semiconductor layer 1a.
And low concentration drain region (drain side LDD region) 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
To e, a corresponding one of the plurality of pixel electrodes 9a is connected via the conductive light shielding layer 80a. As described later, the source regions 1b and 1d and the drain regions 1c and 1e are provided with a predetermined concentration of n-type or p-type dopants for the semiconductor layer 1a depending on whether an n-type or p-type channel is formed. It is formed by doping. n
The TFT of the type channel has an advantage that the operation speed is high, and is often used as the pixel switching TFT 30 which is a pixel switching element. In this embodiment, in particular, the data line 6a is formed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. In the first interlayer insulating film 4, a contact hole 5 leading to the high concentration source region 1d and a contact hole 8a leading to the high concentration drain region 1e are formed. The data line 6a is electrically connected to the high-concentration source region 1d via the contact hole 5 to the high-concentration source region 1d. Further, a contact hole 8b leading to the conductive light-shielding layer 80a is formed in the second interlayer insulating film 7. The pixel electrode 9a is electrically connected to the conductive light-shielding layer 80a via the contact hole 8b, and further electrically connected to the high-concentration drain region 1e via the contact hole 8a via the conductive light-shielding layer 80a. Have been. The above-described pixel electrode 9a is provided on the upper surface of the second interlayer insulating film 7 configured as described above.

The pixel switching TFT 30 preferably has the LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT in which impurity ions are implanted at a high concentration using 3a as a mask to form high-concentration source and drain regions in a self-aligned manner may be used.

Further, in the present embodiment, a single gate structure in which only one gate electrode 3a of the pixel switching TFT 30 is arranged between the high-concentration source region 1d and the high-concentration drain region 1e is used. May be arranged. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced.
If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced,
A stable switching element can be obtained.

As shown in FIGS. 2 and 4, in the liquid crystal device of the present embodiment, the data lines 6 a and the scanning lines 3 b are three-dimensionally arranged on the TFT array substrate 10 via the first interlayer insulating film 4. It is provided so as to intersect. The conductive light-shielding layer 80a is interposed between the semiconductor layer 1a and the pixel electrode 9a, and electrically connects the high-concentration drain region 1e and the pixel electrode 9a via the contact holes 8a and 8b.

For this reason, the diameter of each of the contact holes 8a and 8b can be reduced as compared with the case where one contact hole is formed from the pixel electrode 9a to the drain region. That is, when one contact hole is opened, if the selectivity at the time of etching is low, the etching accuracy decreases as the contact hole is opened deeper.
In order to prevent punch-through in the very thin semiconductor layer 1a of about 0 nm, dry etching that can reduce the diameter of the contact hole is stopped halfway, and a process is finally performed so that the semiconductor layer is opened by wet etching. You have to cross. Alternatively, it becomes necessary to separately provide a polysilicon film for preventing penetration through dry etching.

On the other hand, in the present embodiment, the pixel electrode 9
a and the high-concentration drain region 1e may be connected by two serial contact holes 8a and 8b, so that these contact holes 8a and 8b can be opened by dry etching, respectively. Alternatively, it is possible to shorten at least the distance for opening by wet etching. However, when the contact hole 8a is completely opened by dry etching, electric charges due to plasma flow in the semiconductor layer and electrostatic breakdown of the TFT occurs. Therefore, it is preferable to stop dry etching before reaching the semiconductor layer and then perform wet etching. . In order to slightly taper each of the contact holes 8a and 8b, a relatively short wet etching may be performed after the dry etching. In the case of wet etching, the contact hole is slightly tapered due to infiltration of the etching solution into the interface with the resist and isotropic etching.

As described above, according to the present embodiment, the diameters of the contact holes 8a and 8b can be reduced, and the dents and irregularities formed above the contact holes 8a can be reduced. Flattening of the portion of the electrode 9a is promoted. Furthermore, contact hole 8
Since the depressions and irregularities formed on the surface of the pixel electrode 9a in b are small, flattening of the pixel electrode 9a is promoted. As a result, disclination (poor alignment) in the liquid crystal layer 50 due to depressions and irregularities on the surface of the pixel electrode 9a is reduced, and finally, a high-quality image can be displayed by the liquid crystal device. For example, if the layer thickness of the second interlayer insulating film 7 interposed between the conductive light-shielding layer 80a and the pixel electrode 9a is set to about several thousand angstroms, the above-described dents and irregularities on the surface of the pixel electrode 9a are more likely to occur. Contact hole 8 that directly affects
The diameter of b can be made very small. In addition, it is possible to avoid a situation in which the unevenness generated at the planar position where the contact holes 8a and 8b are opened overlaps and the unevenness is amplified. Therefore, good contact in these contact holes can be expected.

In this embodiment, the conductive light shielding layer 80a
Is mainly composed of refractory metals Ti, Cr, W, Ta,
It is made of metal silicide such as Mo and Pb.
For this reason, since the selectivity in the etching of the metal silicide film and the interlayer insulating film (that is, the glass film or the silicon film) is largely different, there is almost no possibility that the conductive light-shielding layer 80a penetrates by the dry etching as described above.

The layer thickness of the conductive light shielding layer 80a is, for example, 50
It is preferable that the thickness be approximately from 500 nm to 500 nm. 50
If the thickness is about nm, the possibility that the contact hole 8b will penetrate when the contact hole 8b is opened in the manufacturing process is low. If the thickness is about 500 nm, the unevenness of the surface of the pixel electrode 9a does not cause a problem or is relatively easily flattened. Because it is possible.

In this embodiment, the first light shielding film 11a is formed of TF
It is provided so as to cover the scanning lines 3a, the capacitance lines 3b, and the data lines 6a when viewed from the T array substrate 10 side, that is, over the entire area of the lattice-shaped non-opening region surrounding each pixel. Further, the interlayer insulating film 12 is provided with a contact hole 15 for electrically connecting the capacitance line 3b and the first light shielding film 11a. The capacitance line 3b and the first light-shielding film 11a are connected to a constant potential wiring in a peripheral region of the substrate. Therefore, the first light-shielding film 11a has the function of defining the pixel opening area and the capacity line 3 as well.
b serves as a constant potential wiring or a redundant wiring. With such a configuration, it is possible to define the pixel aperture region with the first light-shielding film 11a alone. Further, the potential of the capacitor line 3b and the first light-shielding film 11a can be set to the same constant potential, and the adverse effect on the image signal and the TFT 30 due to the potential fluctuation in the capacitor line 3b and the first light-shielding film 11a can be reduced.

The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, and the first dielectric film of the first storage capacitor 70a and the gate insulating film 2 of the pixel switching TFT 30 are the same. The first storage capacitor electrode 1f and the channel forming region 1a ', source region 1d, drain region 1e, etc. of the pixel switching TFT 30 are formed of the same semiconductor layer 1a. For this reason, TFT
The laminated structure formed on the array substrate 10 can be simplified,
Further, in a method of manufacturing an electro-optical device described later, the capacitor line 3b and the scanning line 3a can be formed simultaneously in the same thin film forming step, and the first dielectric film and the gate insulating film 2 of the storage capacitor 70a can be formed simultaneously.

In this embodiment, in particular, the conductive light-shielding layer 80a
Is made of a conductive light-shielding film. Therefore, the conductive light shielding layer 8
Oa makes it possible to at least partially define each pixel opening area. Further, the conductive light-shielding layer 80a or the T of a wiring having a light-shielding property such as the data line 6a may be used.
By defining the pixel openings in combination with the light-shielding film formed on the FT substrate 10, the opposing substrate 20 is defined.
It is also possible to omit the second light shielding film on the side. Instead of the second light shielding film 23 on the opposing substrate 20, the TFT array substrate 1
The configuration in which the conductive light-shielding layer 80a is provided as a light-shielding film on
This is extremely advantageous in that a positional shift between the TFT array substrate 10 and the counter substrate 20 in the manufacturing process does not cause a decrease in the pixel aperture ratio.

The second light shielding film 23 on the counter substrate 20 is
Mainly to suppress the temperature rise of the liquid crystal device due to incident light,
It may be configured to be small (narrow) so that the pixel opening area is not defined. Thus, the second light shielding film 23 is
If it is formed smaller than the light shielding area in the T array substrate, the pixel opening area does not need to be reduced due to a slight displacement between the two substrates in the manufacturing process.

The conductive light-shielding layers 80a and 80b are made of a metal silicide such as Ti, Cr, W, Ta, Mo and Pb which are high melting point metals. With this configuration, the conductive light-shielding layer 80a can be prevented from being broken or melted by the high-temperature treatment performed after the conductive light-shielding layer 80a forming step.

Further, since the refractory metal silicide and the ITO (Indium Tin Oxide) film forming the pixel electrode 9a have good compatibility, the conductive light-shielding layer 80a and the pixel electrode 9a are connected via the contact hole 8b. Good contact can be obtained.

In this embodiment, in particular, as shown in FIG. 3, the conductive light-shielding layer 80a made of a light-shielding film is provided on the TFT array substrate 10 with the data lines 6 adjacent to each other in a plane shape.
In the non-opening area of the pixel extending along the scanning line 3a and the capacitance line 3b between the areas a, the islands are formed. Therefore, it is possible to define more portions of the side along the scanning line 3a in the pixel opening region.

The scanning line 3a in the pixel opening region on the side (lower side in FIG. 2) where the scanning line 3a and the pixel electrode 9a are adjacent to each other.
May be defined by the first light-shielding film 11 a and the second light-shielding film 23. The side of the pixel opening region along the data line 6a may be defined by the data line 6a made of Al or the like or the first light shielding film 11a or the second light shielding film 23.

(Manufacturing Process in First Embodiment of Electro-Optical Device) Next, a manufacturing process of the liquid crystal device in the embodiment having the above-described configuration will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 8 to 11 show each layer on the TFT array substrate side in each step, as in FIG.
13 is a process diagram shown corresponding to the BB ′ cross section of FIG.

First, as shown in step (1) of FIG. 8, a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, annealing is preferably performed in an inert gas atmosphere such as N2 (nitrogen) and a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it. That is, the TFT array substrate 10 is previously heat-treated at the same temperature or a higher temperature in accordance with the highest temperature at the highest temperature in the manufacturing process. Then, the TFT array substrate 10 thus treated is
A metal such as i, Cr, W, Ta, Mo, and Pb or a metal alloy film such as a metal silicide is
The light-shielding film 11 having a layer thickness of about 0 to 500 nm, preferably about 200 nm is formed. In addition, on the light shielding film 11,
An antireflection film such as a polysilicon film may be formed to reduce surface reflection.

Next, as shown in step (2), a resist mask corresponding to the pattern of the first light-shielding film 11a (see FIG. 2) is formed on the formed light-shielding film 11 by photolithography. The first light-shielding film 11a is formed by etching the light-shielding film 11 through the step.

Next, as shown in step (3), a TEOS (tetra-ethyl-ortho-silicate) gas, a TEB (tetra-ethyl・ Boat rate) Gas, T
An interlayer insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed using MOP (tetramethyl oxyphosphate) gas or the like. The thickness of the interlayer insulating film 12 is, for example, about 500 to 2000 nm.

Next, as shown in the step (4), on the interlayer insulating film 12, about 450 to 550 ° C., preferably about 500 ° C.
Flow rate of about 400 to 600 cc /
An amorphous silicon film is formed by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like for min. Thereafter, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 1 is formed to a thickness of about 50 to 200 nm by performing an annealing process for 4 to 6 hours.
Preferably, the solid phase is grown to a thickness of about 100 nm. As a method for solid phase growth, RTA (Rapid Ther
(annealing using mal anneal) or laser annealing using an excimer laser or the like.

At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG.
V such as b (antimony), As (arsenic), and P (phosphorus)
A group element dopant may be slightly doped by ion implantation or the like. Also, the pixel switching TFT 30 is set to p
In the case of a channel type, a dopant of a group III element such as B (boron), Ga (gallium), or In (indium) may be slightly doped by ion implantation or the like.
The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low-pressure CVD method or the like to make the polysilicon film once amorphous (amorphized), and then recrystallize by annealing or the like.

Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by a photolithography step, an etching step and the like.

Next, as shown in the step (6), the first layer together with the semiconductor layer 1a constituting the pixel switching TFT 30 is formed.
By thermally oxidizing the storage capacitor electrode 1f at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C., a relatively thin thermally oxidized silicon film 2 of about 30 nm is formed.
a, and as shown in step (7), low pressure CVD
An insulating film 2b made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a method or the like, and a pixel switching having a multilayer structure including the thermal silicon oxide film 2a and the insulating film 2b A first dielectric film for forming a storage capacitor is formed together with the gate insulating film 2 of the TFT 30 for use. As a result, the thickness of the first storage capacitor electrode 1f is about 3
The thickness becomes 0 to 150 nm, preferably about 35 to 50 nm, and the thickness of the gate insulating film 2 and the first dielectric film is about 20 to 150 nm, preferably about 30 to 1 nm.
The thickness becomes 00 nm. By shortening the high-temperature thermal oxidation time in this way, warpage due to heat can be prevented particularly when a large substrate of about 8 inches is used. However, the gate insulating film 2 having a single-layer structure may be formed only by thermally oxidizing the polysilicon layer 1.

Next, as shown in a step (8), a resist layer 50 is formed by a photolithography step, an etching step and the like.
0 is the semiconductor layer 1 excluding the portion serving as the first storage capacitor electrode 1f
After forming on P.a, for example, P ions are dosed at about 3 × 1
Doping at 0 ¹² / cm ² lowers the resistance of the first storage capacitor electrode 1f.

Next, as shown in step (9), after the resist layer 500 is removed, a polysilicon layer 3 is deposited by a low pressure CVD method or the like, and phosphorus (P) is thermally diffused to form the polysilicon film 3. It becomes conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon layer film 3 may be used. The layer thickness of the polysilicon layer 3 is about 100 to 5
Volume to a thickness of 00 nm, preferably about 300 nm.

Next, as shown in a step (10) of FIG. 9, by a photolithography step using a resist mask, an etching step and the like, a capacitor line 3b is formed together with a scanning line 3a having a predetermined pattern as shown in FIG. . The layer thickness of these capacitance lines 3b (scanning lines 3a) is, for example, about 350 nm. The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel type TFT having an LDD structure, the semiconductor layer 1a first has a low concentration source region 1b and a low concentration source region 1b. In order to form the concentration drain region 1c, the scanning line 3a (gate electrode) is used as a diffusion mask, and a dopant of a V group element such as P is used at a low concentration (for example, P ions are used at a concentration of 1 to 3 × 10 ¹³ / cm ² ). (Dose amount). Thereby, the semiconductor layer 1a below the scanning line 3a becomes the channel region 1a '. The resistance of the capacitance line 3b and the scanning line 3a is also reduced by the doping of the impurity.

Next, as shown in step (12), the high-concentration source region 1d constituting the pixel switching TFT 30
After forming the resist layer 600 on the scanning line 3a with a mask wider than the scanning line 3a in order to form the high-concentration drain region 1e, a dopant of a group V element such as P is also added at a high concentration (for example, , P ions from 1 to 3 × 10 ¹⁵
/ Cm ² (dose amount). When the pixel switching TFT 30 is of a p-channel type, B or the like is used to form the low-concentration source region 1b and the low-concentration drain region 1c and the high-concentration source region 1d and the high-concentration drain region 1e in the semiconductor layer 1a. Using a Group III element dopant. Note that, for example, a TFT having an offset structure may be used without doping at a low concentration, and a self-aligned TF may be formed by an ion implantation technique using P ions, B ions, or the like using the scanning line 3a as a mask.
It may be T. The capacitance line 3b is formed by doping this impurity.
Further, the resistance of the scanning line 3a is further reduced.

Incidentally, in parallel with the element forming process of the TFT 30, an n-channel TFT and a p-channel TFT are formed.
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of As described above, in the present embodiment, since the semiconductor layer of the pixel switching TFT 30 is formed of polysilicon, the pixel switching TFT 30
A peripheral circuit can be formed in almost the same process when forming the semiconductor device, which is advantageous in manufacturing.

Next, as shown in step (13), after the resist layer 600 is removed, the capacitor line 3b, the scanning line 3a, and the gate insulating film 2 (first dielectric film) are, for example, at normal pressure or reduced pressure. NSG, using a CVD method or TEOS gas, etc.
Silicate glass films such as PSG, BSG, and BPSG;
A first interlayer insulating film 4 made of a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the first interlayer insulating film 4 is about 50
0-1500 nm is preferred. If the thickness of the first interlayer insulating film 4 is 500 nm or more, the data line 6a and the scanning line 3a
Parasitic capacitance coupling between them is of little or no problem.

Next, in the step (14), an annealing process at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 1d and the high-concentration drain region 1e.
A contact hole 5 for the data line 6a is opened.
Also, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings (not shown) in the peripheral region of the substrate are provided.
The first interlayer insulating film 4 is opened in the same process as the contact hole 5.

Next, as shown in step (15), a light-shielding layer A is formed on the first interlayer insulating film 4 by sputtering or the like.
1 as a metal film 6 having a thickness of about 100 to 500 nm, preferably about 300 to 500 nm.
nm.

Next, as shown in a step (16), the data lines 6 are formed by a photolithography step, an etching step and the like.
a is formed.

Next, as shown in step (17) of FIG.
A contact hole 8a for the pixel electrode is formed in the first interlayer insulating film 4.

Next, as shown in step (18), Ti, Cr, W are formed on the entire surface of the high-concentration drain region 1e, which is viewed through the first interlayer insulating film 4 and the contact hole 8a, like the first light-shielding film 11a. , Ta, Mo, Pb and other metal silicide films are deposited by sputtering, and
A conductive light shielding layer 80 having a thickness of about 00 nm is formed. 5
If the thickness is about 0 nm, the contact hole 8b will be formed later.
There is almost no possibility of piercing when opening the hole. Note that an anti-reflection film such as a polysilicon film may be formed on the conductive light-shielding layer 80 to reduce surface reflection.

Next, as shown in step (19), a resist corresponding to the pattern (see FIG. 3) of the conductive light-shielding layers 80a and 80b is formed on the formed conductive light-shielding layer 80 by photolithography. A mask is formed, and the conductive light-shielding layer 80 is etched through the resist mask to form a conductive light-shielding layer 80a including a third storage capacitor electrode and a conductive light-shielding layer 80b.

Next, as shown in the step (20), the NSG, PSG, and the like are applied so as to cover the conductive light-shielding layers 80a and 80b using, for example, normal pressure or reduced pressure CVD, TEOS gas, or the like.
A second interlayer insulating film 7 made of a silicate glass film such as SG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the second interlayer insulating film 7 is about 500
~ 1500 nm is preferred.

Next, as shown in step (21) of FIG.
A contact hole 8b for electrically connecting the pixel electrode 9a and the conductive light-shielding layer 80a is formed by dry etching such as reactive ion etching or reactive ion beam etching. Further, wet etching may be used to form a tapered shape.

Next, as shown in step (22), a transparent conductive thin film 9 such as an ITO film is deposited on the second interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in the step (23), the pixel electrode 9a is formed by a photolithography step, an etching step and the like. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing treatment is performed so as to have a predetermined pretilt angle and in a predetermined direction. 4) is formed.

On the other hand, as for the counter substrate 20 shown in FIG. 4, a glass substrate or the like is first prepared, and the second light shielding film 23 and the third light shielding film 53 as a frame (see FIGS. 13 and 14).
Are formed through, for example, a photolithography step and an etching step after sputtering metal chromium. The second and third light-shielding films may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or Al. still,
If the light shielding area is defined by the data lines 6a, the conductive light shielding layers 80a and 80b, the first light shielding film 11a, and the like on the TFT array substrate 10, the second light shielding film 23 and the third light shielding film on the counter substrate 20 are omitted. be able to.

Thereafter, a transparent conductive thin film such as ITO is applied to the entire surface of the counter substrate 20 by sputtering or the like for about 50 to 2 minutes.
The counter electrode 21 is formed by depositing to a thickness of 00 nm. Further, after applying a coating liquid for a polyimide-based alignment film on the entire surface of the counter electrode 21, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the like, so that the alignment film 22 (see FIG. 4) is formed. It is formed.

Finally, the T on which each layer is formed as described above
The FT array substrate 10 and the counter substrate 20 are bonded together with a sealing material (see FIGS. 13 and 14) so that the alignment films 16 and 22 face each other. The liquid crystal formed by mixing the above nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness.

(Second Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIG. FIG.
It is sectional drawing of 2nd Embodiment corresponding to BB 'cross section of the top view of FIG. 2 in embodiment. In the second embodiment shown in FIG. 12, the same components as those in the first embodiment shown in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted. Also, in FIG. 12, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawing.

In FIG. 12, unlike the first embodiment, a layer made of the same material as the data lines and formed simultaneously with the formation of the data lines is formed under the conductive light shielding layer 80a in the second embodiment. I have. The planar shape of this layer is the same as the shape of the island-shaped conductive light-shielding layer 80a. Other configurations are the same as those in the first embodiment.

According to the second embodiment, since the material of the data line, such as aluminum, has a low resistance, the contact resistance can be reduced.

In the first and second embodiments, the pixel electrode 9a is flattened by flattening the second interlayer insulating film 7. The planarization of the second interlayer insulating film 7 is performed, for example, by CMP (Ch
emical mechanical polishing), spin coating, reflow method, etc., and organic SOG (Spin O
n Glass) film, inorganic SOG film, polyimide film or the like.

(Overall Configuration of Electro-Optical Device) The overall configuration of the liquid crystal device in each embodiment configured as described above will be described with reference to FIGS. Note that FIG.
FIG. 14 is a plan view of the FT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side.
FIG. 13 is a sectional view taken along line HH ′ of FIG. 12.

In FIG. 13, a sealing material 52 is provided along the edge of the TFT array substrate 10 and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. In a region outside the sealing material 52, a data line driving circuit 101 that drives the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and a mounting terminal 102 are provided.
A scanning line driving circuit 104, which is provided along one side of the FT array substrate 10 and drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing, operates along two sides adjacent to this one side. It is provided. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines are arranged along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining side of the TFT array substrate 10,
Scanning line drive circuits 104 provided on both sides of the image display area
A plurality of wirings 105 for connecting between them are provided.
In at least one of the corners of the opposing substrate 20, a conductive material 106 for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 is provided. Then, as shown in FIG. 14, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 13 is fixed to the TFT array substrate 10 by the sealing material 52. Incidentally, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., on the TFT array substrate 10,
A sampling circuit 103 for applying an image signal to the plurality of data lines 6a at a predetermined timing; a precharge circuit for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 6a in advance of the image signal; An inspection circuit or the like for inspecting the quality, defects, and the like of the liquid crystal device at the time may be formed. According to the present embodiment, the second light shielding film 23 on the counter substrate 20 may be formed smaller than the light shielding area of the TFT array substrate 10. Further, the second light shielding film 23 can be easily removed depending on the use of the liquid crystal device.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a TAB (Tape Automated Bonding Tape) is used. It may be electrically and mechanically connected to a driving LSI mounted on an automated bonding (substrate) via an anisotropic conductive film provided on a peripheral portion of the TFT array substrate 10. For example, the TN (Twisted Nematic Twisted Nematic) mode and the VA (Vertically Aligne) mode are provided on the side of the opposite substrate 20 where the projected light is incident and on the side where the emitted light of the TFT array substrate 10 is emitted, respectively.
d) STN (Super TN) mode, PBLC (Polymer D
ispersed Liquid Crystal) Mode D-STN (Double-
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as an STN) mode or a normally white mode / normally black mode.

Since the liquid crystal device in each of the embodiments described above is applied to a color liquid crystal projector, three liquid crystal devices are used as light valves for R (red), G (green), and B (blue), respectively. The light of each color separated through the dichroic mirror for RGB color separation is incident on each panel as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film. Alternatively, R on the TFT array substrate 10
It is also possible to form a color filter layer with a color resist or the like below the pixel electrode 9a facing the GB. In this way, the liquid crystal device in each embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector. In addition, 1
A micro lens may be formed so as to correspond to one pixel. In this case, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color liquid crystal device can be realized.

In the liquid crystal device according to each of the embodiments described above, incident light is made to enter from the side of the counter substrate 20 as in the prior art. However, since the first light shielding film 11a is provided, the TFT array substrate 10 The incident light may be incident from the side and emitted from the counter substrate 20 side. That is,
Thus, even if the liquid crystal device is attached to the liquid crystal projector, it is possible to prevent light from being incident on the channel region 1a 'and the LDD regions 1b, 1c of the semiconductor layer 1a, and it is possible to display a high quality image. is there. Here, conventionally, in order to prevent reflection on the back side of the TFT array substrate 10, it is necessary to separately arrange a polarizing plate coated with an anti-reflection (AR) coating for anti-reflection, or to attach an AR film. However, in each embodiment, the TFT array substrate 1
0 and at least the channel region 1 of the semiconductor layer 1a.
a ′ and the first light shielding film 11 between the LDD regions 1b and 1c.
a is formed, such an AR-coated polarizing plate or AR film may be used, or the TFT array substrate 10 may be used.
This eliminates the need to use a substrate that has been AR processed. Therefore, according to each of the embodiments, the material cost can be reduced, and the yield is not significantly reduced due to dust, scratches or the like when attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
Embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area in a liquid crystal device according to a first embodiment of the electro-optical device.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding film, and the like are formed in the liquid crystal device according to the first embodiment.

FIG. 3 is a partial plan view of FIG. 2;

FIG. 4 is a sectional view taken along line B-B 'of FIG.

FIG. 5 is a partial cross-sectional view for explaining a mode of contact between a conductive light-shielding layer, a pixel electrode, and a semiconductor layer.

FIG. 6 is a partial cross-sectional view for explaining an aspect of a light shielding layer formed on a data line.

FIG. 7 is a partial cross-sectional view for explaining an aspect of a light shielding layer formed in a predetermined island region.

FIG. 8 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 9 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 10 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 11 is a process view (part 4) for sequentially illustrating the manufacturing process of the liquid crystal device of the first embodiment.

FIG. 12 is a sectional view of a liquid crystal device according to a second embodiment of the electro-optical device.

FIG. 13 is a plan view of a TFT array substrate in the liquid crystal device according to each embodiment together with components formed thereon as viewed from a counter substrate side.

FIG. 14 is a sectional view taken along line H-H ′ of FIG.

[Explanation of symbols]

 1a semiconductor layer 1a 'channel region 1b low concentration source region (source side LDD region) 1c low concentration drain region (drain side LDD region) 1d high concentration source region 1e high concentration drain region 1f first accumulation Capacitance electrode 2 gate insulating film 3a scanning line 3b capacitance line (second storage capacitor electrode) 4 first interlayer insulating film 5 contact hole 6a data line 7 second interlayer insulating film 8a contact hole 8b Contact hole 9a: Pixel electrode 10: TFT array substrate 11a, 11b: First light-shielding film 12: Interlayer insulating film 15: Contact hole 16: Alignment film 20: Counter substrate 21: Counter electrode 22: Alignment film 23: Second light-shielding film Reference Signs List 30: TFT for pixel switching 50: Liquid crystal layer 52: Seal material 53: Third light-shielding film 70: Storage capacitance 70a: First storage capacitance 7 b ... second storage capacitor 80 ... shielding layer 80a ... conductive light shielding layer 80b ... conductive light shielding layer second storage capacitor 81: second dielectric layer 101 ... the data line driving circuit 104 ... scan line driver circuit

Continued on the front page F term (reference) 2H092 GA51 JA25 JA33 JA35 JA46 JB51 JB64 JB69 KA04 KA05 KA10 KA22 KB25 MA05 MA07 MA08 MA13 MA18 MA19 MA27 MA29 MA30 MA37 NA01 NA04 NA07 NA16 PA02 PA04 PA06 PA08 PA09 5C058 AA06 AB01 AB02 AA07 BA03 BA43 CA19 DA13 DB04 EA03 EA04 EA07 ED15 FB12 FB15 FB19 GB01 5F110 AA21 BB01 BB02 BB04 CC02 DD02 DD03 DD12 DD13 DD14 DD25 EE04 EE05 EE09 FF02 FF03 FF09 FF23 FF32 GG02 GG13 GG13 GG13 GG13 GG02 HL07 HL14 HL23 HM14 HM15 HM18 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN44 NN46 NN54 PP03 PP10 PP33 QQ11

Claims (12)

[Claims] 1. An electro-optical device comprising: a substrate; a plurality of scanning lines and a plurality of data lines; a thin film transistor connected to the scanning line and the data line; and a pixel electrode connected to the thin film transistor. A semiconductor layer serving as a source region and a drain region of the thin film transistor; a gate electrode disposed on the semiconductor layer via a gate insulating film; a first interlayer insulating film disposed on the gate electrode; A second interlayer insulating film disposed on the interlayer insulating film, wherein the data line is a first interlayer insulating film formed on the first interlayer insulating film.
A first conductive layer arranged to be connected to the data line via a contact hole; and a first conductive layer arranged to be connected to the data line; A second conductive layer made of the same layer as the first conductive layer is connected to a drain region of the semiconductor layer via a second contact hole formed in the first interlayer insulating film;
An electro-optical device, wherein the device is arranged in an island shape so as to be connected to the pixel electrode via a third contact hole formed in the second interlayer insulating film. 2. The electro-optical device according to claim 1, wherein the first and second conductive layers have a light shielding property. 3. A storage capacitor connected to the thin film transistor, wherein the storage capacitor is formed of a first storage capacitor electrode extending from a semiconductor layer forming the drain region and a same material as the gate electrode. A first storage capacitor having an insulating thin film formed of the same layer as the gate insulating film between the second storage capacitor electrode and a second storage capacitor electrode formed of a part of the capacitor line; 3. The electro-optical device according to claim 1, further comprising a second storage capacitor including the first interlayer insulating film between the two conductive layers. 4. 4. The electro-optical device according to claim 1, wherein the first and second conductive layers are made of a different material from the data lines. 5. The semiconductor device according to claim 1, wherein the first and second conductive layers are mainly made of a metal silicide.
The electro-optical device according to any one of the above. 6. The electro-optical device according to claim 1, wherein the first interlayer insulating film is made of an insulating material having a high dielectric constant. 7. The insulating high dielectric constant material is made of at least one material selected from barium titanate, BST, RuO2, silicon oxynitride, tantalum oxide, silicon nitride, and silicon oxide. Item 7. An electro-optical device according to item 6. 8. The semiconductor device according to claim 2, wherein the second contact hole and the third contact hole are opened at different plane positions on the one substrate. An electro-optical device according to claim 1. 9. The method according to claim 2, wherein the second contact hole and the third contact hole are formed at the same position on the one substrate. Electro-optical device. 10. The semiconductor device according to claim 1, further comprising a base light-shielding film between the substrate and the semiconductor layer so as to cover at least a channel region of the semiconductor layer. An electro-optical device according to claim 1. 11. A method for manufacturing an electro-optical device, comprising: a plurality of scanning lines and a plurality of data lines on a substrate; a thin film transistor connected to the scanning line and the data line; and a pixel electrode connected to the thin film transistor. Forming a source / drain region and a semiconductor layer serving as the first storage capacitor electrode on the substrate; forming a gate insulating film of the thin film transistor and a dielectric film of the storage capacitor on the semiconductor layer; Forming the insulating thin film to be formed, forming the scanning line and the capacitor line on the insulating thin film, respectively, forming a first interlayer insulating film above the scanning line and the capacitor line, Forming first and second contact holes in the first interlayer insulating film on the source region and the drain region; and forming the first and second contact holes via the first contact holes. Forming the data line so as to be connected to the source region; and forming a first on the data line so as to be connected to the data line.
Forming a conductive layer and forming an island-shaped second conductive layer so as to be connected to the drain region; forming a second interlayer insulating film on the first and second conductive layers; Forming a third contact hole in the second interlayer insulating film on a second conductive layer; and forming the pixel electrode so as to be connected to the second conductive layer via the third contact hole. A method for manufacturing an electro-optical device, comprising: 12. The device according to claim 1, wherein the first and second conductive layers are made of a different material from the data lines.
2. The method for manufacturing an electro-optical device according to item 1.