JP2001186754A - Negative voltage generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a manufacturing process having a gate-source breakdown strength high enough to withstand a voltage equal to two times of an input voltage is required because that voltage is conventionally applied between the gate and source of an MOS transistor constituting a charge pump circuit, and to use a manufacturing process having a low gate-source breakdown strength withstanding a voltage of substantially the same level as the input voltage. SOLUTION: When a positive voltage Vcc1 is supplied to a voltage regulation circuit 40, the potential Vcc2 on a second feeder line 5 follows up variation of the output voltage Vo to take the potential level of the positive voltage Vcc1 for the output voltage Vo>=-VBE, a potential level shown by Vcc2=Vcc1-(|Vo|-VBE) for Vo<-VBE, and the potential level of VBE for Vo=-Vcc1. Consequently, the ON control voltage between the gate and source of the MOS transistor T4 in a charge pump circuit 10 has a constant level of Vcc2+|Vo|=VBE+Vcc1 regardless of variation of the output voltage Vo.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a negative voltage generating circuit using a charge pump circuit, and more particularly to a MOS integrated circuit for a charge pump circuit in a semiconductor integrated circuit using a Bi-CMOS process which can use a bipolar element.
The present invention relates to a negative voltage generating circuit suitable for use in a transistor having a manufacturing process in which a withstand voltage between a gate and a source of a transistor is lower than a withstand voltage between a drain and a source.

[0002]

2. Description of the Related Art As a negative current source having a low current capacity, a negative voltage generating circuit using a charge pump circuit which can be formed into a small and simple circuit is used. The basic operation principle of the charge pump circuit will be described with reference to FIG. In the figure,
SW1 to SW4 are switches, and C1 and C2 are capacitors. First, when the input voltage Vin of the positive voltage is supplied to the input terminal and the switches SW1 and SW2 are turned on and the switches SW3 and SW4 are turned off, the capacitor C
1 is charged. Next, when the switches SW1 and SW2 are turned off and the switches SW3 and SW4 are turned on, the electric charge charged in the capacitor C1 is discharged to charge the capacitor C2, and the output terminal of the negative voltage is output to the output terminal.
o is output. Hereinafter, switches SW1, SW2 and SW
3 and SW4, the capacitor C
2, a negative voltage Vo having a voltage value substantially equal to the input voltage Vin is output to the output terminal.

[0003] SW1 to SW of the above charge pump circuit
FIG. 7 shows an example in which 4 is constituted by MOS transistors. In the figure, T1 is a P-channel MOS transistor, T
2 to T4 are N-channel MOS transistors. The gate of each MOS transistor is driven by the output from the drive circuit. In the conventional example, the potentials of the gates G1, G2, G3, and G4 of each MOS transistor are, for example, shown in FIG.
The potential of the waveform shown in FIG. That is, the input voltage Vin
The positive voltage Vcc1 is supplied to the input terminal, the ground voltage is applied to the gate G1 of the MOS transistor T1, and the MOS
The positive voltage Vcc1 is supplied to the gate G2 of the transistor T2, and the MOS transistors T1 and T2 are turned on.
The ground voltage is supplied to the gate G3 of the OS transistor T3, and the output terminal voltage Vo is supplied to the gate G4 of the MOS transistor T4, so that the MOS transistors T3 and T4 are turned off, and the capacitor C1 is charged. Next, MOS
The positive voltage Vcc1 is supplied to the gate G1 of the transistor T1, and the output terminal voltage Vo is supplied to the gate G2 of the MOS transistor T2, and the MOS transistors T1 and T2 are turned off.
The positive voltage Vcc1 is supplied to the gates G3 and G4 of
The S transistors T3 and T4 are controlled to be turned on, the electric charge charged in the capacitor C1 is discharged and charged in the capacitor C2, and the negative voltage Vo is output to the output terminal. Below, MO
By repeatedly applying the control signal having the waveform of FIG. 8 to each gate of the S transistors T1, T2, T3, and T4,
Charge is accumulated in the capacitor C2, and the absolute value of the output terminal voltage Vo is the negative voltage Vss having substantially the same voltage value as the positive voltage Vcc1.
Is output.

[0004]

The gates G1 and G4 of the MOS transistors T1, T2, T3 and T4, respectively.
When the potentials of G2, G3, and G4 have the waveforms shown in FIG. 8, as shown in FIG.
A positive voltage V is applied between the gate and the source of the OS transistor T4.
A voltage equal to the sum of cc1 and the absolute value of the negative voltage Vo is applied. When the output voltage Vo = −Vcc1, the voltage between the gate and the source of the MOS transistor T4 is Vcc1 + | Vo | = 2.
When a voltage twice as high as Vcc1 and Vcc1 is applied and the MOS transistors T1, T2, T3, and T4 are manufactured by a process with a low gate-source withstand voltage that guarantees only the positive voltage Vcc1 as the gate-source withstand voltage, the MOS transistor T
4 cannot guarantee the breakdown voltage between the gate and the source, or
When the S transistors T1, T2, T3, and T4 are manufactured by a process having a high withstand voltage between the gate and the source that guarantees a withstand voltage of twice the positive voltage Vcc1 as a withstand voltage between the gate and the source, the element size generally increases, and the chip size increases. The problem of area increase occurs. The present invention has been made in order to solve the above-mentioned problem, and it is not necessary to manufacture the MOS transistor T4 in a process having a high withstand voltage between the gate and the source that guarantees a withstand voltage of twice the positive voltage Vcc1 as a withstand voltage between the gate and the source. Another object of the present invention is to provide a negative voltage generating circuit having a driving method capable of guaranteeing a withstand voltage between the gate and the source of the MOS transistor T4 when the MOS transistor T4 is turned on.

[0005]

In view of the above-mentioned object, the present inventors have conventionally proposed that a positive voltage Vcc1 be applied to the gate G4 of the MOS transistor T4 when the MOS transistor T4 is turned on.
In order to control the ON state of the MOS transistor T4, when no negative voltage is generated at the output terminal, the source is at the ground potential and the gate G
4, it is necessary to apply the positive voltage Vcc1, but when the output voltage Vo becomes the negative voltage Vss whose absolute value is substantially the same as the positive voltage Vcc1, the negative voltage Vss is applied to the source and the gate is G4 only needs to be a ground potential, and the applied voltage between the gate and the source is a positive voltage V regardless of a change in the output voltage.
The inventor of the present invention has focused on the fact that the potential of the gate G4 may be displaced by the same displacement as the output voltage so as to be constant at substantially the same voltage as cc1. A negative voltage generation circuit according to the present invention, a charge pump circuit that charges a capacitor with a positive voltage from an input terminal using a MOS transistor as a switching element and outputs a voltage charged in the capacitor as a negative voltage from an output terminal, A negative voltage generating circuit including a drive circuit for driving the MOS transistor, wherein the drive circuit outputs a secondary voltage reduced from the positive voltage by the same displacement as the potential of an output terminal; A level shift circuit for level-shifting the positive voltage to the secondary voltage by supplying a clock signal, and outputting the level shift circuit. An output of the level shift circuit is connected between the capacitor and the output terminal of the MOS transistor. Connected to the gate of the MOS transistor. According to the above means, a secondary voltage reduced by the same displacement as the potential of the output terminal from the positive voltage supplied to the input terminal is supplied to the gate of the MOS transistor of the charge pump circuit. A voltage twice as high as the positive voltage supplied to the input terminal is not applied between the source and the source, and a constant voltage substantially equal to the positive voltage Vcc1 is always applied regardless of the change in the output voltage Vo. Vcc1 + | Vo | = 2Vcc1 applied between the gate and source of the MOS transistor T4
It is not necessary to manufacture in a process with a high withstand voltage between the gate and the source that can withstand the voltage, and a process with a low withstand voltage between the gate and the source withstands substantially the same voltage as the positive voltage Vcc1.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A negative voltage generating circuit according to a first embodiment of the present invention will be described below with reference to FIGS. 1, 4 and 5. FIG. Note that the same components as those in FIG. 7 are denoted by the same reference numerals and description thereof is omitted. 1, the negative voltage generation circuit includes a charge pump circuit 10 having the same circuit configuration as the charge pump circuit shown in FIG. 7, and a drive circuit 20 for driving the charge pump circuit 10.
Is supplied as a positive voltage Vcc1 as an input voltage Vin, and a clock signal is supplied as a control signal Vc to a control terminal 2 so that the positive voltage Vcc1 and the absolute value are substantially A negative voltage Vss having the same voltage value is output. The drive circuit 20 includes a level shift circuit 30 for level-shifting and supplying a clock signal for driving a gate of a MOS transistor, which is a switch element included in the charge pump circuit 10, and a second terminal connected to the input terminal 1. The positive voltage Vcc1 is supplied to one power supply line 4, and the positive voltage Vcc2 is supplied to the level shift circuit 30 via the second power supply line 5 by being displaced from the positive voltage Vcc1 by the same displacement as the output voltage Vo of the output terminal 3. And a voltage adjustment circuit 40 for performing the adjustment.

The level shift circuit 30 is a P-channel type M
A first series circuit 32 in which an N-channel MOS transistor T7 is connected to a first CMOS inverter 31 including an OS transistor T5 and an N-channel MOS transistor T6, and a P-channel MOS transistor T8 and an N-channel MOS transistor T9 The 2nd CMO
An N-channel MOS transistor T is connected to the S inverter 33.
10 and a P-channel type M
A third CMOS inverter 35 including an OS transistor T11 and an N-channel MOS transistor T12;
A fourth CMOS inverter 36 including a P-channel MOS transistor T13 and an N-channel MOS transistor T14 is included. The first series circuit 32 and the second series circuit 34 are connected in parallel so that the second power supply line 5 and the third
The first CMOS inverter 3 connected between the power supply lines 6
1 has an input connected to the control terminal 2 and an output connected to the gate of the MOS transistor T10 and the input of the fourth CMOS inverter 36. The second CMOS inverter 33 has an input connected to the output of the third CMOS inverter 35 and an output connected to M.
It is connected to the gate of OS transistor T7. Third
The CMOS inverter 35 is connected between the second power supply line 5 and the ground, and the input is connected to the control terminal 2. The fourth CMOS inverter 36 is connected between the second power supply line 5 and the third power supply line 6, and its output is connected to the gate G4 of the MOS transistor T4 of the charge pump circuit 10.

In the level shift circuit 30 having the above configuration, when the "H (high)" level of the clock signal, that is, the positive voltage Vcc1, is supplied to the control terminal 2, the first CMOS
The MOS transistor T5 of the inverter 31 is turned off. At this time, since the MOS transistors T6 and T7 of the first CMOS inverter 31 are both kept off, the output of the first CMOS inverter 31 is output to the second power supply line. 5 and an intermediate potential between the potential Vo of the third power supply line 6. Then, the third CMO
The “H (high)” level of the clock signal supplied to the S inverter 35 is inverted by the third CMOS inverter 35, and the “L (low)” level of the clock signal, that is, the ground voltage is supplied to the input of the second CMOS inverter 33. Then, the MOS transistor T8 of the second CMOS inverter 33 is turned on, so that the second CMOS inverter 3
3 becomes the potential Vcc2 of the second power supply line, whereby the MOS transistor T7 is completely turned on.
The output of the first CMOS inverter 31 is the third power supply line 6
Potential Vo.

On the other hand, "L" of the clock signal is applied to the control terminal 2.
(Low) "level, that is, when the ground voltage is supplied, an operation symmetric to the above operation is performed, and the first CMO
The output of the S inverter 31 is the potential Vcc of the second power line 5
The output of the second CMOS inverter 33 becomes the potential Vo of the third power supply line 6. Therefore, when the "H (high)" level of the clock signal is supplied to the control terminal 2, the output of the first CMOS inverter 31, which is the potential Vo of the third power supply line 6, is inverted by the fourth CMOS inverter 36, and the charge pump circuit 10 MOS transistors T4
When the potential Vcc2 of the second power supply line 5 is supplied to the gate G4 and the "L (low)" level of the clock signal is supplied, the first CMOS which is the potential Vcc2 of the second power supply line 5 is supplied.
The output of the inverter 31 is inverted by the fourth CMOS inverter 36, and the potential Vo of the third power supply line 6 is supplied to the gate G4 of the MOS transistor T4 of the charge pump circuit 10. In the present embodiment, the output of the first CMOS inverter 31 is connected to the gate G4 of the MOS transistor T4 of the charge pump circuit 10 via the fourth CMOS inverter 36 so that the output of the MOS transistor T4 Although the input waveform of the gate G4 is non-inverted, the output of the second CMOS inverter 33 is connected to the gate G4 of the MOS transistor T4 via the fourth CMOS inverter 36, and the output of the MOS transistor T4 is controlled with respect to the clock signal waveform of the control terminal 2. The input waveform of the gate G4 may be inverted. In the present embodiment, the first
As a CMOS inverter connected between the CMOS inverter 31 and the gate G4 of the MOS transistor T4,
Although one CMOS inverter 36 is connected, a plurality of CMOS inverters may be connected as necessary.

The voltage adjusting circuit 40 includes a first resistor R1 as a first dividing unit having a fixed resistance value as a detecting unit, and a second resistor whose resistance value changes according to the detection result of the potential of the output terminal 3.
An NPN detection transistor T15 as a dividing means and a second resistor R connected in series to the detection transistor 15
2 is connected between the first power supply line 4 and the third power supply line 6, and a third resistor R3 as control means;
The series circuit 42 with the PNP control transistor T16 is the first
An NPN output transistor T17 is connected between the power supply line 4 and the third power supply line 6, and is connected between the first power supply line 4 and the second power supply line 5 as output means. In the series circuit 41, the first resistor R1 is connected to the first power line 4
, And the second resistor R2 are connected to the third power supply line 6, and the transistor T15 is connected to the first resistor R1 and the second resistor R2.
Connected between the collector and the emitter, the transistor T
The 15 bases are grounded. The series circuit 42 has a resistor R
3 is connected to the first power supply line 4 and the transistor T16
Is connected between the resistor R3 and the third power supply line 6 by an emitter and a collector, and the base of the transistor 16 is connected to the first resistor R3.
1 and the transistor T15.
The transistor T17 is connected between the first power supply line 4 and the second power supply line 5 by a collector and an emitter. The base of the transistor T17 has a third resistor R3 and a transistor T16.
Is connected to the connection point.

[0011] In the voltage regulating circuit 40 having the above configuration, the potential Vo of the third power supply line 6, the base-emitter forward voltage of the transistor T15 as _{V BE,} Vo ≧ -
For V _BE, transistor T15, T16 is in the off state, through the base resistor R3 of the transistor T17 positive voltage Vcc1 is applied, the transistor T17 is in the on state of saturation, the potential Vcc2 of the second power supply line 5 Vcc2 =
Vcc1. On the other hand, when the potential Vo of the third power supply line 6 is V
In the case of o _{<-V BE,} transistor T15, T16, T
Reference numeral 17 denotes an ON state in which the degree of saturation or non-saturation changes according to the potential Vo of the third power supply line 6, and the collector voltage (base voltage of T16) V of the transistor T15
_CT15 becomes the potential shown by the following equation (1), and the potential Vcc2 of the second power supply line 5 becomes the potential shown by the following equation (2). _{V CT15 = Vcc1- (h FE /} (1 + h FE)) (R1 / R2) (| Vo | -V BE) ...... (1) h FE: current amplification factor of the transistor T15 V _BE: base of the transistor T15・ Emitter forward voltage Vcc2 = Vct15 + V _BET16 -V _BET17 (2) V _BET16 : forward voltage between base and emitter of transistor T16 V _BET17 : forward voltage between base and emitter of transistor T17 , (1), (2) where R1 = R
2, h _FE / (1 + h _FE ) = 1, V _BET16 = V _BET17 and V
cc2 is approximated by the following equation. Vcc2 = Vcc1- (| Vo | -V BE) ...... (3) that is, when the potential Vo of the third power supply line 6 is Vo <-V _BE, the voltage adjustment circuit 40 as shown by (3) the The potential Vcc1 of the first power supply line 4 and the potential Vo of the third power supply line 6
Is supplied, the second as the output of the voltage adjustment circuit 40
The potential Vcc2 of the power supply line 5 decreases from Vcc1 + V _BE following the increase of the absolute value | Vo | of the potential of the third power supply line 6, and accordingly, the potential Vcc2 between the second power supply line 5 and the third power supply line 6 The potential difference is expressed by the following equation (4).
Is constant regardless of the change in the negative potential Vo. Vcc2 + | Vo | = Vcc1- ( | Vo | -V BE) + | Vo | = Vcc1 + V BE ...... (4)

In the negative voltage generating circuit having the above configuration, the gate of each MOS transistor of the charge pump circuit 10 is driven by a control signal having the waveform shown in FIG. 4 from the drive circuit, and the gate G1 of each of the MOS transistors T1, T2, T3. , G2, and G3 are supplied from a drive circuit (not shown) similar to the conventional drive circuit, and a control signal to the gate G4 of the MOS transistor T4 is supplied from the drive circuit 20. That is, the positive voltage Vcc1 is supplied to the input terminal 1 as the input voltage Vin, the ground voltage is applied to the gate G1 of the MOS transistor T1, and the MOS transistor T
The positive voltage Vcc1 is supplied to the gate G2 of the MOS transistor T2 to turn on the MOS transistors T1 and T2, the ground voltage is supplied to the gate G3 of the MOS transistor T3, and the voltage Vo of the output terminal 3 is supplied to the gate G4 of the MOS transistor T4. As a result, the MOS transistors T3 and T4 are turned off,
The capacitor C1 is charged. Next, the positive voltage Vcc1 is supplied to the gate G1 of the MOS transistor T1, and the voltage Vo of the output terminal 3 is supplied to the gate G2 of the MOS transistor T2, so that the MOS transistors T1 and T2 are turned off. Gate G
3, the positive voltage Vcc1 is supplied to the gate G4 of the MOS transistor T4, and the positive voltage Vcc2 is supplied to the gate G4 of the MOS transistor T4.
3, T4 is turned on, and the electric charge charged in the capacitor C1 is discharged and charged in the capacitor C2.
Outputs the output voltage Vo. Hereinafter, the gates G1, G2, G of the MOS transistors T1, T2, T3, T4
3, a charge is accumulated in the capacitor C2 by repeatedly applying the control signal having the waveform of FIG. 4 to the G4, and after a transient change as described later as the output voltage Vo, a voltage having substantially the same voltage value as the positive voltage Vcc1. The negative voltage Vss is output.

The gate potential Vcc2 at the time of ON control of the gate G4 of the MOS transistor T4 shown in FIG. 4 changes following the change in the potential Vo of the output terminal 3, as shown in FIG. Specifically, the positive voltage Vcc1 is supplied as an input voltage Vin to the input terminal 1, the control terminal 2 clock signal is started to be applied to, when the potential Vo at the output terminal 3 is Vo ≧ -V _BE, from the input terminal 1 Positive voltage V via first power supply line 4
cc1 and the output voltage Vo from the output terminal 3 via the third power supply line 6 to the voltage adjustment circuit 40, and the potential V of the second power supply line 5 as an output of the voltage adjustment circuit 40.
cc2 has substantially the same potential level as the positive voltage Vcc1 (hereinafter, Vcc2
= Vcc1). At this time, when the “H (high)” level of the clock signal is supplied to the control terminal 2, the “H (high)” level of the clock signal, that is, the potential level of the positive voltage Vcc 1 is changed by the level shift circuit 30. 2 The level of the potential of the power supply line 5 is shifted to Vcc2 = Vcc1 (in this case, the same potential remains), and the MOS of the charge pump circuit 10 is
The potential of the gate G4 of the transistor T4 becomes the potential level Vcc2 = Vcc1 of the second power supply line 6, between the gate and source of the MOS transistor _{T4 Vcc2-Vo ≦ Vcc1 + V} BE
Is applied, the MOS transistor T4 is turned on, and the "L (low)" level of the clock signal is supplied.
(Low) "level, that is, the ground potential is
, That is, the potential Vo of the output terminal 3, and the MOS transistor T4 of the charge pump circuit 10
The potential of the gate G4 becomes the potential Vo of the output terminal 3 and the potential of M
Vo-Vo between the gate and source of the OS transistor T4
= 0V is applied, and the MOS transistor T4 is turned off.

Next, a clock signal is further supplied to the control terminal 2 from the above state, and the potential Vo of the output terminal 3 becomes Vo.
When <−V _BE , the potential Vcc2 of the second power supply line 5 as the output of the voltage adjustment circuit 40 becomes the potential represented by the above equation (3). At this time, when the “H (high)” level of the clock signal is supplied to the control terminal 2, the “H (high)” level of the clock signal, that is, the potential level of the positive voltage Vcc 1 is changed by the level shift circuit 30. The level of the MOS transistor T of the charge pump circuit 10 is shifted to the level Vcc2 of the second power supply line 5 having the potential expressed by the equation (3).
The potential of the gate G4 of No. 4 becomes the potential shown by the equation (3) as the potential level Vcc2 of the second power supply line 5,
Vcc2 + | Vo | = between the gate and source of the transistor T4
_{Vcc1- (| Vo | -V BE)} + | Vo | = voltage Vcc1 _{+ V BE} is applied, MOS transistor T4 is on-controlled,
When the “L (low)” level of the clock signal is supplied,
The level shift circuit 30 shifts the “L (low)” level of the clock signal, that is, the ground potential, to the potential of the third power supply line 6, that is, the potential Vo of the output terminal 3,
The potential of the gate G4 of the MOS transistor T4 of the charge pump circuit 10 becomes the potential Vo of the output terminal 3,
Vo−Vo = 0 between the gate and the source of the transistor T4
When the voltage of V is applied, the MOS transistor T4 is turned off.

Further, a clock signal is applied to the control terminal 2 from the above state, and the potential Vo of the output terminal 3 becomes -Vcc1.
, The potential level of the substantially same negative voltage Vss (hereinafter, Vo = Vss
= -Vcc1), the potential Vcc2 of the second power supply line 5 as the output of the voltage adjusting circuit 40 becomes Vcc2 = Vcc2.
1-a _{(| | Vo -V BE) =} Vcc1- (Vcc1-V BE) = V BE. At this time, when the "H (high)" level of the clock signal is supplied to the control terminal 2, the level shift circuit 30
In, "H (high)" level of the clock signal, i.e., the potential level of the positive voltage Vcc1 is the second level shift to the potential Vcc2 power supply line 5 of Vcc2 _{= V BE,} the gate of the MOS transistor T4 of the charge pump circuit 10 G4 potential becomes the potential level Vcc2 _{= V bE} of the second power supply line 6,
Vcc2 + | between the gate and source of the MOS transistor T4.
The voltage Vo | = _VBE + Vcc1 is applied, the MOS transistor T4 is turned on, and when the "L (low)" level of the clock signal is supplied, the level shift circuit 30
Then, the "L (low)" level of the clock signal, that is, the ground potential is level-shifted to the potential of the third power supply line 6, that is, the potential Vo = Vss = -Vcc1 of the output terminal 3, and the MOS of the charge pump circuit 10 Gate G4 of transistor T4
Becomes the potential Vo = Vss = −Vcc1 of the output terminal 3, and Vo is applied between the gate and source of the MOS transistor T4.
A voltage of -Vo = 0 V is applied, and the MOS transistor T4 is turned off.

As described above, the negative voltage generating circuit according to the present invention does not always set the potential of the gate G4 when the MOS transistor T4 is ON-controlled to the potential level of the positive voltage Vcc1, but the voltage adjusting circuit 40 The positive voltage Vcc1 is supplied to change the potential Vcc2 of the second power supply line 5 to the output voltage Vo ≧
At −V _BE , the potential level of the positive voltage Vcc1, Vo <−
At V _BE , Vcc 2 = Vcc 1-(| Vo−V _BE ), and at Vo = −Vcc 1, V _BE is displaced by the same level as the potential level of V _BE and the output voltage Vo.
The ON control voltage between the gate and the source of the MOS transistor T4 of the charge pump circuit 10 is Vcc2 + | Vo | = _VBE
+ Vcc1 and becomes constant regardless of changes in the output voltage Vo.
When the output voltage Vo ≧ _{-V BE,} the potential level of the positive voltage Vcc1, when Vo _{<-V BE,} (3) the potential of formula, when Vo = Vss = -Vcc1, the potential level of the VBE, the output The potential of the gate G4 is changed following the change of the voltage Vo, and the applied voltage between the gate and the source of the MOS transistor T4 is kept constant regardless of the change of the output voltage Vo, that is, Vcc2 + | Vo | = _VBE + Vcc1. So, M
Gate G when OS transistor T4 is ON-controlled
4 is always the potential level of the positive voltage Vcc1,
MOS transistor T4 when Vo = Vss = -Vcc1
Vcc1 + | Vo | applied between the gate and source of
It is not necessary to produce the gate and high source voltage process to withstand 2Vcc1, gate-source breakdown voltage V _BE
It can be manufactured by a process as low as + Vcc1.

Next, a negative voltage generating circuit according to a second embodiment of the present invention will be described with reference to FIG. Note that the same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted. In the figure, the difference from FIG. 1 is that a voltage adjustment circuit 60 instead of the voltage adjustment circuit 40 is connected to the level shift circuit 30 as the drive circuit 50. The voltage adjustment circuit 60 includes a first resistor R11 as a first dividing unit having a fixed resistance value as a detecting unit, and an NPN detecting unit as a second dividing unit whose resistance value changes according to a detection result of the potential of the output terminal 3. A series circuit 61 including a transistor T18 and a second resistor R12 connected in series to the transistor T18 forms a first power supply line 4
And the third power supply line 6, and as control means, a third resistor R13 and a fourth resistor R14, and the third resistor R13
13 and the fourth resistor R14 connected in series to each other.
PN first and second control transistors T19 and T2
0 and a fifth parallel resistor 62 connected in common to the emitters of the transistors T19 and T20.
An NPN output transistor T21 is connected between the first power supply line 4 and the second power supply line 5 as an output means. In the series circuit 61, the first resistor R11 is connected to the first power line 4
And the second resistor R12 are connected to the third power supply line 6, and the transistor T18 is connected to the first resistor R11 and the second resistor R12.
A collector and an emitter are connected between the transistors 12, and the base of the transistor T18 is grounded. In the series circuit 62, the third resistor R13 and the fourth resistor R14 are connected to the first power line 4
, The fifth resistor R15 is connected to the third power supply line 6, the transistor T19 is connected between the third resistor R13 and the fifth resistor R15 by a collector and an emitter, and the base of the transistor T19 is connected to the first resistor R11. The transistor T20 is connected to a connection point with the detection transistor T18, the transistor T20 is connected between the fourth resistor R14 and the fifth resistor R15 by a collector and an emitter, and the base of the transistor T20 is connected to the emitter of the transistor T21. The transistor T21 is connected between the first power supply line 4 and the second power supply line 5 by a collector and an emitter, and the base of the transistor T21 is connected to a connection point between the fourth resistor R14 and the second control transistor 20.

In the voltage adjustment circuit 60 having the above configuration, the transistors T19, T20, and T21 form a voltage follower differential amplifier circuit.
Operate so that the base potential of the transistor T20 becomes the base potential of the transistor T20 (emitter potential of the transistor T21). That is, the potential Vcc2 of the second power supply line becomes the same potential as the collector potential of the transistor T18. Therefore,
Potential Vo of the third power supply line 6, the base-emitter forward voltage of the transistor T18 as _{V BE,} Vo ≧
For -V _BE, transistor T18 is turned off, the collector potential of the transistor T18 is next to a positive voltage Vcc1, the potential Vcc2 of the second power supply line 5 is Vcc2 = Vcc1. On the other hand, when the potential Vo of the third power supply line 6 is Vo <−V
_In the case of _BE , the collector voltage of the transistor T18 (T1
9 (base voltage) V _CT18 , that is, the potential Vcc2 of the second power supply line is a potential represented by the following equation (5). _{Vcc2 = Vcc1- (h FE / (} 1 + h FE)) (R11 / R12) (| Vo | -V BE) ...... (5) h FE: current amplification factor of the transistor T18 V _BE: base of the transistor T18 · Emitter forward voltage In the following description, in equation (5), R11 = R12, _hFE
Assuming that / (1 + h _FE ) = 1, Vcc2 is approximated by the following equation. _{Vcc2 = Vcc1- (| Vo | -V} BE) ...... (6) below, is the same as the first embodiment, the description thereof is omitted.

In the first and second embodiments, the MOS transistors included in the level shift circuits 30 of the drive circuits 20 and 50 can be formed by reversing the conductivity types. That is, an N-channel MOS transistor and an N-channel M transistor
The OS transistor may be configured as a P-channel MOS transistor, for example, the circuit shown in FIG. 1 may be the circuit shown in FIG.

[0020]

According to the present invention, the MOS transistor T
4 the potential of the gate G4 when it is on-controlled, when the output voltage Vo ≧ -V _BE, the potential level of the positive voltage Vcc1,
When Vo _{<-V BE,} (3) and Equation (6) the potential of formula, when Vo = Vss = _-Vcc1, the potential level of _{V BE,} of the gate G4 to follow the change in the output voltage Vo Since the potential is changed and the applied voltage between the gate and the source of the MOS transistor T4 is made substantially the same as the input voltage and kept constant regardless of the change in the output voltage Vo, the input voltage between the gate and the source of the MOS transistor T4 becomes 2 A double voltage is not applied, and there is no need to manufacture by a process having a high withstand voltage between the gate and the source that withstands a voltage twice as high as the input voltage, and the withstand voltage between the gate and the source is almost equal to the input voltage. Can be manufactured with a low process.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a negative voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a negative voltage generating circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a modified example of the negative voltage generation circuit shown in FIG.

FIG. 4 is a waveform chart showing the potential of the gate of each transistor of the charge pump circuit used in the circuit of FIG.

FIG. 5 is a waveform chart showing a change in potential of a gate G4 of a transistor T4 of the charge pump circuit used in the circuit of FIG.

FIG. 6 is a circuit diagram illustrating the operation principle of a charge pump circuit.

FIG. 7 is a circuit diagram of a general charge pump circuit.

FIG. 8 is a waveform chart showing a conventional gate potential of each transistor for driving the charge pump circuit of FIG. 7;

FIG. 9 is a waveform diagram showing a conventional gate-source applied voltage of each transistor for driving the charge pump circuit of FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 input terminal 3 output terminal 10 charge pump circuit 20, 50 drive circuit 30 level shift circuit 40, 60 voltage adjustment circuit 41, 61 detection means (series circuit) 42 control means (series circuit) 62 control means (series-parallel circuit) T1 , T2, T3, T4 MOS transistor T15, T18 NPN detection transistor T16, T19, T20 Control transistor T17, T21 Output means (NPN output transistor) C1 capacitor

Claims (7)

[Claims] A charge pump circuit for charging a capacitor with a positive voltage from an input terminal using a MOS transistor as a switching element and outputting the voltage charged in the capacitor as a negative voltage from an output terminal, and driving the MOS transistor A voltage adjustment circuit that outputs a secondary voltage reduced from the positive voltage by the same displacement as the potential of an output terminal; and a clock signal supply circuit. The positive voltage is
A level shift circuit for level-shifting to the next voltage and outputting the voltage, and an output of the level shift circuit is connected to a gate of a MOS transistor connected between the capacitor and the output terminal among the MOS transistors. And a negative voltage generating circuit. 2. The voltage adjustment circuit according to claim 1, wherein said voltage adjustment circuit detects a potential of said output terminal, and control means generates a control voltage for outputting said secondary voltage based on a detection result of said detection means. 2. The negative voltage generating circuit according to claim 1, further comprising an output unit that outputs the secondary voltage based on the control voltage. 3. The first dividing means, wherein the detecting means is connected to the input terminal and has a fixed resistance value, and the second dividing means is connected to the output terminal and changes the resistance value in accordance with the detection result of the potential of the output terminal. 3. A negative voltage generating circuit according to claim 2, wherein said negative voltage generating circuit comprises a series circuit with said means. 4. The first dividing means comprises a first resistor,
The second dividing means includes an NPN detecting transistor having a collector connected to the first resistor and a base grounded, and a second resistor connected between the emitter of the detecting transistor and the output terminal. 4. The negative voltage generating circuit according to claim 3, further comprising an NPN output transistor connected between said input terminal and said level shift circuit. 5. The control means comprises a series circuit of a third resistor connected to the input terminal, and a PNP control transistor connected between the third resistor and the output terminal. 5. The negative voltage generation circuit according to claim 4, wherein a connection point is connected to a base of said output transistor, and a base of said control transistor is connected to a series connection point of said detection means. 6. The control means includes a third resistor and a fourth resistor connected to the input terminal, a fifth resistor connected to the output terminal, and a connection between the third resistor and the fifth resistor. And a series-parallel circuit of an NPN first control transistor and an NPN second control transistor connected between the fourth resistor and the fifth resistor, the base of the first control transistor being connected to the series of the detection means. Connected to a connection point, a base of the second control transistor is connected to an emitter of the output transistor, and a series connection point of the second control transistor and the fourth resistor is connected to a base of the output transistor. The negative voltage generating circuit according to claim 4, wherein: 7. An on-control voltage applied from said drive circuit between a gate and a source of a MOS transistor connected between said capacitor and said output terminal among said MOS transistors of said charge pump circuit is said positive voltage and said detection voltage. 5. The negative voltage generation circuit according to claim 4, wherein the sum is a sum of the forward voltage VBE of the transistor.