CN110350778A - Negative voltage generator and its negative voltage detector - Google Patents

Abstract

The present invention provides a negative voltage generator and a negative voltage detector thereof. The negative voltage generator is used to provide a negative reference voltage. The negative voltage generator includes a negative voltage detector and a voltage pump circuit. The negative voltage detector includes a first circuit, a second circuit and a comparison circuit. The first circuit is used to receive a negative reference voltage and generate a first voltage according to the negative reference voltage. The second circuit is used to generate a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and compares the first voltage and the second voltage to generate a control signal. The voltage pump circuit is coupled to the negative voltage detector to receive the control signal and generates a negative reference voltage according to the control signal.

Description

Negative voltage generator and its negative voltage detector

technical field

The invention relates to a voltage generating device, in particular to a negative voltage generator and a negative voltage detector thereof.

Background technique

A general negative voltage generator first generates a positive set voltage, and then converts the positive set voltage into a negative reference voltage through its negative pump circuit, so as to provide a negative reference voltage at its output terminal. The voltage absolute value of the negative reference voltage is equal to the voltage value of the set voltage. However, the settling time of the negative reference voltage generated by the above-mentioned negative voltage generator is very long. In addition, even after the settling time, there is still a spike current in the above-mentioned negative voltage generator.

Contents of the invention

In view of this, the present invention provides a negative voltage generator and a negative voltage detector thereof, which can reduce the settling time of the negative reference voltage to quickly provide a stable negative reference voltage, and after the negative reference voltage reaches a set value, the negative voltage There is no surge current in the voltage generator.

The negative voltage generator of the present invention is used for providing a negative reference voltage. The negative voltage generator includes a negative voltage detector and a voltage pump circuit. The negative voltage detector includes a first circuit, a second circuit and a comparison circuit. The first circuit is used for receiving a negative reference voltage and generating a first voltage according to the negative reference voltage. The second circuit is used for generating a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and compares the first voltage and the second voltage to generate a control signal. The voltage pump circuit is coupled to the negative voltage detector to receive the control signal, and generates a negative reference voltage according to the control signal.

In an embodiment of the present invention, the first circuit includes a first P-type transistor, a first resistor, and a first current source. The first terminal of the first P-type transistor is coupled to the ground voltage, and the control terminal of the first P-type transistor receives a negative reference voltage. The first terminal of the first resistor is coupled to the second terminal of the first P-type transistor. The first current source is coupled to the second end of the first resistor to provide a first voltage. The second circuit includes a second P-type transistor and a second current source. The first terminal and the control terminal of the second P-type transistor are coupled to the ground voltage, and the second terminal of the second P-type transistor provides a second voltage. The second current source is coupled to the second terminal of the second P-type transistor.

In an embodiment of the invention, the body of the first P-type transistor is coupled to the second end of the first resistor. The second circuit also includes a second resistor. A first end of the second resistor is coupled to the second end of the second P-type transistor, and a second end of the second resistor is coupled to the second current source and the body of the second P-type transistor.

In an embodiment of the present invention, the second circuit further includes a third resistor. A first end of the third resistor is coupled to the ground voltage, and a second end of the third resistor is coupled to the first end of the second P-type transistor.

In an embodiment of the present invention, when the first voltage is greater than the second voltage, the comparison circuit generates a control signal to enable the voltage pump circuit, so that the voltage pump circuit increases the absolute value of the negative reference voltage according to the power supply voltage.

In an embodiment of the present invention, when the first voltage is equal to the second voltage, the comparison circuit generates a control signal to disable the voltage pump circuit, so that the voltage pump circuit maintains the absolute value of the negative reference voltage at the set voltage value, Wherein the set voltage value is less than the absolute value of the voltage of the power supply voltage.

In an embodiment of the invention, the voltage pump circuit includes a clock signal generating circuit and a negative pump circuit. The clock signal generating circuit is used for generating a clock signal group according to the control signal. The negative pump circuit is coupled to the clock signal generating circuit to receive the clock signal set, and generates a negative reference voltage according to the clock signal set and the power supply voltage, wherein the absolute value of the negative reference voltage is smaller than the absolute voltage value of the power supply voltage.

The negative voltage detector of the present invention is used for detecting negative reference voltage. The negative voltage detector includes a first circuit, a second circuit and a comparison circuit. The first circuit is used for receiving a negative reference voltage and generating a first voltage according to the negative reference voltage. The second circuit is used for generating a second voltage. The comparison circuit is coupled to the first circuit to receive the first voltage, coupled to the second circuit to receive the second voltage, and compares the first voltage and the second voltage to determine whether the absolute value of the negative reference voltage is equal to the set voltage value .

Based on the above, the negative voltage generator of the embodiment of the present invention uses the power supply voltage to generate the negative reference voltage. Based on the absolute value of the voltage of the power supply voltage being greater than the absolute value of the voltage of the negative reference voltage, the absolute value of the voltage of the negative reference voltage can be reached quickly. Set the voltage value. Besides, the negative voltage detector of the embodiment of the present invention does not draw current from the negative reference voltage. Therefore, after the absolute value of the voltage of the negative reference voltage reaches the set voltage value, the voltage pump circuit in the negative voltage generator can stop pumping to avoid surge current, while the absolute value of the voltage of the negative reference voltage can still be maintained at Set the voltage value.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

The accompanying drawings, which follow and form a part of the specification of this invention, illustrate example embodiments of the invention and together with the description explain the principles of the invention.

FIG. 1 is a schematic circuit block diagram of a negative voltage generator according to an embodiment of the present invention.

FIG. 2 is a schematic circuit block diagram of a voltage pump circuit according to an embodiment of the invention.

FIG. 3 is a schematic diagram of a circuit structure of a negative pump circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of signal waveforms of a clock signal group according to an embodiment of the present invention.

5A is a schematic circuit diagram of a first circuit and a second circuit of a negative voltage detector according to an embodiment of the present invention.

5B is a schematic circuit diagram of a first circuit and a second circuit of a negative voltage detector according to another embodiment of the present invention.

5C is a schematic circuit diagram of the first circuit and the second circuit of the negative voltage detector according to another embodiment of the present invention.

5D is a schematic circuit diagram of the first circuit and the second circuit of the negative voltage detector according to another embodiment of the present invention.

【Symbol Description】

100: negative voltage generator

120: Negative voltage detector

121, 521A, 521B, 521C, 521D: first circuit

122, 522A, 522B, 522C, 522D: second circuit

123: Comparison circuit

140: Voltage pump circuit

142: Clock signal generation circuit

144: Negative pump circuit

C1, CL: Capacitor

CS: control signal

GND: ground voltage

I1, I2: current source

M1, M2: P-type transistors

NVref: negative reference voltage

R1, R2, R3: Resistors

S_PH: clock signal group

S_PH1, S_PH2: clock signal

SW1～SW4: switch

TP1, TP2: time interval

V1: first voltage

V2: second voltage

VDD: supply voltage

VR3: across voltage

Vsg: voltage difference

Vset: set voltage value

Detailed ways

In order to make the content of the present invention more comprehensible, the following specific embodiments are taken as examples in which the present invention can be implemented. In addition, wherever possible, elements/components with the same reference numerals are used in the drawings and embodiments to represent the same or similar components.

FIG. 1 is a schematic circuit block diagram of a negative voltage generator according to an embodiment of the present invention. Referring to FIG. 1 , the negative voltage generator 100 is used to provide a negative reference voltage NVref, that is, the voltage of the negative reference voltage NVref is lower than zero volts. The negative voltage generator 100 includes a negative voltage detector 120 and a voltage pump circuit 140 . The negative voltage detector 120 may include a first circuit 121 , a second circuit 122 and a comparison circuit 123 , but the invention is not limited thereto. The first circuit 121 is used for receiving the negative reference voltage NVref, and generating the first voltage V1 according to the negative reference voltage NVref. The second circuit 122 is used to generate the second voltage V2. The comparison circuit 123 is coupled to the first circuit 121 to receive the first voltage V1, and coupled to the second circuit 122 to receive the second voltage V2. The comparison circuit 123 compares the first voltage V1 and the second voltage V2 to determine whether the absolute value of the negative reference voltage NVref is equal to the set voltage value Vset, and generates a control signal CS accordingly. The voltage pump circuit 140 is coupled to the negative voltage detector 120 to receive the control signal CS, and generates a negative reference voltage NVref according to the control signal CS.

In an embodiment of the present invention, when the first voltage V1 is greater than the second voltage V2, the comparison circuit 123 judges that the absolute value of the negative reference voltage NVref is less than the set voltage value Vset, so the comparison circuit 123 can generate the first level The control signal CS (for example, logic high level) enables the voltage pump circuit 140, causing the voltage pump circuit 140 to perform pumping operation according to the power supply voltage VDD to increase the absolute value of the voltage of the negative reference voltage NVref, wherein the power supply voltage VDD is a positive voltage, And the set voltage value Vset is lower than the voltage value of the power supply voltage VDD. Relatively, when the first voltage V1 is equal to the second voltage V2, the comparison circuit 123 judges that the absolute voltage value of the negative reference voltage NVref is equal to the set voltage value Vset, so the comparison circuit 123 can generate a second level (such as a logic low level ) control signal CS to disable the voltage pump circuit 140, causing the voltage pump circuit 140 to stop the pumping operation to maintain the absolute value of the voltage of the negative reference voltage NVref at the set voltage value Vset, wherein the first level and the second level are complementary . It can be understood that the absolute value of the negative reference voltage NVref is smaller than the voltage value of the power supply voltage VDD.

Incidentally, the relationship between the logic high and low levels of the control signal CS and whether the voltage pump circuit 140 is enabled or not in the above example is just an example. Those skilled in the art know that the relationship between the logic high and low levels of the control signal CS and whether the voltage pump circuit 140 is enabled or not can be defined by the designer according to actual requirements.

FIG. 2 is a schematic circuit block diagram of a voltage pump circuit according to an embodiment of the invention. Referring to FIG. 2 , the voltage pump circuit 140 may include a clock signal generating circuit 142 and a negative pump circuit 144 , but the present invention is not limited thereto. The clock signal generating circuit 142 can generate the clock signal set S_PH according to the control signal CS. The negative pump circuit 144 is coupled to the clock signal generating circuit 142 to receive the clock signal set S_PH, and can generate a negative reference voltage NVref according to the clock signal set S_PH and the power voltage VDD.

In an embodiment of the present invention, the clock signal generating circuit 142 can be realized by a known clock signal generating circuit. In an embodiment of the present invention, the negative pump circuit 144 can be realized by using the two-phase negative pump circuit shown in FIG. 3 . Please refer to FIG. 2 and FIG. 3 together, the negative pump circuit 144 may include capacitors C1 and CL and switches SW1 - SW4 , but the present invention is not limited thereto. The first end of the switch SW1 is coupled to the power voltage VDD. The second end of the switch SW1 is coupled to the first end of the capacitor C1. The first end of the switch SW2 is coupled to the ground voltage GND. The second end of the switch SW2 is coupled to the second end of the capacitor C1. A first terminal of the switch SW3 is coupled to a first terminal of the capacitor C1. The second end of the switch SW3 is coupled to the ground voltage GND. A first terminal of the switch SW4 is coupled to a second terminal of the capacitor C1. The first end of the capacitor CL is coupled to the ground voltage GND. The second terminal of the capacitor CL is coupled to the second terminal of the switch SW4 to provide a negative reference voltage NVref. In addition, the clock signal group S_PH (shown in FIG. 2 ) may include, for example, clock signals S_PH1 and S_PH2 as shown in FIG. In the time interval of logic high level, the switches SW1 and SW2 in FIG. 3 are controlled by the clock signal S_PH1, and the switches SW3 and SW4 are controlled by the clock signal S_PH2, but the present invention is not limited thereto. In another embodiment of the present invention, the switches SW1 and SW2 are controlled by the clock signal S_PH2, and the switches SW3 and SW4 are controlled by the clock signal S_PH1.

Please refer to FIG. 3 and FIG. 4 together. It is assumed that the switches SW1 and SW2 can be turned on in response to the clock signal S_PH1 of logic high level, and the switches SW1 and SW2 can be turned on in response to the clock signal S_PH1 of logic low level. To turn off, the switches SW3 and SW4 can be turned on in response to the clock signal S_PH2 of logic high level, and the switches SW3 and SW4 can be turned off in response to the clock signal S_PH2 of logic low level. Therefore, in the time interval TP1 shown in FIG. 4 , the switches SW1 and SW2 are turned on and the switches SW3 and SW4 are turned off, so that the power supply voltage VDD charges the capacitor C1 . Then, in the time interval TP2 shown in FIG. 4 , the switches SW1 and SW2 are in the off state and the switches SW3 and SW4 are in the on state, so the capacitor C1 transfers the stored charge to the capacitor CL (that is, the capacitor C1 is connected to the capacitor CL). CL charging) to decrease the negative reference voltage NVref (ie increase the absolute value of the negative reference voltage NVref). By repeatedly switching the logic level of the clock signal S_PH1 and the logic level of the clock signal S_PH2, the capacitor C1 can be repeatedly charged and the capacitor CL can be charged to gradually reduce the negative reference voltage NVref (that is, gradually increase The voltage absolute value of the negative reference voltage NVref), until the voltage absolute value of the negative reference voltage NVref is equal to the set voltage value Vset.

Since the voltage value of the power supply voltage VDD is greater than the set voltage value Vset, compared with the general use of a voltage source with the set voltage value Vset to charge the capacitor C1, the use of the power supply voltage VDD to charge the capacitor C1 in this embodiment can effectively improve the performance of the capacitor. The amount of charge stored in C1 and the amount of charge transferred from the capacitor C1 to the capacitor CL can be increased, so the falling speed of the negative reference voltage NVref can be accelerated (that is, the rising speed of the absolute value of the negative reference voltage NVref can be accelerated), thereby reducing Settling time of negative reference voltage NVref. In addition, after the absolute value of the negative reference voltage NVref is equal to the set voltage value Vset, the clock signal generating circuit 142 in FIG. The logic level of the pulse signal S_PH2 (that is, the logic levels of the pulse signals S_PH1 and S_PH2 will no longer transition), so that the negative pump circuit 144 stops the pumping operation (details will be described later). In this way, it is possible to avoid the surge current generated by the switch SW1 - SW4 being switched on and off.

5A is a schematic circuit diagram of a first circuit and a second circuit of a negative voltage detector according to an embodiment of the present invention. Referring to FIG. 5A , the first circuit 521A may include a P-type transistor M1 , a resistor R1 and a current source I1 . A first terminal of the P-type transistor M1 is coupled to the ground voltage GND. The control terminal of the P-type transistor M1 receives the negative reference voltage NVref. A first end of the resistor R1 is coupled to a second end of the P-type transistor M1. The current source I1 is coupled to the second end of the resistor R1 to provide the first voltage V1. The second circuit 522A includes a P-type transistor M2 and a current source I2. The first terminal and the control terminal of the P-type transistor M2 are coupled to the ground voltage GND. The second terminal of the P-type transistor M2 provides a second voltage V2. The current source I2 is coupled to the second terminal of the P-type transistor M2.

In an embodiment of the present invention, the P-type transistors M1 and M2 can be P-type MOSFETs of the same size, so the first voltage V1 and the second voltage V2 can be expressed as formula (1) and formula (2) respectively ), where Vref is the absolute value of the negative reference voltage NVref, Vsg is the voltage difference between the second terminal of the P-type transistor M1 (or P-type transistor PM2) and the control terminal, and I is the output current of the current source I1 value, and R is the resistance value of resistor R1.

V1＝-Vref+Vsg+Vset＝-Vref+Vsg+I×R Formula (1)

V2＝Vsg formula (2)

When the voltage absolute value Vref of the negative reference voltage NVref is equal to the set voltage value

When Vset (that is, I×R), the first voltage V1 is equal to the second voltage V2, so it can be judged whether the absolute value Vref of the negative reference voltage NVref is equal to the set voltage or not through the comparison result of the first voltage V1 and the second voltage V2. Voltage value Vset. In addition, by adjusting the resistance value R of the resistor R1, the set voltage value Vset can be adjusted.

Please refer to FIG. 3 and FIG. 5A together. It is worth mentioning here that since the negative reference voltage NVref is coupled to the control terminal of the P-type transistor M1 (that is, the gate terminal of the P-type MOSFET), there is no current flowing from the capacitor CL in FIG. 3 Flow to the P-type transistor M1 of FIG. 5A. In other words, the negative voltage detector of the embodiment of FIG. 5A does not draw current from the capacitor CL of FIG. 3 . Therefore, after the absolute voltage value Vref of the negative reference voltage NVref is equal to the set voltage value Vset, the absolute voltage value Vref of the negative reference voltage NVref can still be maintained at the set voltage value Vset even if the negative pump circuit 144 in FIG. .

It is also worth mentioning that in FIG. 5A, the voltage at the second terminal of the P-type transistor M1 (which is -Vref+Vsg) must be greater than the voltage at the first terminal of the P-type transistor M1 (which is the ground voltage GND), resulting in a negative reference The voltage absolute value Vref of the voltage NVref must be smaller than the voltage difference Vsg. Therefore, in other embodiments of the present invention, the threshold voltage (threshold voltage) of the P-type transistors M1 and M2 can be increased by increasing the body effect of the P-type transistors M1 and M2, thereby increasing the voltage difference Vsg and the negative voltage. The upper limit of the voltage absolute value Vref of the reference voltage NVref.

5B is a schematic circuit diagram of a first circuit and a second circuit of a negative voltage detector according to another embodiment of the present invention. Please refer to FIG. 5A and FIG. 5B together. The first circuit 521B of FIG. 5B is similar to the first circuit 521A of FIG. 5A, the difference between the two is only that the base of the P-type transistor M1 of the first circuit 521B is a coupling resistor R1 The second terminal of the first circuit 521B increases the threshold voltage of the P-type transistor M1 by increasing the body effect of the P-type transistor M1, thereby increasing the upper limit of the absolute value of the negative reference voltage NVref. In addition, the second circuit 522B in FIG. 5B is similar to the second circuit 522A in FIG. 5A , the only difference is that the second circuit 522B further includes a resistor R2.

In detail, as shown in FIG. 5B, the first end of the resistor R2 is coupled to the second end of the P-type transistor M2, and the second end of the resistor R2 is coupled to the current source I2, wherein the base of the P-type transistor M2 is coupled to Connect to the second end of the resistor R2 to increase the body effect of the P-type transistor M2. By increasing the body effect of the P-type transistor M2 of the second circuit 522B, the threshold voltage of the P-type transistor M2 of the second circuit 522B can be increased correspondingly, so that the characteristics of the P-type transistor M2 of the second circuit 522B are different from those of the first circuit 521B. The characteristics of the P-type transistor M1 are matched.

Please refer to FIG. 5A again, the voltage difference between the second terminal and the first terminal of the P-type transistor M1 is -Vref+Vsg, and the voltage difference between the second terminal and the first terminal of the P-type transistor M2 is Vsg. Since the voltage difference between the second terminal and the first terminal of the P-type transistor M1 is not equal to the voltage difference between the second terminal and the first terminal of the P-type transistor M2, the characteristics of the P-type transistors M1 and M2 do not match.

5C is a schematic circuit diagram of the first circuit and the second circuit of the negative voltage detector according to another embodiment of the present invention. Please refer to FIG. 5A and FIG. 5C together. The first circuit 521C in FIG. 5C is similar to the first circuit 521A in FIG. 5A . In addition, the second circuit 522C in FIG. 5C is similar to the second circuit 522A in FIG. 5A , the only difference is that the second circuit 522C further includes a resistor R3.

In detail, as shown in FIG. 5C , the first end of the resistor R3 is coupled to the ground voltage GND. The second end of the resistor R3 is coupled to the first end of the P-type transistor M2. Since the first end of the P-type transistor M2 of the second circuit 522C is coupled to the ground voltage GND through the resistor R3, the voltage of the first end of the P-type transistor M2 of the second circuit 522C is the voltage VR3 across the two ends of the resistor R3 , and the voltage difference between the second terminal and the first terminal of the P-type transistor M2 of the second circuit 522C is Vsg−VR3. In addition, the voltage difference between the second terminal and the first terminal of the P-type transistor M1 of the second circuit 521C is -Vref+Vsg, so by adjusting the resistance value of the resistor R3, the voltage across the voltage VR3 is equal to the negative reference voltage NVref. The value of Vref can make the voltage difference between the second terminal and the first terminal of the P-type transistor M1 equal to the voltage difference between the second terminal and the first terminal of the P-type transistor M2, so that the characteristics of the P-type transistors M1 and M2 match.

Similarly, the design of the resistor R3 in the second circuit 522C of FIG. 5C can also be applied to the second circuit 522B of FIG. 5B , as shown in the second circuit 522D of FIG. 5D . The implementation details and operation of the second circuit 522D can refer to the relevant description above, and will not be repeated here. In addition, the first circuit 521D in FIG. 5D is similar to the first circuit 521B in FIG. 5B , so reference may be made to the relevant description above, and details are not repeated here.

To sum up, the negative voltage generator of the embodiment of the present invention uses the power supply voltage to charge the capacitor to generate and provide a negative reference voltage. The absolute value of the voltage quickly reaches the set voltage value. Besides, the negative voltage detector of the embodiment of the present invention does not draw current from the capacitor. Therefore, after the absolute value of the voltage of the negative reference voltage reaches the set voltage value, the voltage pump circuit in the negative voltage generator can stop pumping to avoid surge current, while the absolute value of the voltage of the negative reference voltage can still be maintained at Set the voltage value.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (15)

1. a kind of negative voltage generator, to provide negative reference voltage, which is characterized in that the negative voltage generator includes:

Negative voltage detector, comprising:

First circuit generates first voltage to receive the negative reference voltage, and according to the negative reference voltage；

Second circuit, to generate second voltage；And

Comparison circuit couples first circuit to receive the first voltage, couples the second circuit to receive described the Two voltages, and the first voltage and the second voltage are compared to generate control signal；And

Voltage pump circuit couples the negative voltage detector to receive the control signal, and generate according to the control signal The negative reference voltage.

2. negative voltage generator according to claim 1:

Wherein first circuit includes:

First P-type transistor, the first end coupling ground voltage of first P-type transistor, and first P-type transistor Control terminal receives the negative reference voltage；

First resistor device, the first end of the first resistor device couple the second end of first P-type transistor；And

First current source, couples the second end of the first resistor device to provide the first voltage,

Wherein the second circuit includes:

Second P-type transistor, the first end and control terminal of second P-type transistor couple the ground voltage, and described the The second end of two P-type transistors provides the second voltage；And

Second current source couples the second end of second P-type transistor.

3. negative voltage generator according to claim 2, wherein the matrix coupling described first of first P-type transistor The second end of resistor, and the second circuit further include:

Second resistor, the first end of the second resistor couple the second end of second P-type transistor, and described The second end of second resistor couples the matrix of second current source and second P-type transistor.

4. negative voltage generator according to claim 3, wherein the second circuit further include:

3rd resistor device, the first end of the 3rd resistor device couple the ground voltage, and the second of the 3rd resistor device End couples the first end of second P-type transistor.

5. negative voltage generator according to claim 2, wherein the second circuit further include:

Second resistor, the first end of the second resistor couple the ground voltage, and the second of the second resistor End couples the first end of second P-type transistor.

6. negative voltage generator according to claim 1, wherein when the first voltage is greater than the second voltage, institute It states comparison circuit and generates the control signal with voltage pump circuit described in enable, cause the voltage pump circuit according to supply voltage To be incremented by the absolute value of voltage of the negative reference voltage.

7. negative voltage generator according to claim 6, wherein when the first voltage is equal to the second voltage, institute It states comparison circuit and generates the control signal with voltage pump circuit described in forbidden energy, cause the voltage pump circuit by the negative reference The absolute value of voltage of voltage maintains setting voltage value, wherein the voltage that the setting voltage value is less than the supply voltage is absolute Value.

8. negative voltage generator according to claim 1, wherein the voltage pump circuit includes:

Clock signal generation circuit, to according to the control signal to generate clock signal group；And

Negative pump circuit couples the clock signal generation circuit to receive the clock signal group, and according to the clock signal Group and supply voltage generate the negative reference voltage, wherein the absolute value of voltage of the negative reference voltage is less than the power supply electricity The absolute value of voltage of pressure.

9. negative voltage generator according to claim 8, wherein the clock signal group is two-phase clock signal, and described Negative pump circuit includes:

First capacitor device；

First switch, the first end of the first switch couple the supply voltage, and the second end coupling of the first switch The first end of the first capacitor device；

Second switch, the first end of the second switch couple ground voltage, and described in the second end coupling of the second switch The second end of first capacitor device；

The first end of third switch, the third switch couples the first end of the first capacitor device, and the third is opened The second end of pass couples the ground voltage；

The first end of 4th switch, the 4th switch couples the second end of the first capacitor device；And

Output capacitor, the first end of the output capacitor couple the ground voltage, and the second of the output capacitor Hold the second end of coupling the 4th switch to provide the negative reference voltage,

Wherein the first switch and the second switch are controlled by a wherein clock signal for the two-phase clock signal, and institute It states third switch and the 4th switch is controlled by wherein another clock signal of the two-phase clock signal.

10. a kind of negative voltage detector, to detect negative reference voltage, which is characterized in that the negative voltage detector includes:

First circuit generates first voltage to receive the negative reference voltage, and according to the negative reference voltage；

Second circuit, to generate second voltage；And

Comparison circuit couples first circuit to receive the first voltage, couples the second circuit to receive described the Two voltages, and the absolute value of voltage first voltage and the second voltage being compared to judge the negative reference voltage Whether setting voltage value is equal to.

11. negative voltage detector according to claim 10:

Wherein first circuit includes:

First P-type transistor, the first end coupling ground voltage of first P-type transistor, and first P-type transistor Control terminal receives the negative reference voltage；

First resistor device, the first end of the first resistor device couple the second end of first P-type transistor；And

First current source, couples the second end of the first resistor device to provide the first voltage,

Wherein the second circuit includes:

Second P-type transistor, the first end and control terminal of second P-type transistor couple the ground voltage, and described the The second end of two P-type transistors provides the second voltage；And

Second current source couples the second end of second P-type transistor.

12. negative voltage detector according to claim 11, wherein the matrix coupling of first P-type transistor described the The second end of one resistor, and the second circuit further include:

Second resistor, the first end of the second resistor couple the second end of second P-type transistor, and described The second end of second resistor couples the matrix of second current source and second P-type transistor.

13. negative voltage detector according to claim 12, wherein the second circuit further include:

3rd resistor device, the first end of the 3rd resistor device couple the ground voltage, and the second of the 3rd resistor device End couples the first end of second P-type transistor.

14. negative voltage detector according to claim 11, wherein the second circuit further include:

Second resistor, the first end of the second resistor couple the ground voltage, and the second of the second resistor End couples the first end of second P-type transistor.

15. negative voltage detector according to claim 10, wherein when the first voltage is greater than the second voltage, The comparison circuit generates the control signal of the first level；When the first voltage is equal to the second voltage, the comparison Circuit generates the control signal of second electrical level, wherein first level is complementary with the second electrical level.