JPH11330376A - Charge pump type driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the withstanding voltage of a capacitor which is used in a charge pump circuit from depending on the voltage of a power source. SOLUTION: In a charge pump type driving circuit, a charge pump circuit CPC is driven by a negative power source using the voltage of a power source VDH as a reference. As a result, the voltage applied across both ends of capacitors C1 to C3 used in the circuit CPC can be decreased. Further, by inserting a switch circuit SW1 between the circuit CPC and an output MOS transistor Mout, the circuit CPC is separated from the transistor Mout. As a result, the voltage applied across both ends of the capacitors C1 to C3 can be made independent of the voltage of the source VDH irrespective of the state of the transistor Mout, whether it is in the ON state or in the OFF state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump type driving circuit, and more particularly to a charge pump type driving circuit having a switching element above a load, which is used for a driving portion of a so-called high side switch. It is.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a conventional charge pump type driving circuit. FIG. 6A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG.
6B is a diagram showing a waveform of the input control signal A, and FIG.
(C) is a diagram showing a waveform of the input pulse signal B.

[0005] As can be seen from FIG. 5, this charge pump type driving circuit includes a charge pump circuit CPC ′ and a switch circuit SW ′. The charge pump circuit CPC 'includes a diode D1 connected in series.
To D4 and an inverter X12 similarly connected in series.
To X3, these diodes D1 to D4 and the inverter X
1 to X3 and capacitors C1 to C3 connected in parallel.
C3. Further, the switch circuit SW 'is a bipolar transistor Q which constitutes a current mirror circuit on the previous stage side of the charge pump circuit CPC'.
1, Q2, a resistor R1 and a MOS transistor M1 connected in series to the bipolar transistor Q1, and a MOS transistor M2 connected to the subsequent stage of the charge pump circuit.

An input control signal A shown in FIG. 6B is applied to the control terminal of the MOS transistor M1, and an input pulse signal B shown in FIG. 6C is applied to the inverter X1. When the input control signal A changes from the low level to the high level, the MOS transistor M1 turns on, and the bipolar transistors Q1 and Q2 turn on. Therefore, charging of the capacitor C1 for the charge pump is started. When the output of the inverter X1 is at a low level, the capacitor C1 is charged from the power supply VDH via the bipolar transistor Q2 and the diode D1, and stores about VDH-VF.

Next, when the output of the inverter X1 changes from the low level to the high level, VDL-VF of the electric charge stored in the capacitor C1 moves to the capacitor C2. For this reason, about VDH + V
The electric charge of DL-VF is stored. By repeating the same operation, about VDH + 2VDL is added to the capacitor C3.
A charge of -2VF is stored. Such an operation is continuously performed in synchronization with the input pulse signal B. Therefore, if the output of the inverter X3 is a node m1 and the node between the diode D3 and the diode D4 is a node m2,
The voltage waveforms at these nodes m1 and m2 are as shown in FIG. As can be seen from FIG. 6A, the power supply VDH is provided by the charge pump circuit CPC '.
A higher voltage is generated.

[0006]

As can be seen from the above description, the conventional charge pump type driving circuit accumulates electric charges with respect to the ground potential and secures a driving power source for the high-side switch. However, the power supply VDH and the switching element M used for the output stage
Since a voltage higher than the withstand voltage of the OS transistor MOUT (voltage-driven element including MOSFET, IGBT, etc.) is applied to the drive circuit including the charge pump circuit, the withstand voltage of the capacitors C1 to C3 is determined by the power supply voltage VDH or the output There is a problem that a device having a breakdown voltage higher than the step element must be used.

That is, since a voltage higher than the power supply voltage VDH is applied to the capacitors C1 to C3, the charge pump capacitors C1 to C3 have the bipolar transistors Q1 and Q
A withstand voltage higher than 2 etc. is required. Generally, in an IC process, a capacitor is formed using an insulator such as an oxide film, and the withstand voltage of the capacitor is determined by the oxide film thickness. Therefore, in order to obtain the withstand voltage of this capacitor, it is necessary to make this oxide film thicker.
When the oxide film is thickened, there is a disadvantage that the capacity per unit area decreases and the chip size increases. Also, when a capacitor is formed using components, there is a problem that a capacitor having a high withstand voltage must be selected.

The present invention has been made in view of the above problems, and has as its object to provide a charge pump drive circuit in which a voltage higher than a power supply is not applied to a capacitor constituting a charge pump. I do.
That is, an object of the present invention is to provide a charge pump drive circuit in which the withstand voltage of a capacitor constituting a charge pump does not depend on a power supply.

[0009]

To solve the above problems, a charge pump type driving circuit according to the present invention generates a first power supply voltage and a second power supply voltage higher than the first power supply voltage. A power supply and a second power supply
A plurality of diodes connected in series to the supply voltage of
A plurality of inverters connected in series, wherein an input pulse signal is input to an inverter in a first stage, and a pulse output of each inverter is the second power supply voltage and the second power supply voltage. A plurality of inverters oscillating between a third power supply voltage dropped by a predetermined voltage from
And a plurality of capacitors respectively connecting in parallel each node between the plurality of inverters.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention is used in a charge pump type driving circuit by driving the charge pump circuit with a negative power supply based on a power supply. The voltage applied to both ends of the capacitor is reduced. Further, by inserting a switch circuit between the charge pump circuit and the output transistor, the charge pump circuit and the output transistor are separated from each other, regardless of whether the output transistor is on or off. Is made independent of the power supply. Hereinafter, a more detailed description will be given based on the drawings.

FIG. 1 is a diagram showing a charge pump type driving circuit according to a first embodiment of the present invention. FIG. 2 (a)
2A and 2B are diagrams showing voltage waveforms at various points of the charge pump type driving circuit shown in FIG. 1, FIG. 2B is a diagram showing a waveform of an input control signal A, and FIG. It is a figure showing a waveform.

As can be seen from the left side of FIG. 1, a power supply VDH is connected between the ground terminal GND and the node n1. As can be seen from the right side of FIG. 1, an n-type MOS transistor MOUT, which is an output element, and a resistor RL are connected in series between the node n1 and the ground GND. This output MOS transistor M
A node n2 is provided between OUT and the node n1. This node n2 and MOS transistor MOUT
Are connected between the limiting resistor R2 and the diodes D1 to D1.
D4 and an n-type MOS transistor M3 are connected in series, and between them form nodes n3 to n7, respectively. A resistor R3 is connected between the control terminal of the MOS transistor M3 and the node n6. A node n8 is formed between the ground GND and the resistor RL. An npn-type bipolar transistor Q3 and an n-type MOS transistor M2 are connected in series between the node n8 and the node n7. ing. The control terminal of the bipolar transistor Q3 is connected to its output terminal, and forms a so-called diode connection. A node n9 between the bipolar transistor Q3 and the MOS transistor M2 and a node n10 between the MOS transistor M3 and the resistor R3 are commonly connected to each other. The input control signal A is input to the control terminal of the MOS transistor M2 via the inverter X4. The above-described MOS transistors M2 and M3 and the inverter X
4, the resistor R3, and the bipolar transistor Q3,
This constitutes the switch circuit SW1 in the present embodiment.

A node n11 is located below the node n1 in the figure.
, A closed loop LP formed by closing the loop is provided. A negative power supply VDL is provided in a closed loop LP below the node n11 in the figure. This negative power supply VDL is a negative power supply based on the voltage of the power supply VDH. Due to the closed loop LP, the inverters X1, X
2, a voltage VDH and a voltage VDH-VDL are supplied to a logic circuit composed of X3. The input pulse signal B is input to the first stage inverter X1 located on the input side of the logic circuit. Inverters X1, X2, X3
Are formed between nodes n12 and n13. The output of the inverter X3 is connected to the node 14. The capacitor C1 is connected between the node n12 and the node n3. The capacitor C2 is connected between the node n13 and the node n4. Inverter X3 output (node n14) and node n
5, a capacitor C3 is connected. That is, the diodes D1 to D4 and the inverters X1 to X3
, Capacitors C1 to C3 are connected in parallel. The diodes D1 to D4, the inverters X1 to X3, and the capacitors C1 to C3 constitute a charge pump circuit CPC in the present embodiment.

Next, the operation of the charge pump type driving circuit will be described.

As can be seen from FIG. 1, the input pulse signal B shown in FIG. 2C is input to the inverter X1.
The input pulse signal B performs an amplitude operation between the voltage VDH (high level) and the voltage VDH-VDL (low level). As can be seen from FIG. 2A, the inverters X1 to X
The output of 3 also performs amplitude operation between VDH and VDH-VDL. This amplitude operation is performed because the inverters X1 to X3 are connected in series.
Are adjacently alternately inverted.

Focusing on the capacitor C1, when the output of the inverter X1 is at VDH-VDL, that is, when the output of the inverter X1 is at a low level, the electric charge of VDL-VF is stored via the limiting resistor R2 and the diode D1. Can be When the output of the inverter X1 changes to VDH, that is, when the output of the inverter X1 changes to a high level, the charge stored in the capacitor C1 is charged to the capacitor C2. Next, the output of the inverter X2 becomes V
DH-VDL, that is, when the output of the inverter X2 changes to a low level, this capacitor C
2 includes the electric charge transferred from the capacitor C1 and 2
The charge of VDL-2VF is stored. Similarly, when the output of the inverter X2 changes to VDH, that is, when the output of the inverter X2 changes to a high level, the charge stored in the capacitor C2 is charged to the capacitor C3. Next, the output of the inverter X3 is VDH-V
When it changes to DL, that is, when the output of the inverter X3 changes to low level, the capacitor C3
3VDL- together with the charge transferred from the capacitor C2
A charge of 3 VF is stored. The above operation is continuously performed, and the nodes n3, n4, n5, n12, n
The voltage at 14 changes as shown in FIG.

Whether or not such a charge pump circuit CPC is driven is controlled by an input control signal A. That is, as shown in FIG. 2B, when the input control signal A goes high, the charge pump drive circuit operates. As can be seen from FIG.
The input control signal A is input to the control terminal of the MOS transistor M2 via the inverter X4. That is, when the input control signal A changes from the low level to the high level, the MOS transistor M2 changes from the on state to the off state. When the MOS transistor M2 is turned off, the MOS transistor M3 diode-connected from the diode D4 by the resistor R3 is turned on. As a result, the output of the diode D4 is input to the control terminal of the MOS transistor MOUT. At this time, the voltage of the node n7 is, as shown in FIG.
The voltage is higher than the voltage of DH. That is, VD
H + 3 (VDL-VF) to forward resistance V of diode D4
The voltage is reduced by the ON resistance of F and the MOS transistor M3. The MOS transistor MOUT is turned on by this voltage, and the output voltage V
out is output. As can be seen from FIG. 2B, when the input control signal A changes from the high level to the low level, M
The OS transistor M2 is turned on from the off state,
Diode-connected bipolar transistor Q3
Is also turned on. Therefore, the node n7 is at the ground level. Therefore, the MOS transistor MOUT is turned off. At the same time, the node n10 also goes to the ground level, so that the MOS transistor M3 is turned off. That is, when the input control signal goes low, the voltage is pulled out from the control terminals of the MOS transistors MOUT and M3, and the diode D4, which is the output of the charge pump circuit, is disconnected from the MOS transistor MOUT. Therefore, although the voltage of the node n7 is at the ground level, the voltage of the node n6 becomes approximately V
It is maintained at DH-4VF. In this case, the voltage of the node n5 is VDH-3VF, the voltage of the node n4 is VDH-2VF, and the voltage of the node n3 is VDH-VF.
VF.

As described above, according to the charge pump type driving circuit according to the present embodiment, the charge pump circuit is controlled based on the voltage of the power supply VDH and the negative voltage VDH−
Since the drive is performed by the VDL, the voltage applied to both ends of the capacitors C1 to C3 used in the charge pump circuit CPC can be reduced. That is, as can be seen from FIG. 2, since the output pulses of the inverters X1 and X2 are made to swing from the voltage VDH to the width of the voltage VDH-VDL, the voltage applied to the capacitors C1 to C3 can be reduced as compared with the related art. it can. Moreover, the voltages applied to these capacitors C1 to C3 are VDL-
Since the voltages are represented by VF, 2VDL-2VF, and 3VDL-3VF, the voltage stored in the capacitors C1 to C3 can be made independent of the power supply VDH.

Further, as can be seen from FIG. 1, when the MOS transistor MOUT is turned off,
Since the control terminal of the S-transistor MOUT is separated from the diode D4 which is the output of the charge pump circuit, the node n6 does not need to be dropped to the ground level. Therefore, a high voltage depending on VDH is applied to the capacitor C3 and the like. It can be prevented from being applied. That is, it is possible to prevent the node n14 from going to VDH and the node n5 from going to the ground level, so that a high voltage is applied to the capacitor C3 and the like.

[Second Embodiment] The second embodiment of the present invention is different from the charge pump drive circuit of the first embodiment described above in that a switch circuit is also provided before the charge pump circuit. This is to reduce the steady-state current flowing when the drive circuit is in an off state, thereby reducing power consumption. Hereinafter, a more detailed description will be given based on the drawings. FIG. 3 is a diagram illustrating a charge pump type driving circuit according to a second embodiment of the present invention. FIG. 4 (a)
FIG. 4 is a diagram showing voltage waveforms at various points in the charge pump type driving circuit shown in FIG. 1, FIG. 4 (b) is a diagram showing a waveform of an input control signal A, and FIG. FIG. 6 is a diagram showing a waveform of B.

As can be seen from FIG. 3, the charge pump type driving circuit according to the second embodiment includes a switch circuit SW1 at the subsequent stage of the charge pump circuit CPC as in the first embodiment.
And a switch circuit SW2 is additionally provided in a stage preceding the charge pump circuit CPC.

The former-stage switch circuit SW2 includes a bipolar transistor Q1, a resistor R1, and a MOS transistor M1, which are connected in series between the power supply VDH and the ground. Bipolar transistor Q2 is connected to bipolar transistor Q1 so that the control terminals are commonly connected. That is,
The bipolar transistors Q1 and Q2 form a current mirror circuit. The output terminal of the bipolar transistor Q2 is connected to the diode D1 of the charge pump circuit. An input control signal A is input to a control terminal of the MOS transistor M1. The input control signal A is also input to the inverter X4 of the subsequent-stage switch circuit SW1. Except for these points, the configuration of the charge pump driving circuit according to the second embodiment is the same as that of the first embodiment.

Next, the operation of the charge pump type driving circuit according to the second embodiment will be described. As can be seen from FIG. 4, the operation of the charge pump type driving circuit according to the second embodiment is the first type. The operation is the same as the operation of the charge pump drive circuit according to the embodiment.

As described above, according to the charge pump drive circuit according to the present embodiment, the switch circuit SW2 is also provided at the preceding stage of the charge pump circuit. Can be prevented from flowing, and power consumption can be suppressed. More specifically, as can be seen from FIG. 1, in the first embodiment, when the charge pump drive circuit is off, the MOS transistor M2 is on. Therefore, a steady current flows from the diode D4, which is the output of the charge pump circuit CPC, to the ground via the resistor R3 and the MOS transistor M2. On the other hand, as can be seen from FIG. 3, also in the second embodiment,
When the charge pump drive circuit is off, the MOS transistor M2 is on. Further, since the MOS transistor M1 is turned off, the bipolar transistor Q2 forming the current mirror is also turned off. That is, the switch circuit SW2 preceding the charge pump circuit CPC is turned off. Therefore, the voltage supply from the power supply VDH to the charge pump circuit CPC is cut off, and it is possible to prevent a steady current from flowing from the diode D4 to the ground via the resistor R3 and the MOS transistor M2. Therefore, power consumption when the charge pump type driving circuit is off can be reduced.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, as can be seen from FIG. 1 and FIG.
The voltage at the control terminal of the UT can be reduced linearly. In this case, if the voltage of the control terminal of the MOS transistor MOUT is reduced, the voltage of the control terminal of the MOS transistor M3 can also be reduced at the same time. That is,
The present invention can also be applied to a case where the voltage at the node n9 is linearly controlled using an operational amplifier or the like.

As can be seen from FIGS. 2 and 4, in the above-described embodiment, the input pulse signal B is supplied continuously regardless of the high level / low level state of the input control signal A. However, the input pulse signal B can be linked with the state of the input control signal A. That is, the input pulse signal B can be supplied only during the period when the input control signal A turns on the charge pump drive circuit, that is, only during the high state. In this way, power consumption can be reduced by the unnecessary input pulse signal B.

[0027]

As described above, according to the present invention,
Since the charge pump circuit is driven by the negative power supply based on the power supply, the voltage applied to both ends of the capacitor used in the charge pump circuit can be reduced, and the withstand voltage of the capacitor does not depend on the power supply. You can do so.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a circuit configuration of a charge pump drive circuit according to a first embodiment of the present invention.

2A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 1, FIG. 2B is a diagram showing an input control signal, and FIG. 2C is a diagram showing an input pulse signal; FIG.

FIG. 3 is a diagram illustrating an example of a circuit configuration of a charge pump drive circuit according to a second embodiment of the present invention.

4A is a diagram showing voltage waveforms at various points in the charge pump type driving circuit shown in FIG. 3, FIG. 4B is a diagram showing an input control signal, and FIG. 4C is a diagram showing an input pulse signal; FIG.

FIG. 5 is a diagram showing an example of a circuit configuration of a conventional charge pump drive circuit.

6A is a diagram showing voltage waveforms at various points in the charge pump drive circuit shown in FIG. 5, FIG. 6B is a diagram showing an input control signal, and FIG. 6C is a diagram showing an input pulse signal; FIG.

[Explanation of symbols]

 SW1 Rear-stage switch circuit SW2 Front-stage switch circuit CPC Charge pump circuit X1 to X4 Inverter D1 to D4 Diode M1 to M3 MOS transistor MOUT Output MOS transistor Q1 to Q3 Bipolar transistor

Claims (5)

[Claims] A power supply for generating a first power supply voltage and a second power supply voltage higher than the first power supply voltage; and a power supply connected in series to a second power supply voltage of the power supply. A plurality of diodes, and a plurality of inverters connected in series, wherein an input pulse signal is input to an inverter in a first stage, and a pulse output of each inverter is the second power supply voltage, A plurality of inverters swinging between a third power supply voltage obtained by dropping the second power supply voltage by a certain voltage, a plurality of nodes between the plurality of diodes, and a plurality of nodes between the plurality of inverters; And a plurality of capacitors respectively connected in parallel with each other. 2. An output of a last-stage diode among the plurality of diodes is connected to a control terminal of an output transistor, and an output of the last-stage diode is connected to a control terminal of the output transistor. The switch circuit according to claim 1, further comprising a second-stage switch circuit for disconnecting the last-stage diode from the output transistor only when the output transistor is off. Charge-pump driving circuit. 3. The last-stage switch circuit includes: an input terminal connected to the last-stage diode; an output terminal connected to a control terminal of the output transistor; A first transistor having a control terminal connected to the diode of the stage; an input terminal connected to the control terminal of the first transistor; an output terminal connected to a first power supply voltage of the power supply; A second transistor having a control terminal to which an input control signal for switching between an on state and an off state of the output transistor is input; and an input terminal and a control terminal connected to a control terminal of the output transistor. A third transistor having an output terminal connected to the input terminal of the second transistor, and a third transistor. Large pump drive circuit. 4. When the output transistor is in an off state between an input of a diode of a first stage among the plurality of diodes and a second power supply voltage of the power supply, the output of the first stage is controlled. The second of the diode and the power supply
4. The charge pump type driving circuit according to claim 2, further comprising: a front-stage switch circuit for disconnecting the power supply voltage from the power supply voltage. 4. 5. The front-stage switch circuit includes a fourth transistor having an input terminal connected to a second power supply voltage of the power supply, and one end connected to an output terminal and a control terminal of the fourth transistor. A second resistor; an input terminal connected to the other end of the second resistor; an output terminal connected to a first power supply voltage of the power supply; and an on state and an off state of the output transistor. A fifth transistor having an input terminal for inputting an input control signal for switching between the first and second transistors, an input terminal connected to a second power supply voltage of the power supply, and a control terminal of the fourth transistor. 6. A sixth transistor, comprising: a control terminal, and a sixth transistor having an output terminal connected to a first-stage diode of the plurality of diodes. A charge pump type drive circuit.