JP2001028447A - Insulation gate type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent mobile ions from entering from outside and a gate insulation film from being broken by forming a silicon nitride film contacting an insulation substrate, a semiconductor layer involving channel forming regions, source regions and drain regions thereon and a silicon nitride film thereon. SOLUTION: On a substrate 101 a silicon nitride film 102 is formed to prevent mobile ions from entering from the substrate, a silicon oxide base film 103 is formed and patterned to form island-like semiconductor regions 104, 105, a gate oxide film 106 and a silicon nitride film 107 are deposited, an Al film is formed and patterned to form gate electrode wirings 108-111, a current is applied to form Al oxide films 112-115, and an n-type impurity and a p-type impurity are doped in the semiconductor regions 104, 105, respectively, to form n-type impurity regions 116 and p-type impurity regions 117.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating gate type semiconductor device, and more particularly to a structure of a thin film insulating gate type field effect transistor (TFT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a thin film insulated gate field effect transistor (TFT) has been actively studied. For example,
Japanese Patent Application Nos. Hei 4-30220 and Hei 4-30220, which are inventions of the present inventors.
No. 38637 uses aluminum, titanium, chromium, tantalum, or silicon as a gate electrode and covers the periphery thereof with aluminum oxide formed by anodization, thereby eliminating the overlap between the source / drain and the gate electrode, and rather offsetting it. A manufacturing method and a TFT in which a source / drain region is recrystallized by laser annealing in a state are described.

[0003] Such a TFT has better characteristics than a conventional silicon gate TFT having no offset or a TFT having a high melting point metal such as tantalum or chromium as a gate electrode and activated by thermal annealing. . However, it has been difficult to obtain the characteristics with good reproducibility.

[0004] One of the causes was due to intrusion of mobile ions such as sodium from the outside. In particular, during the formation of a gate electrode made of a metal material such as aluminum (a sputtering method or an electron beam evaporation method is used) and the subsequent anodic oxidation, there is a risk that sodium may enter from the outside. In particular, in the sputtering method, sodium contamination was large. However, since the sputtering method is more excellent in mass productivity than the electron beam evaporation method, it has been desired to use the sputtering method for cost reduction.

[0005] It has been known that sodium is blocked and gettered by phosphorus glass or the like. Therefore, the gate insulating film is generally formed of phosphorus glass. However,
It has been difficult to produce phosphorus glass at the low temperature intended for the above patent. If phosphorus glass is to be produced at such a low temperature, many defects are generated in the gate insulating film when the gate insulating film is implanted into a silicon oxide gate insulating film by, for example, an ion doping method. There were times when it was done.

Further, anodic oxidation requires a high voltage of 100 to 300 V, and there is a concern that the gate insulating film may be destroyed.
That is, in the technical range shown in the above patent, a gate insulating film is formed on a semiconductor film, and a gate electrode is present thereon, but at the time of anodic oxidation, the gate electrode is in a floating state with a positively charged gate electrode. A voltage is generated between the semiconductor films,
As the anodic oxide film on the gate electrode becomes thicker and the resistance between the gate electrode and the electrolytic solution increases, the current flowing from the gate electrode to the electrolytic solution via the gate insulating film and the semiconductor film increases. Then, the gate electrode may be destroyed by this current.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances. That is, an object of the present invention is to prevent the invasion of mobile ions from the outside and prevent the gate insulating film from being broken, thereby improving reliability.

[0008]

According to the present invention, at least a semiconductor layer, an insulating film layer and any one of aluminum, chromium, titanium, tantalum, silicon, an alloy thereof, or an alloy thereof are provided on an insulating substrate. A multi-layered gate electrode, and the insulating film layer is composed of an aluminum oxide single layer, a silicon oxide single layer, a silicon nitride single layer, an aluminum nitride single layer, an aluminum oxide layer and a silicon nitride layer.
It is composed of two layers, an aluminum oxide layer and a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, or an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer. For example, a silicon nitride film is interposed between an aluminum gate electrode and a gate insulating film. The composition of silicon nitride is
In this case, the ratio of nitrogen is preferably from 1 to 4/3, more preferably from 1.2 to 4/3. Of course, hydrogen or oxygen other than nitrogen and silicon may be added.

Since the silicon nitride film has an effect of blocking mobile ions such as sodium, it not only has an effect of preventing mobile ions from entering the channel region from the gate electrode and the like, but also has an effect of preventing a normal gate insulating film. Also, it has a feature that since the conductivity is better than that of silicon oxide, an excessive voltage is not applied between the gate electrode and the semiconductor region (channel region) therebelow, so that the gate insulating film can be prevented from being broken. .

Therefore, a semiconductor region and a gate insulating film are formed, thereafter, the silicon nitride film is formed, and thereafter, an aluminum electrode for forming a gate electrode is formed. During the anodization of the aluminum electrode, it is desirable that the silicon nitride film be present integrally over the entire surface of the substrate, since the anodic potential is kept substantially constant over the entire surface of the substrate. Further, in the method for manufacturing an insulated gate semiconductor device according to the present invention, a step of forming a semiconductor region on an insulating substrate, and a step of forming an aluminum oxide single layer, a silicon oxide single layer, a silicon nitride single layer, an aluminum nitride Single layer, two layers of aluminum oxide layer and silicon nitride layer, two layers of aluminum oxide layer and silicon oxide layer, two layers of silicon nitride layer and silicon oxide layer, or three layers of aluminum oxide layer, silicon oxide layer and silicon nitride layer Forming an insulating film layer comprising a layer,
Forming a metal film mainly composed of aluminum, chromium, titanium, tantalum, silicon, or an alloy thereof or a multilayer thereof on the insulating film layer; Forming an oxide layer on the surface thereof. In the insulating gate type semiconductor device and the method of manufacturing the same according to the present invention, when the gate electrode (the metal film) is made of an alloy of silicon and aluminum, the gate electrode (the metal film) contains 0.5 to 3% of silicon. It consists of an added aluminum layer. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0011]

[Embodiment 1] FIG. 1 is a sectional view showing a manufacturing process of this embodiment. The detailed conditions of this embodiment are described in Japanese Patent Application No. Hei 4-30220 or 4-3, filed by the present inventors.
Since it is almost the same as 8637, it will not be described in detail. First, N-0 manufactured by NEC Corporation was used as the substrate 101.
Glass was used. Although this glass has a high strain temperature, it is rich in lithium and also contains significant amounts of sodium. Therefore, in order to prevent invasion of these mobile ions from the substrate, the silicon nitride film 102 is formed with a thickness of 10 to 50 nm by a plasma CVD method or a low pressure CVD method. Further, an underlying silicon oxide film 103 was formed by a sputtering method to a thickness of 100 to 800 nm. An amorphous silicon film is coated on the plasma CV
It was formed to a thickness of 20 to 100 nm by Method D, and was annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere for crystallization. Further, this is patterned by photolithography and reactive ion etching (RIE) to form an island-shaped semiconductor region 104 as shown in FIG.
(For N-channel TFT) and 105 (for P-channel TFT)
And).

Further, the gate oxide film 106 is formed by a sputtering method in an oxygen atmosphere targeting silicon oxide.
Was deposited with a thickness of 50-200 nm. Further, a silicon nitride film 107 was deposited to a thickness of 2 to 20 nm, preferably 8 to 11 nm by a plasma CVD method or a low pressure CVD method.

Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes and wirings 108 to 111. Thus, the outer shape of the TFT was adjusted.

Further, a gate electrode / wiring 1 in an electrolytic solution is provided.
A current was passed through 08 to 111, and aluminum oxide films 112 to 115 were formed by anodic oxidation. The conditions for the anodic oxidation are as described in Japanese Patent Application No.
The method described at 220 was employed. The state so far is shown in FIG.

Next, an N-type impurity is implanted into the semiconductor region 104 and a P-type impurity is implanted into the semiconductor region 105 by a known ion implantation method, and the N-type impurity region (source and drain) 116 and the P-type impurity are implanted. An impurity region 117 was formed. This process used a known CMOS technology. Further, silicon nitride 107 other than that existing under the gate electrode / wiring portion was removed by a reactive ion etching method. This step can be replaced by wet etching. At this time, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in etching rate between aluminum oxide and silicon nitride, which are anodized films.

In this way, a structure as shown in FIG. 1D was obtained. Note that, of course, the crystallinity of the portion into which the impurities are implanted by the previous ion implantation is significantly deteriorated, and is substantially in an amorphous state (an amorphous state,
Or a polycrystalline state close to it). Therefore, the crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for laser annealing are described, for example, in Japanese Patent Application No. Hei.
No. 0220 was used. After laser annealing, a hydrogen atmosphere at 250 to 450 ° C. (1 to 700 t)
orr, preferably 500-700 torr) and 30
Annealing was performed for minutes to 3 hours, and hydrogen was added to the semiconductor region to reduce lattice defects (such as dangling bonds).

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 118 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, the second
Metal film (aluminum or chromium) was selectively formed, and this was used as electrodes / wirings 119 to 121. Here, the second metal wires 119 and 121 cross over the first metal wires 108 and 111. As described above, NT
FT122 and PTFT123 were formed.

[Embodiment 2] FIG. 2 is a sectional view showing a manufacturing process of this embodiment. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 filed by the present inventors, and will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 201, and a silicon nitride film 202 having a thickness of 10 to 50 nm was formed by a plasma CVD method or a low pressure CVD method. Further, an underlying silicon oxide film 203 was formed with a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to crystallize. This is further patterned to form an island-shaped semiconductor region 204 as shown in FIG.
(For N-channel TFT) and 205 (for P-channel TFT)
And).

Further, a gate oxide film 206 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, the silicon nitride film 207 is formed with a thickness of 2 to 20 nm, preferably 8 to 20 nm by a plasma CVD method or a low pressure CVD method.
Only 11 nm was deposited.

Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned to form gate electrodes / wirings 208 to 211. Thus, the outer shape of the TFT was adjusted as shown in FIG.

Further, in the electrolytic solution, the gate electrode / wiring 2
A current was passed through 08 to 211 to form aluminum oxide films 212 to 215 by anodization. The conditions of the anodic oxidation are as follows:
The method described at 220 was employed. The state up to this point is shown in FIG.

Next, as shown in FIG. 2C, silicon nitride 207 and silicon oxide 206 other than those existing under the gate electrode / wiring portion are formed by reactive ion etching.
Was removed, and the semiconductor regions 204 and 205 were exposed. This step can be replaced by wet etching. At this time, the etching can be performed in a self-aligned manner using aluminum oxide as a mask by utilizing the difference in the etching rate between aluminum oxide, which is an anodic oxide film, silicon nitride, and silicon oxide. Further, the semiconductor region 204 is doped with an N-type impurity and the semiconductor region 205 is doped with a P-type impurity by a laser doping technique (Japanese Patent Application No. 3-283981), which is an invention of the present inventors. Region (source, drain) 216 and P-type impurity region 217
Was formed. This process used CMOS technology as described in Japanese Patent Application No. 3-283981.

In this way, a structure as shown in FIG. 2D was obtained. In the laser doping method, the implantation of impurities and the annealing are performed at the same time, so that the steps of laser annealing and thermal annealing as in the first embodiment are unnecessary. After laser doping, 250 ~
Annealing was performed in a hydrogen atmosphere at 450 ° C. (1 to 700 torr, preferably 500 to 700 torr) for 30 minutes to 3 hours, and hydrogen was added to the semiconductor region to reduce lattice defects (dangling bonds and the like).

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 218 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed. Finally, the second
Metal film (aluminum or chromium) was selectively formed to form electrodes / wirings 219 to 221. As described above, NTFT 222 and PTFT 223 were formed.

[Embodiment 3] FIG. 3 is a sectional view showing a manufacturing process of this embodiment. The detailed conditions of the present embodiment are almost the same as those of Japanese Patent Application No. Hei 4-30220 filed by the present inventors, and will not be described in detail. First, N-0 glass manufactured by NEC Corporation was used as the substrate 301, and a silicon nitride film 302 was formed to a thickness of 10 to 50 nm by a plasma CVD method or a low pressure CVD method. Further, a silicon oxide film 303 as a base was formed to a thickness of 100 to 800 nm by a sputtering method. An amorphous silicon film was formed thereon by plasma CVD to a thickness of 20 to 100 nm, and annealed at 600 ° C. for 12 to 72 hours in a nitrogen atmosphere to crystallize. Further, this is patterned to form an island-shaped semiconductor region 304 as shown in FIG.
(For N-channel TFT) and 305 (for P-channel TFT)
And).

Further, a gate oxide film 306 having a thickness of 50 to 200 nm was deposited by a sputtering method. Further, the silicon nitride film 307 is formed by a plasma CVD method or a low pressure CVD method to a thickness of 2 to 20 nm, preferably 8 to 20 nm.
Only 11 nm was deposited.

Next, an aluminum film was formed by a sputtering method or an electron beam evaporation method, and this was patterned to form gate electrodes and wirings 308 to 311. Thus, the outer shape of the TFT was adjusted as shown in FIG.

Further, in the electrolytic solution, the gate electrode / wiring 3
A current was passed through 08 to 311 to form aluminum oxide films 312 to 315 by anodization. The conditions for the anodic oxidation are as described in Japanese Patent Application No.
The method described at 220 was employed. The state up to this point is shown in FIG.

Next, an N-type impurity is implanted into the semiconductor region 304 and a P-type impurity is implanted into the semiconductor region 305 by a known plasma ion doping method. Type impurity region 317
Was formed. This process used a known CMOS technology. In addition to the impurity elements, hydrogen used as a diluent for the gas source was also ionized from the plasma and injected into the semiconductor region. Although this step can be performed by a known ion implantation method, it is required to separately implant hydrogen ions for the reason described later.

Thus, a structure as shown in FIG. 3D was obtained. Note that, of course, the crystallinity of the portion into which the impurities are implanted by the previous ion implantation is significantly deteriorated, and is substantially in an amorphous state (an amorphous state,
Or a polycrystalline state close to it). Therefore, the crystallinity was recovered by laser annealing. This step may be performed by thermal annealing at 600 to 850 ° C. The conditions for laser annealing are described, for example, in Japanese Patent Application No. Hei.
No. 0220 was used. However, since the silicon nitride film 307 does not transmit short-wavelength ultraviolet light having a wavelength of 250 nm or less, a XeCl laser (308 nm) or a XeF laser (351 nm) was used.

After laser annealing, 250-450 ° C.
Hydrogen atmosphere (1-700 torr, preferably 50
Annealing is performed at 0 to 700 torr) for 30 minutes to 3 hours, and lattice defects (dangling bonds, etc.) in the semiconductor are performed.
Was reduced. Actually, since the silicon nitride film 307 exists, there is almost no exchange of hydrogen inside and outside the semiconductor region. Therefore, for example, in the plasma doping method, a large amount of hydrogen atoms are implanted into the semiconductor region, but in the ion implantation method, a separate hydrogen ion implantation step is required. In the plasma doping method, if the amount of hydrogen is insufficient, hydrogen must be separately doped.

Thus, the shape of the element was adjusted. Thereafter, as usual, an interlayer insulator 318 is formed by sputter deposition of silicon oxide, an electrode hole is formed by a known photolithography technique, and the surface of the semiconductor region or the gate electrode / wiring is exposed, Finally, the second
Metal film (aluminum or chromium) was selectively formed to form electrodes / wirings 319 to 321. As described above, NTFT 322 and PTFT 323 were formed.

[Embodiment 4] "The thin-film insulated gate semiconductor device and its manufacturing method", filed by the present inventors and filed on February 25, 1992 (Applicant, Semiconductor Energy Laboratory Co., Ltd. Reference numbers P002042-01 to P0
FIG. 2 shows an example in which the present invention is applied to a TFT having two layers of channels described in 02044-03 (the above three cases).

That is, in FIG. 4, FIG. 5, and FIG.
01, 501, 601 are N-channel TFTs, 402, 4
Reference numerals 02 and 402 denote P-channel TFTs. In each figure, first layers 408, 410, 508,
Each of 510, 508, and 510 is substantially made of amorphous silicon. Its thickness is 20 ~ 200n
m.

407, 409, 507, 509,
Reference numerals 607 and 609 denote substantially polycrystalline or semi-amorphous silicon, and the thickness thereof is 20 to 200 nm. Further, 404, 406, 504, 506, 60
4, 606 are gate insulating films made of silicon oxide;
The thickness is 50-300 nm. And 403, 40
5, 503, 505, 603, and 605 are silicon nitride films having a thickness of 2 to 20 nm formed in the same manner as in Examples 1 to 3. These structures were manufactured based on the description of the above patent application or Example 1.

[0036]

As described above, by forming a silicon nitride film, a silicon oxide film, an aluminum oxide film, an aluminum nitride film, or a multilayer film thereof between the gate electrode and the semiconductor layer (channel region), It was possible to prevent the intrusion of ions and to prevent the gate insulating film from being broken at the time of anodic oxidation of the gate electrode.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
Is shown.

FIG. 2 is a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
Is shown.

FIG. 3 is a manufacturing process diagram (cross section) of a semiconductor device according to the present invention.
Is shown.

FIG. 4 shows a structural example of a semiconductor device according to a conventional example.

FIG. 5 shows a structural example of a semiconductor device according to a conventional example.

FIG. 6 shows a structural example of a semiconductor device according to a conventional example.

[Explanation of symbols]

Reference Signs List 101 Insulating substrate 102 Blocking layer (silicon nitride) 103 Blocking layer (silicon oxide) 104 Semiconductor region (N-channel TFT
105 semiconductor region (P-channel TFT)
106) Gate insulating film 107 Silicon nitride film 108-111 Gate electrode / wiring (aluminum) 112-115 Anodic oxide layer 116 N-type impurity region 117 P-type impurity region 118 Interlayer insulator 119-121 Second layer metal wiring 122 NTFT 123 PTFT

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[Procedure amendment]

[Submission date] July 25, 2000 (2007.2
5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

2. The method according to claim 1, wherein said insulating surface is in contact with said insulating surface.
A silicon nitride film having a thickness of 10 to 50 nm.

3. The semiconductor layer according to claim 1 , wherein:
An insulating gate type semiconductor device, wherein the thickness of the silicon nitride film above is 2 to 20 nm.

4. A any one of claims 1 to 3,
The silicon nitride film in contact with the insulating surface has a silicon composition ratio of 1
And insulated gate semiconductor device having a composition ratio of nitrogen is characterized by a 1-3 / 4 der Turkey when the.

5. A any one of claims 1 to 4,
The silicon nitride film above the semiconductor layer contains hydrogen and oxygen.
Over there the insulated gate semiconductor device according to claim.

6. A any one of claims 1 to 5,
Said upper silicon nitride film of absolute semiconductor layer, an insulating gate semiconductor device having a composition ratio of nitrogen is characterized by a 1-3 / 4 der Turkey when the composition ratio of silicon and 1.

A substrate having a 7. insulating surface, a nitride Ka珪Motomaku to contact the insulating surface, a semiconductor layer including the upper switch Yaneru forming region of the silicon nitride film, a source region and a drain region, a gate electrode When, and a nitrogen Ka珪Motomaku between the gate electrode and the semiconductor layer
An insulated gate semiconductor device, comprising:

8. The method according to claim 7 , wherein said insulating surface is in contact with said insulating surface.
A silicon nitride film having a thickness of 10 to 50 nm.

9. The method of claim 7 or 8, wherein the semiconductor layer
A silicon nitride film between the gate electrode and the gate electrode has a thickness of 2 to 20 nm.

10. A any one of claims 7 to 9, wherein the semiconductor layer and the gate electrode silicon nitride film, an insulating gate semiconductor device comprising a-law containing hydrogen and oxygen.

11. The any one of claims 7 to 10, said silicon nitride film in contact with the insulating surface, the composition ratio of nitrogen in the case where the composition ratio of silicon and 1 is 1-3 / 4 An insulated gate semiconductor device.

12. The any one of claims Koko 7 to 11, the silicon nitride film between the absolute semiconductor layer and the gate electrode
The composition ratio of nitrogen is 1 when the composition ratio of silicon and 1
An insulated gate semiconductor device characterized by being 3/4.

A substrate having a 13. insulating surface, a nitride silicofluoride Motomaku in contact with the insulating surface, above the channel formation region of the silicon nitride film in contact with the insulating surface, a semiconductor layer including a source region and a drain region, wherein be between the insulating sheet surface and the semiconductor layer, and the oxide silicofluoride Motomaku in contact with the channel forming region, a gate electrode, a between the gate electrode and the semiconductor layer, oxide silicofluoride-containing contacting before SL channel forming region and film, and a nitride silicofluoride Motomaku between the gate electrode and the semiconductor layer
An insulated gate semiconductor device, comprising:

A substrate having a 14. insulating surface, a nitride silicofluoride Motomaku in contact with the insulating surface, above the channel formation region of the silicon nitride film in contact with the insulating surface, a semiconductor layer including a source region and a drain region, wherein be between the semiconductor layer and the insulating surface, an oxide silicofluoride Motomaku in contact with the channel forming region, a gate electrode, a between the gate electrode and the semiconductor layer, oxide silicofluoride Motomaku in contact with the front SL channel forming region When, a nitride silicofluoride Motomaku between the gate electrode and the semiconductor layer
A silicon nitride film in contact with the insulating surface, the semiconductor layer and the gate
An insulating gate type semiconductor device characterized by being thicker than a silicon nitride film between gate electrodes .

A substrate having a 15. insulating surface, a nitride silicofluoride Motomaku in contact with the insulating surface, above the channel formation region of the silicon nitride film in contact with the insulating surface, a semiconductor layer including a source region and a drain region, wherein be between the semiconductor layer and the insulating surface, a silicon oxide film in contact with the channel forming region, and the gate electrode, be between the semiconductor layer and the gate electrode, the oxide silicofluoride Motomaku in contact with the front SL channel forming region , and a nitride silicofluoride Motomaku between the gate electrode and the semiconductor layer
A silicon oxide film between the semiconductor layer and the gate electrode, the semi
An insulated gate semiconductor device characterized by being thicker than a silicon nitride film between a conductor layer and a gate electrode .

A substrate having a 16. insulating surface, a nitride silicofluoride Motomaku in contact with the insulating surface, above the channel formation region of the silicon nitride film in contact with the insulating surface, a semiconductor layer including a source region and a drain region, wherein be between the semiconductor layer and the nitride silicofluoride Motomaku in contact with the insulating surface, an oxide silicofluoride Motomaku in contact with the channel forming region, and the upper gate electrode of the semiconductor layer, oxidation between the semiconductor layer and the gate electrode and silicofluoride Motomaku, and a nitride silicofluoride Motomaku between the gate electrode and the semiconductor layer
An insulated gate semiconductor device, comprising:

17. The method of claim 15 or 16, wherein the channel forming region is insulated gate semiconductor device characterized by comprising a crystalline silicon.

18. Any one of claims 13 to 17, the silicon nitride film between the gate electrode and the semiconductor layer
Is an insulated gate semiconductor device which is in contact with said gate electrode.

19. any one of claims 13 to 18, the thickness of the silicon nitride film in contact with the insulating surface 10
An insulating gate type semiconductor device having a thickness of 50 nm.

20. A any one of claims 13 to 19, insulated gate semiconductor device wherein the thickness of the silicon oxide film between the insulating surface and the semiconductor layer is 100 to 800 nm.

21. Any one of claims 13 to 20, insulated gate semiconductor device wherein the thickness of the silicon oxide film between the semiconductor layer and the gate electrode is 50 to 200 nm.

22. A any one of claims 13 to 21, insulated gate semiconductor device wherein the thickness of the silicon nitride film between the semiconductor layer and the gate electrode is 2 to 20 nm.

23. In any one of claims 13 to 22, the silicon nitride film in contact with the insulating surface insulated gate semiconductor device comprising a call containing hydrogen and oxygen.

24. A any one of claims 13 to 23, the silicon nitride film between the first semiconductor layer and the gate electrode is insulated gate semiconductor device comprising a call containing hydrogen and oxygen.

25. Any one of claims 13 to 24, wherein the silicon nitride film in contact with the insulating surface, the composition ratio of nitrogen in the case where the composition ratio of silicon and 1 to 3/4 der Turkey <br/> An insulated gate semiconductor device.

26. A any one of claims 13 to 25, the silicon nitride film between said semiconductor layer and the gate electrode,
When the composition ratio of silicon is 1, the composition ratio of nitrogen is 1 to 3 /
4 der Turkey and insulated gate semiconductor device according to claim.

27. Any one of claims 13 to 26, wherein the gate electrode is aluminum, chromium, titanium, tantalum, including any of the elements of silicon
Insulating characterized and this gate semiconductor device.

Claims (22)

[Claims] 1. An insulated gate field effect semiconductor device provided on a substrate having an insulating surface, comprising: a first insulating film made of silicon nitride provided in contact with the insulating surface; An insulated gate semiconductor device, comprising: a semiconductor layer including a channel formation region, a source region, and a drain region provided above; and a second insulating film made of silicon nitride that covers the semiconductor layer. . 2. A substrate having an insulating surface; a first insulating film made of silicon nitride provided in contact with the insulating surface; a channel forming region and a source region provided above the first insulating film And a semiconductor layer including a drain region, a gate electrode, and an insulating film layer provided between the semiconductor layer and the gate electrode. The insulating film layer includes a second insulating film made of silicon nitride. An insulated gate semiconductor device characterized by including: 3. The insulated gate semiconductor device according to claim 1, wherein the first insulating film has a thickness of 10 to 50 nm. 4. The method according to claim 1, wherein
The insulating gate type semiconductor device, wherein the thickness of the second insulating film is 2 to 20 nm. 5. The method according to claim 1, wherein:
The insulating gate type semiconductor device, wherein the second insulating film is made of silicon nitride containing hydrogen and oxygen. 6. The method according to claim 1, wherein
The insulating gate type semiconductor device according to claim 1, wherein the first insulating film is made of silicon nitride and the composition ratio of nitrogen is 1 to 3/4 when the composition ratio of silicon is 1. 7. The method according to claim 1, wherein
The insulating gate type semiconductor device according to claim 2, wherein the second insulating film is made of silicon nitride and the composition ratio of nitrogen is 1/3/4 when the composition ratio of silicon is 1. 8. A semiconductor, comprising: a first insulating film made of silicon nitride provided in contact with an insulating surface of a substrate; and a channel forming region, a source region, and a drain region provided above the first insulating film. A second insulating film made of silicon oxide which is provided between the first insulating film and the semiconductor layer and is in contact with the channel formation region; a gate electrode; and an insulating film provided between the semiconductor layer and the gate electrode. An insulating gate, comprising: a third insulating film made of silicon oxide in contact with the channel formation region; and a fourth insulating film made of silicon nitride. Type semiconductor device. 9. A semiconductor including: a first insulating film made of silicon nitride provided in contact with an insulating surface of a substrate; and a channel forming region, a source region, and a drain region provided above the first insulating film. A second insulating film made of silicon oxide which is provided between the first insulating film and the semiconductor layer and is in contact with the channel formation region; a gate electrode; and an insulating film provided between the semiconductor layer and the gate electrode. A second insulating film comprising: a third insulating film made of silicon oxide in contact with the channel formation region; and a fourth insulating film made of silicon nitride. Is an insulating gate type semiconductor device characterized by being thicker than the first insulating film. 10. A semiconductor comprising: a first insulating film made of silicon nitride provided in contact with an insulating surface of a substrate; and a channel forming region, a source region, and a drain region provided above the first insulating film. A second insulating film made of silicon oxide which is provided between the first insulating film and the semiconductor layer and is in contact with the channel formation region; a gate electrode; and an insulating film provided between the semiconductor layer and the gate electrode. Wherein the insulating film layer includes a third insulating film made of silicon oxide and a fourth insulating film made of silicon nitride, the third insulating film being in contact with the channel formation region. Is an insulating gate type semiconductor device characterized by being thicker than the fourth insulating film. 11. A semiconductor comprising: a first insulating film made of silicon nitride provided in contact with an insulating surface of a substrate; and a channel forming region, a source region, and a drain region provided above the first insulating film. A second insulating film made of silicon oxide, which is provided between the first insulating film and the semiconductor layer and is in contact with the channel formation region; a gate electrode provided above the semiconductor layer; An insulating film layer provided between the gate electrodes, wherein the insulating film layer includes a third insulating film made of silicon oxide in contact with the channel formation region, and a fourth insulating film made of silicon nitride. An insulated gate semiconductor device comprising: 12. The insulated gate semiconductor device according to claim 10, wherein the channel formation region is made of crystalline silicon. 13. The insulated gate semiconductor device according to claim 8, wherein the insulating film layer is in contact with the gate electrode in a fourth insulating film. 14. The insulated gate semiconductor device according to claim 8, wherein the first insulating film has a thickness of 10 to 50 nm. 15. The insulated gate semiconductor device according to claim 8, wherein the second insulating film has a thickness of 100 to 800 nm. 16. The insulated gate semiconductor device according to claim 8, wherein the third insulating film has a thickness of 50 to 200 nm. 17. The insulated gate semiconductor device according to claim 8, wherein the thickness of the fourth insulating film is 2 to 20 nm. 18. The insulated gate semiconductor device according to claim 8, wherein the first insulating film is made of silicon nitride containing hydrogen and oxygen. 19. The insulated gate semiconductor device according to claim 8, wherein the fourth insulating film is made of silicon nitride containing hydrogen and oxygen. 20. The semiconductor device according to claim 8, wherein the first insulating film is made of silicon nitride having a nitrogen composition ratio of 1 to 3/4 when a silicon composition ratio is 1. An insulated gate type semiconductor device characterized by the above-mentioned. 21. The semiconductor device according to claim 8, wherein the fourth insulating film is made of silicon nitride in which the composition ratio of nitrogen is 1 to 3/4 when the composition ratio of silicon is 1. An insulated gate type semiconductor device characterized by the above-mentioned. 22. The gate electrode according to claim 8, wherein the gate electrode is made of aluminum, chromium, titanium,
An insulated gate semiconductor device having a layer made of a film containing at least one of tantalum and silicon.