JP2001007333A - SOI structure MOS field effect transistor and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A DTM capable of reducing power consumption even when used under a condition where a gate voltage is relatively high.
It is to provide an OS. SOLUTION: Body regions (p ⁻ region 14, p ⁺ region 1)
6) and the gate electrode 24 are electrically connected via the resistance portion 52. By making the width of a part of the wiring part 56 smaller than the width of the other part of the wiring part 56, a part of the wiring part 56 is used as the resistance part 52. Gate electrode 24
, A forward current flowing through the pn junction formed by the body region and the source region is limited by the resistor 52. Therefore, the current between the body region and the source region can be reduced. As a result, even if the MOS field-effect transistor is used under the condition that the gate voltage is relatively high, the power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to SOI (Sili)
1. Field of the Invention The present invention relates to a MOS field-effect transistor having a con-on-insulator structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art A MOS field effect transistor having an SOI structure can be driven at lower power consumption and at a higher speed than an ordinary MOS field effect transistor.

FIG. 74 is a schematic diagram of an example of a MOS field effect transistor having an SOI structure. Silicon substrate 100
Buried oxide film 11 made of a silicon oxide film
00 is formed. On the buried oxide film 1100, a source region 1200 and a drain region 1300 are formed with a space therebetween. Buried oxide film 110
A body region 1400 is formed on 0 and between the source region 1200 and the drain region 1300. A gate electrode 1500 is formed over body region 1400 with a gate insulating film interposed therebetween.

The body region 1400 of the MOS field effect transistor shown in FIG. 74 is in a floating state. Therefore, carriers generated by the impact ionization phenomenon are accumulated in the body region 1400. When carriers are accumulated, the potential of the body region 1400 changes. This is a phenomenon called a substrate floating effect. Thereby, the kink phenomenon and the parasitic bipolar effect (P
arasictic B-ipolar Effect)
Various disadvantages occur in MOS field-effect transistors.

[0005] SO that can suppress the substrate floating effect
There is a MOS field effect transistor having an I structure. Figure 75
FIG. 1 is a schematic diagram of this MOS field effect transistor. This MOS field effect transistor is a DTMOS (Dyna
mic Threshold-voltage MOS
FET). The difference from the MOS field effect transistor shown in FIG. 74 is that body region 1400 and gate electrode 1500 are electrically connected. With this connection, excess carriers accumulated in body region 1400 can be pulled out of body region 1400. Thereby, the potential of the body region is stabilized, and the occurrence of the substrate floating effect can be prevented.

However, DTMOS has a gate voltage of 1
There is a problem that practical use is possible only under a low gate voltage condition of about V or less. That is, DTMO
In S, a voltage having the same value as the voltage applied to the gate electrode is applied to the body region. When a voltage is applied to the body region, a forward bias voltage is applied to a pn junction formed by the body region and the source region. Since the forward withstand voltage of the pn junction is usually about 0.7 V, when the gate voltage is higher than this, a large current flows between the body region and the source region. This current makes it impossible to achieve low power consumption, which is the purpose of the SOI structure. In addition, a circuit including an SOI structure may malfunction due to this current. Further, even if the DTMOS is used at a gate voltage of 0.7 V or less, a small amount of forward current flows between the body region and the source region, which is disadvantageous in achieving low power consumption.

An object of the present invention is to provide a MOS field effect transistor having an SOI structure capable of reducing power consumption even when used under a condition where a gate voltage is relatively high, and a method of manufacturing the same. That is.

[0008]

Means for Solving the Problems (1) The present invention provides an SOI
A MOS field-effect transistor formed on a substrate, comprising: a source region, a drain region, a body region, a gate electrode, a gate insulating film, a first contact portion, a second contact portion, and a resistance portion, wherein the body region is A gate electrode formed between the source region and the drain region, having a first end and a second end, the gate electrode being formed on the body region via a gate insulating film, and The first contact portion extends from the first end portion to the second end portion, and the first contact portion is formed on the first end side, and the first contact portion is connected to the gate electrode and the gate electrode. A gate signal line for transmitting a gate signal to be transmitted, a second contact portion is formed on the second end side,
In the second contact portion, the gate electrode and the body region are electrically connected, the resistor portion is formed on the second end side, and the gate electrode and the source region are electrically connected via the resistor portion. It is connected.

In the DTMOS, the body region and the gate electrode are electrically connected. Further, the body region and the source region have a pn junction. For this reason,
For example, in the case of an nMOS, when a positive voltage is applied to the gate electrode, a forward voltage is applied to the pn junction. When a voltage equal to or higher than the forward breakdown voltage of the pn junction is applied between the gate electrode and the source region, a current flows between the gate electrode and the source region via the body region. This current increases as the gate voltage increases. Therefore, when used under the condition that the gate voltage is relatively high, the power consumption of the DTMOS increases.

In the SOI-structure MOS field effect transistor according to the present invention, the gate electrode and the source region are
They are electrically connected via a resistor. Therefore, the forward current flowing through the pn junction is limited by the resistance portion, and the current between the body region and the source region can be reduced. As a result, even if the DTMOS is used under the condition that the gate voltage is relatively high, the power consumption of the DTMOS can be reduced.

Further, in the MOS field effect transistor having the SOI structure according to the present invention, the resistance portion is formed on the second end side. Therefore, even if a voltage drop occurs due to the resistance portion, a desired signal voltage can be applied to the gate electrode. That is, the signal voltage is transmitted from the first contact portion (the first end side) to the gate electrode and then to the second contact portion (the second end side). Therefore,
If the resistance portion is on the first end side, a desired voltage may not be applied to the gate electrode due to a voltage drop caused by the resistance portion. In the MOS field effect transistor having the SOI structure according to the present invention, since the resistance portion is on the second end side, such a situation can be prevented.

Further, in the SOI structure MOS field effect transistor according to the present invention, the first contact portion is formed on the first end side, and the second contact portion is formed on the second end side. I have. Thus, according to the present invention,
Since current flows through the gate electrode, the gate electrode itself can also function as a resistor.

In the SOI-structure MOS field-effect transistor according to the present invention, the field-effect transistor has an effect of reducing power consumption regardless of whether it is a partially-depleted type or a fully-depleted type. The reason is [Experimental example] of the embodiment of the invention.
Will be described.

The SOI-structure MOS field effect transistor according to the present invention can be manufactured by the following steps.

(A) A first end and a second end are formed on an SOI substrate.
(B) forming a gate electrode extending in a direction from the first end to the second end on the body region, and (c) forming a gate electrode on the body region. Implanting ions into the SOI substrate using the electrodes as a mask to form source and drain regions so as to sandwich the body region, (d) a gate electrode on the first end side;
A first contact portion is formed to be electrically connected to a gate signal line for transmitting a gate signal input to the gate electrode, and the gate electrode and the body region are electrically connected to the second end. Forming a second contact portion to be formed,
(E) a step of forming a resistance portion electrically connected to the gate electrode and the source region on the second end side in the steps (b) to (d).

(2) The SOI-structure MOS field effect transistor according to the present invention preferably includes the following wiring portion. The resistance part is included in the wiring part. The wiring portion is formed on the second end side, and electrically connects the gate electrode and the second contact portion. By making the width of one part of the wiring part smaller than the width of other parts of the wiring part,
A part of the wiring part is a resistance part.

In this embodiment, the width of a portion of the wiring portion is made smaller than the width of the other portion of the wiring portion, so that a portion of the wiring portion is used as a resistance portion. According to this aspect, the resistance value of the resistance section can be controlled by the combination of the width of a part of the wiring part and the length of the part of the wiring part. That is, as the width W increases, the resistance value decreases, and as the width W decreases, the resistance value increases. When the length L is increased, the resistance value increases, and when the length L is decreased, the resistance value decreases.

The SOI-structure MOS field effect transistor according to this embodiment can be manufactured by the following steps.

The step (e) includes the step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion in the step (b). Is patterned so that the width of a part of the wiring part is smaller than the width of the other part of the wiring part.

(3) The SOI-structure MOS field-effect transistor according to the present invention preferably includes the following wiring portion. The resistance part is included in the wiring part. The wiring section includes a polysilicon film. The wiring portion is formed on the second end side, and electrically connects the gate electrode and the second contact portion. By making the impurity concentration of a part of the wiring part lower than the impurity concentration of the other part of the wiring part, a part of the wiring part is used as a resistance part.

In this aspect, the impurity concentration of a portion of the wiring portion is made lower than the impurity concentration of the other portion of the wiring portion, so that a portion of the wiring portion is used as a resistance portion. According to this aspect, it is possible to simultaneously form the film serving as the wiring portion and the film serving as the resistor portion without increasing the area of the resistor portion.

The MOS field effect transistor having the SOI structure according to this embodiment can be manufactured by the following steps.

The step (e) includes a step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion including the polysilicon film in the step (b). The forming step is such that the impurity concentration of a portion of the wiring portion is lower than the impurity concentration of another portion of the wiring portion. As a method of making the impurity concentration of a part of the wiring part lower than the impurity concentration of the other part of the wiring part, for example, a polysilicon film is formed and only a part of the film is covered with a mask. Then, ions are implanted into this film. Since ions are not implanted into a part of this film,
The impurity concentration of a part of this film can be made lower than the impurity concentration of another part of the film.

(4) The SOI-structure MOS field-effect transistor according to the present invention preferably includes the following wiring portion. The resistance part is included in the wiring part. The wiring portion is formed on the second end side, and electrically connects the gate electrode and the second contact portion. By forming a part of the wiring part only with the polysilicon film and the other part of the wiring part having a structure including the polysilicon film and the silicide film, a part of the wiring part is used as a resistance part.

In this embodiment, a portion of the wiring portion is formed of only a polysilicon film, and the other portion of the wiring portion is formed of a structure including a polysilicon film and a silicide film, so that a portion of the wiring portion is formed as a resistance portion. . According to this aspect, it is possible to simultaneously form the film to be the wiring portion and the film to be the resistance portion while keeping the resistance of the wiring portion low.

The SOI structure MOS field effect transistor according to this embodiment can be manufactured by the following steps.

The step (e) includes the step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion in the step (b). Is formed only of a polysilicon film, and the other portion of the wiring portion includes a polysilicon film and a silicide film. Such a structure can be formed by, for example, a method of removing a silicide film in a part of a wiring portion or a method of preventing a silicide film from being formed in a part of a wiring portion. The method for removing the silicide film from a part of the wiring portion is as follows. A polysilicon film is formed, and a high melting point metal film is formed on the polysilicon film. The refractory metal film is annealed to form a silicide film. Then, the silicide film on a part of the wiring portion is removed.

A method for preventing a silicide film from being formed on a part of the wiring portion is as follows. A polysilicon film is formed. A refractory metal film is formed on the polysilicon film in a region other than a region that becomes a part of the wiring portion. The refractory metal film is annealed to form a silicide film.

(5) The SOI-structure MOS field effect transistor according to the present invention preferably has the following body region. The body region electrically connects the second contact portion and the source region. By setting the distance between the second contact portion and the source region to be equal to or longer than the minimum distance according to the design rule of the distance, the body region is used as the resistance portion.

According to this aspect, the body region is lengthened by setting the distance between the second contact portion and the source region to be equal to or greater than the minimum distance in the design rule of the distance, and the body region serves as a resistor. Is fulfilled. According to this aspect, a new process for forming the resistance portion is not required.
Since the elongation of the body region is only a problem in design design, the resistance portion can be easily formed. The distance is, for example, 1 μm or more.

The SOI structure MOS field effect transistor according to this embodiment can be manufactured by the following steps.

Step (e) is the same as step (d)
Forming a second contact portion at a position such that the distance between the contact portion and the source region is equal to or greater than the minimum distance in the design rule of this distance.

(6) The SOI-structure MOS field-effect transistor according to the present invention preferably includes the following wiring portion. The wiring portion is formed on the second end side, and electrically connects the gate electrode and the second contact portion. By setting the length of the wiring portion to be equal to or longer than the shortest distance between the second contact portion and the gate electrode, the wiring portion becomes a resistance portion.

In this embodiment, the length of the wiring portion is increased by making the length of the wiring portion equal to or longer than the shortest distance between the second contact portion and the gate electrode. Then, the entire wiring portion is used as a resistance portion. As the distance, for example, 1
μm or more.

The structure in which the length of the wiring portion is equal to or longer than the shortest distance between the second contact portion and the gate electrode includes, for example, the following structure. The element isolation insulating layer is located so as to surround the source region and the drain region. The wiring portion is detoured on the plane of the element isolation insulating layer and is electrically connected to the second contact portion. According to this structure, since the resistance portion is formed on the element isolation insulating layer, a region on the element isolation insulating layer can be effectively used.

Such a structure can be manufactured by the following steps. The step (e) includes, in the step (b), a step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion, and the wiring portion forming step includes a source region and a drain region. The wiring portion is patterned so that the wiring portion is bypassed and electrically connected to the second contact portion on the plane of the element isolation insulating layer positioned so as to surround.

As another structure in which the length of the wiring portion is equal to or longer than the shortest distance between the second contact portion and the gate electrode, for example, there is the following structure. The interlayer insulating film covers the gate electrode. The wiring portion passes over the interlayer insulating film and is electrically connected to the second contact portion. According to this structure, since the resistance portion is formed on the interlayer insulating film, a region on the interlayer insulating film can be effectively used.

Such a structure can be manufactured by the following steps. The step (e) includes, after the step (c), a step of forming an interlayer insulating film so as to cover the gate electrode, a step of forming a through hole in the interlayer insulating film, and a step of forming a through hole on the interlayer insulating film. Forming a wiring portion for electrically connecting the gate electrode and the second contact portion.

(7) The SOI-structure MOS field effect transistor according to the present invention preferably has the following body region. The impurity concentration of the body region is a concentration at which the body region functions as a resistor. In this embodiment, the body region functions as a resistance section by controlling the impurity concentration of the body region. As the body region functioning as a resistance portion, there are a portion located below the second contact portion and a portion located below the gate electrode.

(8) In the SOI-structure MOS field effect transistor according to the present invention, for example, the resistance value of the resistance portion has the following value. The resistance value of the resistance section is larger than the ON resistance value of the field effect transistor.

It is preferable that the resistance value of the resistance portion is at least 10 times larger than the ON resistance value of the field effect transistor. The current flowing through the field-effect transistor has a value obtained by adding the value of the current (Igs) between the gate electrode and the source region to the value of the current (Ids) between the drain region and the source region. If the resistance value of the resistance portion is 10 times or more larger than the ON resistance value of the field effect transistor, the following can be said. That is, the value of the current between the gate electrode and the source region is about one-tenth or less of the value of the current between the drain region and the source region. Incidentally, about 10% inevitably occurs in the electrical characteristics of the semiconductor device. Therefore, even if the value of the current between the gate electrode and the source region is added to the value of the current between the drain region and the source region, the total value is the drain-source current (I
ds) falls within the range of error.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Description of Structure} FIG. 1 is a plan view of a MOS field effect transistor having an SOI structure according to a first embodiment of the present invention. FIG. 2 is a sectional structural view showing a state where the MOS field effect transistor shown in FIG. 1 is cut along the line AA. This SOI structure MOS field effect transistor is:
By making the width of a part of the wiring part 56 smaller than the width of the other part of the wiring part 56, a part of the wiring part 56 is used as the resistance part 52. The structure of the MOS field effect transistor having the SOI structure shown in FIG. 2 will be described with reference to FIG. The SOI substrate includes a silicon substrate 10, a buried oxide film 12, and a silicon layer. On silicon substrate 10, buried oxide film 12 made of a silicon oxide film is formed. On the buried oxide film 12, a silicon layer is formed. A body region (p ⁻ region 14, p ⁺ region 16) and the like are formed in the silicon layer.

On the buried oxide film 12, a p ^- region 14 is formed.
And field oxide film 1 so as to sandwich p ⁺ region 16.
8 and 20 are formed. As shown in FIG. 1, the drain region 38 and the source region 40 sandwich the p ⁻ region 14 therebetween.
Are formed. A gate oxide film 22 is formed on p ⁻ region 14. On the gate oxide film 22, a gate electrode 24 is formed. The gate electrode 24 is electrically connected to the wiring section 56. The width of a part of the wiring part 56 is smaller than the width of the other part of the wiring part 56. The portion having the small width becomes the resistance portion 52. As shown in FIG. 1, the width W of the resistance portion 52 is, for example, 0.1 to 0.5 μm. The length L of the resistance section 52 is, for example, 1 to 10 μm. The gate electrode 24, the wiring part 56, and the resistance part 52
It is formed simultaneously by patterning the polysilicon film. Note that the gate electrode 24 extends over the field oxide film 20.

A silicon oxide film 26 is formed on the SOI substrate so as to cover gate electrode 24. Through holes 28 and 30 are formed in the silicon oxide film 26. The through hole 28 is formed in the body region (p ⁻ region 1).
4, p ⁺ region 16) on the second end 15 side. The p ⁺ region 16 is exposed by the through hole 28. An aluminum filling film 34 fills the inside of the through hole 28. The wiring portion 56 and p
⁺ Region 16 is electrically connected. A portion where the wiring portion 56 is electrically connected to the p ⁺ region 16 is a second contact portion 50.

The through hole 30 is formed on the first end 17 side of the body region (p ⁻ region 14, p ⁺ region 16). On the silicon oxide film 26, the gate signal wiring 3
6 are formed. The gate signal input to the gate electrode 24 is transmitted from the gate signal line 36. Gate signal wiring 36 is made of aluminum. The gate signal wiring 36 is also filled in the through hole 30. The gate signal wiring 36 and the gate electrode 24 are electrically connected via the gate signal wiring 36 filled in the through hole 30. The connection portion between the gate signal wiring 36 and the gate electrode 24 becomes the first contact portion 42. The gate signal passes through the first contact portion 42 and is transmitted to the gate electrode 24.

FIG. 3 is a diagram showing an equivalent circuit of the MOS field effect transistor having the SOI structure according to the first embodiment of the present invention shown in FIGS. 1 and 2. Reference numerals 14 and 16 denote body regions (p ⁻ region 14 and p ⁺ region 16), 24 denotes a gate electrode, 38 denotes a drain region, 40 denotes a source region, and 52 denotes a resistance portion.

<< Description of Manufacturing Method >> A method of manufacturing the MOS field effect transistor having the SOI structure according to the first embodiment of the present invention will be described. FIG. 4 is a plan view of the SOI substrate. FIG. 5 is a sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. As shown in FIGS. 4 and 5, the SOI substrate includes a silicon substrate 10, a buried oxide film 12 formed on the silicon substrate 10, and a silicon layer 13 formed on the buried oxide film 12.

FIGS. 6 and 7 (FIG. 7 shows the SOI shown in FIG. 6).
FIG. 3 is a sectional structural view showing a state where the substrate is cut along the line AA. As shown in (1), field oxide films 18 and 20 are formed on the silicon layer 13 by using, for example, the LOCOS method. Field oxide films 18 and 20 are formed so as to surround a region where an nMOS field effect transistor is formed. Next, p-type ions are implanted into the silicon layer 13 using the field oxide films 18 and 20 as a mask,
A p ⁻ region 14 is formed in a region where a MOS field effect transistor is formed. As the p-type acceptor, for example, there is boron. The energy of ion implantation is
For example, it is about 20 KeV. The dose is, for example, 6 × 10 ¹² / cm ² .

FIGS. 8 and 9 (FIG. 9 shows the SOI shown in FIG. 8).
Sectional structural drawing showing the state where the substrate was cut along line AA.
It is. ), Then, for example, by thermal oxidation
, P ^-A thin oxide film serving as a gate oxide film on the region 14
(Thickness: 7 nm).

Next, a polysilicon film (film thickness 2) serving as a gate electrode is formed on the entire surface of the SOI substrate by, eg, CVD.
50 nm).

Next, the polysilicon film is patterned by a photolithography technique and an etching technique,
The gate electrode 24 is formed. Second end 1 of body region
On the side of the gate electrode 24, the field oxide film 1
8 is not on. A region between the gate electrode 24 and the field oxide film 18 is referred to as a region 46. On the other hand, on the first end 17 side of the body region, the gate electrode 24
Are running on the field oxide film 20.

As shown in FIGS. 10 and 11 (FIG. 11 is a sectional structural view showing a state where the SOI substrate shown in FIG. 10 is cut along the line AA).
Is formed to cover the resist. Using the resist 44 and the field oxide films 18 and 20 as a mask, n-type ions are implanted into a region where the nMOS field effect transistor is to be formed, and a source region 40 and a drain region 38 are formed. Examples of the n-type ion include phosphorus. The energy of the ion implantation is, for example, 40 KeV. The dose is, for example, 2 × 10 ¹⁵ / cm ² .

As shown in FIGS. 12 and 13 (FIG. 13 is a sectional structural view showing a state where the SOI substrate shown in FIG. 12 is cut along the line AA).
Is formed to expose the resist. Using the resist 48 as a mask, p-type ions are implanted into the region 46 to form the p ⁺ region 16. Examples of the p-type ion include boron. The energy of the ion implantation is, for example, 20 KeV. The dose amount is, for example, 2
× 10 ¹⁵ / cm ² .

As shown in FIGS. 14 and 15 (FIG. 15 is a sectional structural view showing a state where the SOI substrate shown in FIG. 14 is cut along the line AA). A silicon oxide film 26 (500 nm thick) is formed on the entire surface of the SOI substrate.

The silicon oxide film 26 is selectively removed by photolithography and etching to form through holes 28 and 30. Through hole 28 exposes p ⁺ region 16. The through hole 30 exposes the gate electrode 24 on the field oxide film 20.

As shown in FIGS. 1 and 2, an aluminum film (500 nm thick) is formed on the entire surface of the SOI substrate by, for example, a sputtering method.

The aluminum film is patterned by photolithography and etching to form an aluminum filling film 34 and a gate signal wiring 36. Thus, the MOS field effect transistor having the SOI structure according to the first embodiment is completed.

{Explanation of Effect} (Effect 1) As shown in FIGS. 1 and 2, in the MOS field effect transistor having the SOI structure according to the first embodiment of the present invention, the gate electrode 24, the source region 40, Is
They are electrically connected via a resistance section 52. Resistance part 5
By providing 2, the following effects are produced.
As shown in FIG. 3, when a positive voltage is applied to the gate electrode 24, the body region (p ⁻ region 14,
A positive voltage having the same value is also applied to the p ⁺ region 16). Since the body region is p-type and the source region 40 is n-type, a pn junction is formed between the body region and the source region 40. Usually, since the source region 40 is a reference voltage, a forward voltage is applied to a pn junction between the body region and the source region 40 by applying a positive voltage to the gate electrode 24. Therefore, if there is no resistance portion 52, the gate electrode 2
A current (Igs) flows between the source region 4 and the source region 40. This current is an undesirable current because it does not flow in a normal MOS field-effect transistor. In addition, when a voltage equal to or higher than the forward breakdown voltage of the pn junction is applied between the gate electrode 24 and the source region 40, a current (Igs) flowing between the gate electrode 24 and the source region 40 is reduced. 40 and drain region 38
May be larger than the current (Ids) flowing between them.

The MOS field effect transistor having the SOI structure according to the first embodiment of the present invention includes a resistor 52. Therefore, the forward current flowing through the pn junction is limited by the resistance portion 52, and the body region and the source region 4
The current between 0 and 0 can be kept low. As a result,
Even when the SOI-structure MOS field effect transistor according to the first embodiment is used under the condition that the gate voltage is relatively high, the power consumption of the MOS field effect transistor can be reduced.

Although the first embodiment has been described with reference to an nMOS field effect transistor, a similar effect is produced for a pMOS field effect transistor.

Further, S according to the first embodiment of the present invention
In the MOS field effect transistor having the OI structure, the resistance section 52 is formed on the second end 15 side. Therefore, even if a voltage drop occurs due to the resistance section 52, a desired signal voltage can be applied to the gate electrode. That is,
The signal voltage is applied to the first contact portion 42 (the first end portion 17).
Side) to the gate electrode 24 and the wiring section 56, and then to the second contact section 50 (the second end 15 side). Therefore, when the resistance portion 52 is on the first end portion 17 side,
There is a possibility that a desired voltage may not be applied to the gate electrode 24 due to a voltage drop caused by the resistor 52. In the MOS field effect transistor having the SOI structure according to the first embodiment of the present invention, since the resistance portion 56 is on the second end 15 side,
Such a situation can be prevented.

Further, according to the first embodiment of the present invention,
In the MOS field effect transistor having the OI structure, the first
The contact portion 42 is formed on the first end portion 17 side, and the second contact portion 50 is formed on the second end portion 15 side. Therefore, according to the first embodiment of the present invention, since a current flows through the gate electrode 24, the gate electrode 2
4 itself can also function as a resistor.

(Effect 2) As shown in FIG. 1, in the SOI-structure MOS field-effect transistor according to the first embodiment of the present invention, the width of a portion of the wiring portion 56 is Of the wiring portion 56 is used as the resistance portion 52. Therefore, the resistance value of the resistor 52 can be controlled by a combination of the width W of the resistor 52 and the length L of the resistor 52. That is, the width W
When the value is increased, the resistance value decreases. When the value is decreased, the resistance value increases. When the length L is increased, the resistance value increases, and when the length L is decreased, the resistance value decreases.

[Second Embodiment] {Description of Structure} FIG. 16 is a plan view of a MOS field effect transistor having an SOI structure according to a second embodiment of the present invention. FIG. 17 is a sectional structural view showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 16 is cut along the line AA. The difference from the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. That is, in the second embodiment of the present invention, by making the impurity concentration of a part of the wiring part 56 lower than the impurity concentration of the other part of the wiring part 56, the part of the wiring part 56 is used as the resistance part 52. . In the SOI-structure MOS field-effect transistor according to the second embodiment of the present invention, the same elements as those of the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. The description is omitted by using the same reference numerals.

{Description of Manufacturing Method} First, FIG. 4 (FIG. 5)
The steps up to the step shown in FIG. 6 (FIG. 7) are performed. In the steps so far, the method for manufacturing the MOS field effect transistor having the SOI structure according to the second embodiment is the same as the method for manufacturing the MOS field effect transistor having the SOI structure according to the first embodiment. After the step shown in FIG. 6 (FIG. 7), as shown in FIGS. 18 and 19 (FIG. 19 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 18 is cut along the line AA). Then, a thin oxide film serving as a gate oxide film is formed on p ⁻ region 14. The same method and conditions as in the first embodiment can be used for the formation method and conditions. Next, for example, by a CVD method, a non-doped polysilicon film (having a thickness of 200 to 50
0 nm). The forming conditions are, for example, as follows.

Temperature: 580 to 620 ° C. Time: 10 to 30 minutes Next, the polysilicon film is patterned by a photolithography technique and an etching technique to form a gate electrode 2.
4 is formed. On the second end 15 side of the body region, the gate electrode 24 does not run on the field oxide film 18. Gate electrode 24 and field oxide film 18
The region between the two is defined as a region 46. On the other hand, on the first end 17 side of the body region, the gate electrode 24 runs over the field oxide film 20.

As shown in FIGS. 20 and 21 (FIG. 21 is a sectional structural view showing a state where the SOI substrate shown in FIG. 20 is cut along the line AA), a resist 44 covering the region 46 is shown. Then, a resist 45 covering a part of the wiring portion 56 is formed.

As shown in FIGS. 22 and 23 (FIG. 23 is a sectional structural view showing a state where the SOI substrate shown in FIG. 22 is cut along the line AA).
Then, using the field oxide films 18 and 20 as a mask, n-type ions are implanted into a region where the nMOS field effect transistor is formed, thereby forming a source region 40 and a drain region 38. Examples of the n-type ion include phosphorus. The energy of the ion implantation is, for example, 40K
eV. The dose amount is, for example, 2 × 10 ¹⁵ /
cm ² . By this ion implantation, the gate electrode 24
The ions are also implanted into the wiring section 56. However, since the resist 45 is present on a part of the wiring part 56, ions are not implanted into this part. This part becomes the resistance part 52.

If the resistance value of the resistance section 52 is not the desired value, the following steps are added. First, source area 4
After the formation of the 0 and drain regions 38, the resists 44 and 45 are removed. Next, n-type ions are implanted into the entire surface of the SOI substrate at a dose such that the resistance value of the resistance section 52 becomes a desired value.

Next, FIGS. 24 and 25 (FIG.
FIG. 4 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. ) Is performed. The steps shown in FIGS. 24 and 25 are the same as the steps shown in FIGS.

Next, FIGS. 26 and 27 (FIG.
FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along the line AA. ) Is performed. The steps shown in FIGS. 26 and 27 are the same as the steps shown in FIGS.

Next, the steps shown in FIGS. 16 and 17 are performed. The steps shown in FIGS. 16 and 17 are the same as the steps shown in FIGS. Thus, the MOS field effect transistor having the SOI structure according to the second embodiment is completed.

{Explanation of Effect} (Effect 1) The effect 1 of the MOS field-effect transistor having the SOI structure according to the second embodiment of the present invention is the same as that of the SOI structure MOS transistor according to the first embodiment of the present invention. This is the same as the effect 1 of the field effect transistor.

(Effect 2) As shown in FIGS. 16 and 17, the SOI structure MO according to the second embodiment of the present invention is
According to the S field effect transistor, the impurity concentration of a part of the wiring part 56 is made lower than the impurity concentration of the other part of the wiring part 56 so that the part of the wiring part 56 is
It is 2. Therefore, according to the second embodiment of the present invention, it is possible to simultaneously form the film serving as the wiring portion and the film serving as the resistor portion without increasing the area of the resistor portion.

The impurity concentration of the resistance section 52 is, for example, 1 × 10 ¹⁷ / cm ^{3 to} 5 × 10 ¹⁹ / cm ³ . At this time, the resistance value is 10 kΩ to 1 MΩ.

Third Embodiment {Description of Structure} FIG. 28 is a plan view of a MOS field effect transistor having an SOI structure according to a third embodiment of the present invention. FIG. 29 is a cross-sectional structure diagram showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 28 is cut along the line AA. The difference from the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. That is, in the third embodiment of the present invention, a portion of the wiring portion 56 has a structure including only the polysilicon film, and another portion of the wiring portion 56 has a structure including the polysilicon film and the silicide film 54. A part of the wiring part 56 is used as the resistance part 52. SOI structure MO according to the third embodiment of the present invention
In the S field effect transistor, the same elements as those of the SOI structure MOS field effect transistor according to the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

{Description of Manufacturing Method} First, FIGS.
The steps up to the step shown in FIG. 6 (FIG. 7) are performed. Up to this point, the method of manufacturing the SOI-structure MOS field-effect transistor according to the third embodiment is the same as the method of manufacturing the SOI-structure MOS field-effect transistor according to the first embodiment. After the step shown in FIG. 6 (FIG. 7), as shown in FIGS. 30 and 31 (FIG. 31 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 30 is cut along the line AA). Then, a thin oxide film serving as a gate oxide film is formed on p ⁻ region 14. The same method and conditions as in the first embodiment can be used for the formation method and conditions. Next, a polysilicon film serving as a gate electrode is formed on the entire surface of the SOI substrate by, for example, a CVD method. As the forming conditions, the same conditions as in the first embodiment can be used.

Next, a Mo film (50 to 200 nm in thickness), which is a refractory metal film, is formed on the entire surface of the polysilicon film by, for example, sputtering. The forming conditions are, for example, as follows.

Temperature: room temperature to 100 ° C. Time: 10 to 30 minutes Then, the refractory metal film is annealed to form a silicide film 54 on the polysilicon film. The annealing conditions are, for example, as follows.

Temperature: 900 to 1050 ° C. Time: Several minutes to 30 minutes Next, the gate electrode 24 is formed by patterning the silicide film 54 and the polysilicon film by photolithography and etching. Second of body area
The gate electrode 24 does not ride on the field oxide film 18 on the end 15 side of the gate electrode 24. A region between the gate electrode 24 and the field oxide film 18 is referred to as a region 46.
On the other hand, on the first end 17 side of the body region, the gate electrode 24 runs over the field oxide film 20.

Next, FIGS. 32 and 33 (FIG.
FIG. 3 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 2 is cut along line AA. ) Is performed. The steps shown in FIGS. 32 and 33 are the same as the steps shown in FIGS. 10 and 11.

Next, FIG. 34 and FIG. 35 (FIG.
FIG. 4 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. ) Is performed. The steps shown in FIGS. 34 and 35 are the same as the steps shown in FIGS.

Next, FIG. 36 and FIG. 37 (FIG.
FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along the line AA. As shown in (), a resist 58 is formed on the entire surface of the SOI substrate. The resist on the position to be the resistance portion is removed. Then, using the resist 58 as a mask, the silicide film 54 is selectively removed. The portion of the wiring portion 56 from which the silicide film 54 has been removed becomes the resistance portion 52. Note that the step of removing the silicide film 54 shown in FIGS. 36 and 37 may be performed after the step shown in FIGS. 30 and 31 or may be performed after the step shown in FIGS. 32 and 33.

Next, FIG. 38 and FIG. 39 (FIG.
FIG. 9 is a sectional structural view showing a state where the SOI substrate shown in FIG. 8 is cut along the line AA. ) Is performed. The steps shown in FIGS. 38 and 39 are the same as the steps shown in FIGS.

Next, the steps shown in FIGS. 28 and 29 are performed. The steps shown in FIG. 28 and FIG. 29 are the same as the steps shown in FIG. 1 and FIG. Thus, the MOS field effect transistor having the SOI structure according to the third embodiment is completed.

<< Explanation of Effects >> (Effect 1) The effect 1 of the MOS field effect transistor having the SOI structure according to the third embodiment of the present invention is the same as that of the MOS field effect transistor having the SOI structure according to the first embodiment of the present invention. This is the same as the effect 1 of the field effect transistor.

(Effect 2) As shown in FIGS. 28 and 29, the MO of the SOI structure according to the third embodiment of the present invention is
According to the S field-effect transistor, a portion of the wiring portion 56 is formed of only the polysilicon film, and the other portion of the wiring portion 56 is formed of a structure including the polysilicon film and the silicide film 54. Are the resistance portions 52. Therefore, according to the third embodiment of the present invention,
The film serving as the wiring portion and the film serving as the resistance portion can be simultaneously formed while reducing the resistance of the wiring portion.

[Fourth Embodiment] {Description of Structure} FIG. 40 is a plan view of a MOS field effect transistor having an SOI structure according to a fourth embodiment of the present invention. FIG. 41 is a sectional structural view showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 40 is cut along the line AA. The difference from the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. That is, in the fourth embodiment of the present invention, the distance between the second contact portion 50 and the source region 40 is set to be equal to or more than the minimum distance according to the design rule of the distance, so that the body region (p ⁻ The region 14 and the p ⁺ region 16) are lengthened, and the body region functions as the resistance portion 52. Note that the body region has a function as a wiring portion that electrically connects the source region 40 and the second contact portion 50. In the SOI-structure MOS field-effect transistor according to the fourth embodiment of the present invention, the same elements as those of the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. The description is omitted by using the same reference numerals.

{Description of Manufacturing Method} First, FIGS.
The steps up to the step shown in FIG. 6 (FIG. 7) are performed. In the steps so far, the method for manufacturing the MOS field effect transistor having the SOI structure according to the fourth embodiment is the same as the method for manufacturing the MOS field effect transistor having the SOI structure according to the first embodiment. However, the length of the p ⁻ region 14 of the fourth embodiment is larger than the length of the p ⁻ region 14 of the first embodiment. Thus, the body region of the fourth embodiment is
It becomes longer, and the body region can function as the resistance portion 52. After the step shown in FIG. 6 (FIG. 7), as shown in FIGS. 42 and 43 (FIG. 43 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 42 is cut along the line AA). Then, a thin oxide film serving as a gate oxide film is formed on p ⁻ region 14. The same method and conditions as in the first embodiment can be used for the formation method and conditions. Then, for example,
A polysilicon film serving as a gate electrode is formed over the entire surface of the SOI substrate by a CVD method. As the forming conditions, the same conditions as in the first embodiment can be used.

Next, the polysilicon film is patterned by a photolithography technique and an etching technique,
The gate electrode 24 is formed. Second end 1 of body region
On the side of the gate electrode 24, the field oxide film 1
8 is not on. A region between the gate electrode 24 and the field oxide film 18 is referred to as a region 46. On the other hand, on the first end 17 side of the body region, the gate electrode 24
Are running on the field oxide film 20.

Next, FIG. 44 and FIG. 45 (FIG.
FIG. 4 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. ) Is performed. The steps shown in FIGS. 44 and 45 are the same as the steps shown in FIGS.

Next, FIG. 46 and FIG. 47 (FIG.
FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along the line AA. ) Is performed. The steps shown in FIGS. 46 and 47 are the same as the steps shown in FIGS.

Next, FIGS. 48 and 49 (FIG.
FIG. 9 is a sectional structural view showing a state where the SOI substrate shown in FIG. 8 is cut along the line AA. ) Is performed. The steps shown in FIGS. 48 and 49 are the same as the steps shown in FIGS. 14 and 15.

Next, the steps shown in FIGS. 40 and 41 are performed. The steps shown in FIGS. 40 and 41 are the same as the steps shown in FIGS. Thus, the MOS field effect transistor having the SOI structure according to the fourth embodiment is completed.

<< Explanation of Effect >> (Effect 1) The effect 1 of the MOS field effect transistor having the SOI structure according to the fourth embodiment of the present invention is the same as that of the MOS field effect transistor according to the first embodiment of the present invention. This is the same as the effect 1 of the field effect transistor.

(Effect 2) As shown in FIGS. 40 and 41, the MO of the SOI structure according to the fourth embodiment of the present invention is
According to the S field effect transistor, by setting the distance between the second contact portion 50 and the source region 40 to be equal to or longer than the minimum distance according to the design rule, the body region is lengthened, and the resistance of the body region is reduced. The function of the section 52 is performed. Therefore, according to the fourth embodiment of the present invention, a new step for forming the resistance portion is not required. Since the elongation of the body region is only a problem in design design, the resistance portion can be easily formed.
The distance is, for example, 1 μm or more.

[Fifth Embodiment] {Description of Structure} FIG. 50 is a plan view of an SOI-structure MOS field effect transistor according to a fifth embodiment of the present invention. FIG. 51 is a sectional structural view showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 50 is cut along the line AA. The difference from the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. In other words, in the fifth embodiment of the present invention, the wiring portion 56 bypasses the plane of the field oxide film and
Is electrically connected to Thus, the length of the wiring portion 56 is equal to or longer than the shortest distance between the second contact portion 50 and the gate electrode 24. The entire wiring portion 56 is the resistor portion 52. SO according to a fifth embodiment of the present invention
In the MOS field effect transistor having the I structure, the SOI structure MO according to the first embodiment shown in FIGS.
The same elements as those of the S field effect transistor are denoted by the same reference numerals, and description thereof is omitted.

{Description of Manufacturing Method} First, FIGS.
The steps up to the step shown in FIG. 6 (FIG. 7) are performed. Up to this point, the method for manufacturing the SOI-structure MOS field effect transistor according to the fifth embodiment is the same as the method for manufacturing the SOI-structure MOS field effect transistor according to the first embodiment. After the step shown in FIG. 6 (FIG. 7), as shown in FIGS. 52 and 53 (FIG. 53 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 52 is cut along the line AA). Then, a thin oxide film serving as a gate oxide film is formed on p ⁻ region 14. The same method and conditions as in the first embodiment can be used for the formation method and conditions. Then, for example,
A polysilicon film serving as a gate electrode is formed over the entire surface of the SOI substrate by a CVD method. As the forming conditions, the same conditions as in the first embodiment can be used.

Next, the polysilicon film is patterned by a photolithography technique and an etching technique,
The gate electrode 24 and the wiring part 56 are formed. Wiring unit 56
Extend to the second contact portion in a detour. On the second end 15 side of the body region, the gate electrode 24
It does not run on the field oxide film 18. A region between the gate electrode 24 and the field oxide film 18 is defined as a region 4
6 is assumed. On the other hand, on the first end 17 side of the body region, the gate electrode 24 runs over the field oxide film 20.

Next, FIG. 54 and FIG. 55 (FIG.
FIG. 4 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. ) Is performed. The steps shown in FIGS. 54 and 55 are the same as the steps shown in FIGS.

Next, FIG. 56 and FIG. 57 (FIG.
FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along the line AA. ) Is performed. The steps shown in FIGS. 56 and 57 are the same as the steps shown in FIGS.

Next, FIG. 58 and FIG. 59 (FIG.
FIG. 9 is a sectional structural view showing a state where the SOI substrate shown in FIG. 8 is cut along the line AA. ) Is performed. The steps shown in FIGS. 58 and 59 are the same as the steps shown in FIGS.

Next, the steps shown in FIGS. 50 and 51 are performed. The steps shown in FIGS. 50 and 51 are the same as the steps shown in FIGS. Thus, the MOS field effect transistor having the SOI structure according to the fifth embodiment is completed.

<< Explanation of Effect >> (Effect 1) The effect 1 of the MOS field effect transistor having the SOI structure according to the fifth embodiment of the present invention is the same as that of the SOI structure MOS transistor according to the first embodiment of the present invention. This is the same as the effect 1 of the field effect transistor.

(Effect 2) As shown in FIGS. 50 and 51, the MO of the SOI structure according to the fifth embodiment of the present invention is
According to the S field effect transistor, the wiring portion 56 is bypassed and electrically connected to the second contact portion 50. Therefore, the length of the wiring portion 56 is equal to or longer than the shortest distance between the second contact portion 50 and the gate electrode 24. In the fifth embodiment of the present invention, the entire wiring portion 56 is used as the resistance portion 52 by lengthening the wiring portion 56.
According to the fifth embodiment of the present invention, since the resistance portion is formed on the field oxide film, the region on the field oxide film can be effectively used.

[Sixth Embodiment] {Description of Structure} FIG. 60 is a plan view of a MOS field-effect transistor having an SOI structure according to a sixth embodiment of the present invention. FIG. 61 is a cross-sectional structure diagram showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 60 is cut along the line AA. The difference from the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. That is, in the sixth embodiment of the present invention, the wiring portion 56 passes over the silicon oxide film 26 and is electrically connected to the second contact portion 50. Thereby, the length of the wiring portion 56 is
The distance is set to be equal to or longer than the shortest distance between the second contact portion 50 and the gate electrode 24. The entire wiring portion 56 is connected to the resistance portion 52
And The wiring section 56 is made of a polysilicon film.
The structure of the wiring section 56 will be described in detail. Silicon oxide film 2
6, a through hole 60 is formed. The end of the gate electrode 24 is exposed by the through hole 60.
This end is the end of the gate electrode 24 opposite to the first contact portion 42. The wiring unit 56
It is formed on the silicon oxide film 26. Wiring unit 56
Are also filled in the through holes 28 and 60.

The SOI-structure MOS field-effect transistor according to the sixth embodiment of the present invention is the same as the component of the SOI-structure MOS field-effect transistor according to the first embodiment shown in FIGS. For the element,
The description is omitted by using the same reference numerals.

{Description of Manufacturing Method} First, FIGS. 4 (FIG. 5) to FIG.
The steps up to the step shown in FIG. 6 (FIG. 7) are performed. Up to this point, the method of manufacturing the SOI-structure MOS field-effect transistor according to the sixth embodiment is the same as the method of manufacturing the SOI-structure MOS field-effect transistor according to the first embodiment. After the step shown in FIG. 6 (FIG. 7), as shown in FIGS. 62 and 63 (FIG. 63 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 62 is cut along the line AA). Then, a thin oxide film serving as a gate oxide film is formed on p ⁻ region 14. The same method and conditions as in the first embodiment can be used for the formation method and conditions. Then, for example,
A polysilicon film serving as a gate electrode is formed over the entire surface of the SOI substrate by a CVD method. As the forming conditions, the same conditions as in the first embodiment can be used.

Next, the polysilicon film is patterned by photolithography and etching techniques.
The gate electrode 24 is formed. Second end 1 of body region
On the side of the gate electrode 24, the field oxide film 1
8 is not on. A region between the gate electrode 24 and the field oxide film 18 is referred to as a region 46. On the other hand, on the first end 17 side of the body region, the gate electrode 24
Are running on the field oxide film 20.

Next, FIGS. 64 and 65 (FIG. 65 shows FIG.
FIG. 4 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along the line AA. ) Is performed. The steps shown in FIGS. 64 and 65 are the same as the steps shown in FIGS. 10 and 11.

Next, FIGS. 66 and 67 (FIG.
FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along the line AA. ) Is performed. The steps shown in FIGS. 66 and 67 are the same as the steps shown in FIGS.

Next, FIG. 68 and FIG. 69 (FIG.
FIG. 9 is a sectional structural view showing a state where the SOI substrate shown in FIG. 8 is cut along the line AA. 2), a silicon oxide film 26 is formed on the entire surface of the SOI substrate. As the formation method and conditions, the same methods and conditions as those in the first embodiment described with reference to FIGS. 14 and 15 can be used.

The silicon oxide film 26 is selectively removed by a photolithography technique and an etching technique to form a through hole 28 and a through hole 60. Through hole 28 exposes p ⁺ region 16. The through hole 60 exposes an end of the gate electrode 24. As the formation conditions, the same conditions as in the first embodiment described with reference to FIGS. 14 and 15 can be used.

Next, FIGS. 70 and 71 (FIG.
FIG. 2 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 0 is cut along line AA. ), For example, CV
By a method D, a polysilicon film (film thickness 100 to 500 nm) is formed on the entire surface of the SOI substrate. The forming conditions are, for example, as follows.

Temperature: 580 to 620 ° C. Time: 10 to 30 minutes Reaction gas: monosilane Next, the polysilicon film is patterned by a photolithography technique and an etching technique, and the wiring portion 56 is formed.
(Resistance section 52) is formed. Note that an impurity is introduced into the polysilicon film by an ion implantation method or the like so that the resistance portion 52 has a desired resistance value. The introduction of impurities into the polysilicon film may be performed when the polysilicon film is formed on the entire surface of the SOI substrate or when the polysilicon film is patterned.

Next, FIGS. 72 and 73 (FIG.
FIG. 3 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 2 is cut along line AA. As shown in (), the silicon oxide film 26 is selectively removed by etching to form a through hole 30. The through hole 30 exposes the gate electrode 24 on the field oxide film 20. As the formation conditions, the same conditions as in the first embodiment described with reference to FIGS. 14 and 15 can be used.

Next, as shown in FIG. 60 and FIG.
An aluminum film is formed on the entire surface of the OI substrate. As the formation method and conditions, the same methods and conditions as those in the first embodiment described with reference to FIGS. 1 and 2 can be used.

The aluminum film is patterned by, for example, a lithography technique to form a gate signal line 36. As described above, the SOI according to the sixth embodiment
The MOS field effect transistor having the structure is completed.

<< Explanation of Effect >> (Effect 1) The effect 1 of the MOS field-effect transistor having the SOI structure according to the sixth embodiment of the present invention is the same as that of the MOS field-effect transistor according to the first embodiment of the present invention. This is the same as the effect 1 of the field effect transistor.

(Effect 2) As shown in FIGS. 60 and 61, the MO of the SOI structure according to the sixth embodiment of the present invention is
According to the S field effect transistor, the wiring portion 56 is formed on the silicon oxide film 26. Therefore, the length of the wiring portion 56 is equal to or longer than the shortest distance between the second contact portion 50 and the gate electrode 24. According to the sixth embodiment of the present invention, the length of the wiring portion 56 is increased.
The whole is a resistance section 52. According to the sixth embodiment of the present invention, since the resistance portion is formed on the silicon oxide film 26, the region on the silicon oxide film 26 can be effectively used.

[Seventh Embodiment] An MOS field effect transistor having an SOI structure according to a seventh embodiment of the present invention controls the impurity concentration of the body region so that the body region functions as a resistor. ing. This will be described with reference to FIG. 2 showing the first embodiment of the present invention.
First, a case where the p ⁺ region 16 functions as a resistor will be described. The p ⁺ region 16 is the second contact portion 50
This is the body area below. By controlling the impurity concentration of the p ⁺ region 16, can function p ⁺ region 16 as a resistance portion. The control of the impurity concentration of the p ⁺ region 16 can be performed, for example, by the steps shown in FIGS.

Next, a case where p ^- region 14 functions as a resistance portion will be described. P ⁻ region 14 is a body region below gate electrode 24. p ^- By controlling the impurity concentration in the region 14, p ^- can function region 14 as a resistance unit. The control of the impurity concentration of the p ⁻ region 14 can be performed, for example, by the steps shown in FIGS.

[Experimental Example] The effect of providing the resistor R will be described using an experimental example while explaining the characteristics of the DTMOS. FIG. 74 is a schematic diagram of an example of a MOS field effect transistor having an SOI structure. This structure
This has already been described in the section of Background Art. This structure is hereinafter referred to as a floating body type field effect transistor. FIG. 75 is a schematic diagram of another example of the MOS field effect transistor having the SOI structure. This structure has already been described in the background section. This structure is hereinafter referred to as a DTMOS field effect transistor. FIG. 76 is a schematic diagram of a MOS field-effect transistor having an SOI structure according to an embodiment of the present invention. The difference between the structure shown in FIG. 76 and the structure shown in FIG. 75 is that the structure shown in FIG. This structure is hereinafter referred to as DT according to the embodiment of the present invention.
It is called a MOS field effect transistor.

The operation modes of these MOS field effect transistors include a fully depleted type (Fully Depletion type).
pleated) and partially depleted (Partially)
D-emplified). In general, the fully depleted type has a smaller body region thickness than the partially depleted type. Therefore, the entire body region becomes a depletion layer. On the other hand, in the partially depleted type, the bottom of the body region does not become a depletion layer.

FIG. 77 is a graph showing the relationship between the gate voltage (Vg) and the drain-source current (Ids) of the floating body type field effect transistor.
The conditions are as follows.

Operating mode: Partially depleted type Body region thickness: 175 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 0.1V Resistance part: None As can be seen from the graph, the gate voltage (Vg) is 0.5.
When the drain voltage (Vd) increases in a range around V, the current (Ids) sharply increases even if the gate voltage (Vg) is the same. This is because an increase in the drain voltage (Vd) causes a floating effect on the substrate, which lowers the threshold voltage.

The current (Ids) is, for example, 1.
E-03 (A) indicates that a current of 1 mA flows between the drain and the source.

1. E-03 (A) = 1.0 × 10 ⁻³ (A)
= 1.0 (mA) In the Vg-Ids characteristics shown in FIGS. 77 to 83, the vertical axis (Ids) indicates a value obtained by adding a current between the gate and the source to a current between the drain and the source of the field-effect transistor. Is shown.

FIG. 78 is a graph showing the relationship between the gate voltage (Vg) and the drain-source current (Ids) of the floating body type field effect transistor.
The conditions are as follows.

Operating mode: Fully depleted type Body region thickness: 55 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 .1V Resistance section: None As can be seen from the graph, the phenomenon that occurs in the partially depleted type described above does not occur in the fully depleted type.

FIG. 79 is a graph showing the relationship between the gate voltage (Vg) and the drain-source current (Ids) of the DTMOS field effect transistor. condition is,
It is as follows.

Operating mode: Partially depleted type Body region thickness: 175 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 .1V Resistance: None As can be seen from the graph, in the case of the DTMOS field effect transistor, the phenomenon that occurs in the floating body type field effect transistor (partially depleted type) described above does not occur even in the partially depleted type.

However, as compared with FIG.
In the region of 8 V or more, (Ids) abnormally increases.
This is because the current (Igs) flowing from the gate electrode to the source region via the body region is added to the current between the drain and the source. This is the reason why the increase in the current (Igs) limits the range of a practically usable power supply voltage of the DTMOS field-effect transistor having no resistance portion R.

FIG. 80 is a graph showing the relationship between the gate voltage (Vg) and the drain-source current (Ids) of the DTMOS field effect transistor. condition is,
It is as follows.

Operation mode: Fully depleted type Body region thickness: 55 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 .1V Resistance: None As can be seen from the graph, the DTMOS field effect transistor (fully depleted type) hardly suffers from the phenomenon that occurs in the floating body type field effect transistor (partially depleted type) described above.

However, compared with FIG. 78, (Vg) is 0.7.
(Ids) is abnormally increased in the region above V.
This is because current (Igs) flowing from the gate electrode to the source region via the body region is added to the current between the drain and the source. FIG. 81 shows the gate voltage (Vg) and the drain-source current (Ids) of the DTMOS field effect transistor according to the embodiment of the present invention.
6 is a graph showing the relationship between and. The conditions are as follows.

Operating mode: Partially depleted type Body region thickness: 175 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 .1V Resistor: Yes (56 kΩ) Aspect of Resistor: Sixth Embodiment A DTMOS field-effect transistor according to an embodiment of the present invention includes a resistor R. As can be seen from the graph, in the DTMOS field effect transistor according to the embodiment of the present invention, even when the gate voltage (Vg) is relatively high (1.0 V or more), the current Ids is in a range around 1.E-03. It is kept below. This is because the current between the body region and the source region is suppressed by the resistance portion R. Therefore, the DTMOS field effect transistor according to the embodiment of the present invention can reduce the current (Ids), that is, the power consumption, even when used under the condition that the gate voltage is relatively high. On the other hand, the DTMOS field-effect transistor without the resistance portion R (FIG. 79)
If the gate voltage (Vg) becomes relatively high (1.0 V or more), the current (Ids) cannot be suppressed below a range around 1.E-03.

The DTMO according to the embodiment of the present invention
In the S-type field effect transistor, the phenomenon that occurs in the floating body type field effect transistor (partially depleted type) does not occur.

FIG. 82 shows a DT according to an embodiment of the present invention.
Gate voltage (Vg) of MOS field effect transistor
5 is a graph showing the relationship between the current and the drain-source current (Ids). The conditions are as follows.

Operation mode: fully depleted type Body region thickness: 55 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm Drain voltage Vd: 0.1 V, 1.1 V, 2 .1V Resistor: Yes (56 kΩ) Aspect of Resistor: Sixth Embodiment In FIG. 82, even at Vg (0.7 V or more), no abnormal increase in (Ids) as shown in FIG. 80 is found. . This is because (Igs) is limited by the resistance portion R.

The DTMO according to the embodiment of the present invention
In the S-type field effect transistor, the phenomenon that occurs in the floating body type field effect transistor (partially depleted type) does not occur.

FIG. 83 is a graph showing the case where there is a resistance portion R and the case where there is no resistance portion R together. That is, FIG. 83 shows a graph when the drain voltage (Vd) is 1.1 V among the graphs shown in FIG. FIG. 83 shows a graph when the drain voltage (Vd) is 1.1 V in the graph shown in FIG. When the gate voltage (Vg) is relatively high (1.0
V or more), the current (Ids) of the DTMOS field effect transistor provided with the resistor R
It can be seen that the current is lower than the current (Ids) of the MOS field effect transistor.

FIG. 84 is a graph showing the relationship between the gate voltage (Vg) of the DTMOS field effect transistor and the current (Igs) flowing from the gate electrode through the body region to the source region. The conditions are as follows.

Operation mode: Partially depleted type Body region thickness: 175 nm Element isolation method: LOCOS method Gate electrode width: 25 μm Gate electrode length: 0.6 μm As can be seen from the graph, the resistance R (56 kΩ, resistance When the gate voltage (Vg) is relatively high (0.7 to 0.8 V or more), the current (Igs) is greater when the gate section (the sixth embodiment) is provided than when the resistor section R is not provided. ) Is suppressed. The current (I) of the DTMOS field effect transistor according to the embodiment of the present invention described above
ds) can be set to a relatively low value because the current (Igs) is suppressed.

[Brief description of the drawings]

FIG. 1 is a plan view of a MOS field effect transistor having an SOI structure according to a first embodiment of the present invention.

FIG. 2 is a sectional structural view showing a state in which the MOS field effect transistor having the SOI structure shown in FIG. 1 is cut along the line AA.

FIG. 3 is an equivalent circuit diagram of the SOI-structure MOS field-effect transistor according to the first embodiment of the present invention.

FIG. 4 is a plan view of the SOI substrate for describing a first step of the method for manufacturing the SOI-structure MOS field effect transistor according to the first embodiment of the present invention.

5 is a sectional structural view showing a state where the SOI substrate shown in FIG. 4 is cut along line AA.

FIG. 6 is a plan view of the SOI substrate for describing a second step of the method for manufacturing the SOI-structure MOS field effect transistor according to the first embodiment of the present invention.

FIG. 7 is a sectional structural view showing a state where the SOI substrate shown in FIG. 6 is cut along line AA.

FIG. 8 is a plan view of the SOI substrate for describing a third step of the method for manufacturing a MOS field effect transistor having an SOI structure according to the first embodiment of the present invention.

FIG. 9 is a sectional structural view showing a state where the SOI substrate shown in FIG. 8 is cut along the line AA.

FIG. 10 is a plan view of the SOI substrate for describing a fourth step of the method for manufacturing the SOI-structure MOS field effect transistor according to the first embodiment of the present invention.

11 is a sectional structural view showing a state where the SOI substrate shown in FIG. 10 is cut along the line AA.

FIG. 12 is a plan view of the SOI substrate for describing a fifth step of the method for manufacturing the MOS field-effect transistor having the SOI structure according to the first embodiment of the present invention.

13 is a sectional structural view showing a state where the SOI substrate shown in FIG. 12 is cut along a line AA.

FIG. 14 is a plan view of the SOI substrate for describing a sixth step of the method for manufacturing the MOS field-effect transistor having the SOI structure according to the first embodiment of the present invention.

15 is a sectional structural view showing a state where the SOI substrate shown in FIG. 14 is cut along line AA.

FIG. 16 is a plan view of a MOS field effect transistor having an SOI structure according to a second embodiment of the present invention.

17 is a sectional structural view showing a state where the MOS field-effect transistor having the SOI structure shown in FIG. 16 is cut along the line AA.

FIG. 18 is a plan view of an SOI substrate for describing a first step of a method for manufacturing a MOS field effect transistor having an SOI structure according to a second embodiment of the present invention.

19 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 18 is cut along the line AA.

FIG. 20 is a plan view of the SOI substrate for describing a second step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the second embodiment of the present invention.

21 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 20 is cut along line AA.

FIG. 22 is a plan view of an SOI substrate for describing a third step of the method for manufacturing the MOS field-effect transistor having the SOI structure according to the second embodiment of the present invention.

23 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 22 is cut along the line AA.

FIG. 24 is a plan view of an SOI substrate for describing a fourth step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the second embodiment of the present invention.

25 is a sectional structural view showing a state where the SOI substrate shown in FIG. 24 is cut along line AA.

FIG. 26 is a plan view of an SOI substrate for describing a fifth step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the second embodiment of the present invention.

FIG. 27 is a sectional structural view showing a state where the SOI substrate shown in FIG. 26 is cut along the line AA.

FIG. 28 is a plan view of an SOI-structure MOS field-effect transistor according to a third embodiment of the present invention.

29 is a cross-sectional structure diagram showing a state where the MOS field-effect transistor having the SOI structure shown in FIG. 28 is cut along the line AA.

FIG. 30 is a plan view of an SOI substrate for describing a first step in a method for manufacturing a MOS field effect transistor having an SOI structure according to a third embodiment of the present invention.

FIG. 31 is a sectional structural view showing a state where the SOI substrate shown in FIG. 30 is cut along the line AA.

FIG. 32 is a plan view of an SOI substrate for describing a second step of the method for manufacturing the MOS field-effect transistor having the SOI structure according to the third embodiment of the present invention.

FIG. 33 is a sectional structural view showing a state where the SOI substrate shown in FIG. 32 is cut along the line AA.

FIG. 34 is a plan view of an SOI substrate for describing a third step of the method for manufacturing the SOI-structure MOS field-effect transistor according to the third embodiment of the present invention.

35 is a sectional structural view showing a state where the SOI substrate shown in FIG. 34 is cut along the line AA.

FIG. 36 is a plan view of an SOI substrate for describing a fourth step of the method for manufacturing the MOS field-effect transistor having the SOI structure according to the third embodiment of the present invention.

FIG. 37 is a sectional structural view showing a state where the SOI substrate shown in FIG. 36 is cut along the line AA.

FIG. 38 is a plan view of the SOI substrate for describing a fifth step of the method for manufacturing the SOI-structure MOS field-effect transistor according to the third embodiment of the present invention.

39 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 38 is cut along the line AA.

FIG. 40 is a plan view of a MOS field effect transistor having an SOI structure according to a fourth embodiment of the present invention.

41 is a sectional structural view showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 40 is cut along the line AA.

FIG. 42 is a plan view of an SOI substrate for describing a first step of a method for manufacturing a MOS field effect transistor having an SOI structure according to a fourth embodiment of the present invention.

43 is a sectional structural view showing a state where the SOI substrate shown in FIG. 42 is cut along the line AA.

FIG. 44 is a plan view of an SOI substrate for describing a second step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the fourth embodiment of the present invention.

FIG. 45 is a sectional structural view showing a state where the SOI substrate shown in FIG. 44 is cut along line AA.

FIG. 46 is a plan view of an SOI substrate for describing a third step of the method for manufacturing the SOI-structure MOS field effect transistor according to the fourth embodiment of the present invention.

FIG. 47 is a sectional structural view showing a state where the SOI substrate shown in FIG. 46 is cut along the line AA.

FIG. 48 is a plan view of an SOI substrate for describing a fourth step of the method for manufacturing the SOI-structure MOS field effect transistor according to the fourth embodiment of the present invention.

FIG. 49 is a sectional structural view showing a state where the SOI substrate shown in FIG. 48 is cut along the line AA.

FIG. 50 is a plan view of a MOS field-effect transistor having an SOI structure according to a fifth embodiment of the present invention.

FIG. 51 is a sectional structural view showing a state where the MOS field effect transistor having the SOI structure shown in FIG. 50 is cut along the line AA.

FIG. 52 is a plan view of an SOI substrate for describing a first step in a method for manufacturing a MOS field effect transistor having an SOI structure according to a fifth embodiment of the present invention;

FIG. 53 is a sectional structural view showing a state where the SOI substrate shown in FIG. 52 is cut along the line AA.

FIG. 54 is a plan view of an SOI substrate for describing a second step in the method for manufacturing the MOS field effect transistor having an SOI structure according to the fifth embodiment of the present invention.

FIG. 55 is a cross-sectional structure diagram showing a state where the SOI substrate shown in FIG. 54 is cut along the line AA.

FIG. 56 is a plan view of the SOI substrate for describing a third step of the method for manufacturing the SOI-structure MOS field effect transistor according to the fifth embodiment of the present invention.

FIG. 57 is a sectional structural view showing a state where the SOI substrate shown in FIG. 56 is cut along the line AA.

FIG. 58 is a plan view of an SOI substrate for describing a fourth step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the fifth embodiment of the present invention;

59 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 58 is cut along the line AA.

FIG. 60 is a plan view of an SOI-structure MOS field-effect transistor according to a sixth embodiment of the present invention.

61 is a cross-sectional structural view showing a state where the MOS field-effect transistor having the SOI structure shown in FIG. 60 is cut along the line AA.

FIG. 62 is a plan view of an SOI substrate for describing a first step of a method for manufacturing a MOS field effect transistor having an SOI structure according to a sixth embodiment of the present invention.

63 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 62 is cut along the line AA.

FIG. 64 is a plan view of an SOI substrate for describing a second step of the method for manufacturing the SOI-structure MOS field effect transistor according to the sixth embodiment of the present invention.

65 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 64 is cut along the line AA.

FIG. 66 is a plan view of an SOI substrate for describing a third step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the sixth embodiment of the present invention.

67 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 66 is cut along the line AA.

FIG. 68 is a plan view of an SOI substrate for describing a fourth step of the method for manufacturing the MOS field effect transistor having an SOI structure according to the sixth embodiment of the present invention.

69 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 68 is cut along the line AA.

FIG. 70 is a plan view of an SOI substrate for describing a fifth step of the method for manufacturing the SOI structure MOS field effect transistor according to the sixth embodiment of the present invention.

71 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 70 is cut along the line AA.

FIG. 72 is a plan view of an SOI substrate for describing a sixth step of the method for manufacturing the SOI structure MOS field effect transistor according to the sixth embodiment of the present invention.

73 is a cross-sectional structural view showing a state where the SOI substrate shown in FIG. 72 is cut along the line AA.

FIG. 74 is a schematic view of an example of a MOS field effect transistor having an SOI structure.

FIG. 75 is a schematic view of another example of a MOS field effect transistor having an SOI structure.

FIG. 76 shows an MO having an SOI structure according to an embodiment of the present invention.
It is a schematic diagram of an S field effect transistor.

FIG. 77 is a graph showing characteristics of a floating body type field effect transistor (partially depleted type).

FIG. 78 is a graph showing characteristics of a floating body type field effect transistor (fully depleted type).

FIG. 79 is a graph showing characteristics of a DTMOS field effect transistor (partially depleted type).

FIG. 80 is a graph showing characteristics of a DTMOS field effect transistor (fully depleted type).

FIG. 81 is a graph showing characteristics of a DTMOS field effect transistor (partially depleted type) according to an embodiment of the present invention.

FIG. 82 is a graph showing characteristics of a DTMOS field effect transistor (fully depleted type) according to an embodiment of the present invention.

FIG. 83 is a graph comparing the characteristics of a DTMOS type field effect transistor having a resistance portion R with the characteristics of a DTMOS type field effect transistor having no resistance portion R;

FIG. 84 is a graph showing the relationship between the gate voltage Vg of the DTMOS field effect transistor and the current Igs flowing from the gate electrode through the body region to the source region.

[Explanation of symbols]

Reference Signs List 10 silicon substrate 12 buried oxide film 13 silicon layer 14 p ⁻ region 15 second end 16 p ⁺ region 17 first end 18 field oxide film 20 field oxide film 22 gate oxide film 24 gate electrode 26 silicon oxide film 28 Through hole 30 Through hole 32 Polysilicon film 34 Aluminum filling film 36 Gate signal wiring 38 Drain region 40 Source region 42 First contact portion 44 Resist 45 Resist 46 Region 48 Resist 50 Second contact portion 52 Resistance portion 54 Silicide film 56 Wiring section 58 Resist film 60 Through hole

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Teruo Takizawa 3-3-5 Yamato, Suwa-shi, Nagano F-term in Seiko Epson Corporation (reference) 5F110 AA01 AA09 CC02 DD05 DD13 DD22 EE03 EE05 EE09 EE36 EE37 EE44 EE45 EE48 FF02 FF23 GG28 GG29 GG32 GG34 GG52 HJ01 HJ04 HJ13 HM17 NN62 NN66 QQ09

Claims (22)

[Claims] 1. A MOS field effect transistor formed on an SOI substrate, comprising: a source region, a drain region, a body region, a gate electrode,
A gate insulating film, a first contact portion, a second contact portion, and a resistance portion; wherein the body region is sandwiched between the source region and the drain region; An end portion, wherein the gate electrode is formed on the body region via the gate insulating film, and extends in a direction from the first end portion to the second end portion. The first contact portion is formed on the first end side, and in the first contact portion, the gate electrode and a gate signal line transmitting a gate signal input to the gate electrode are electrically connected. The second contact portion is formed on the second end side, and the gate electrode and the body region are electrically connected in the second contact portion; Is the second And the gate electrode and the source region are electrically connected to each other via the resistor. 2. The device according to claim 1, wherein the resistance portion is included in a wiring portion, the wiring portion is formed on the second end side, and connects the gate electrode and the second contact portion. An MOS field effect transistor having an SOI structure, wherein the MOS field effect transistor is electrically connected, and a part of the wiring part is the resistance part by making a width of a part of the wiring part smaller than a width of another part of the wiring part. 3. The semiconductor device according to claim 1, wherein the resistance section is included in a wiring section, the wiring section includes a polysilicon film, the wiring section is formed on the second end side, and The gate electrode is electrically connected to the second contact portion, and the impurity concentration of a portion of the wiring portion is made lower than the impurity concentration of another portion of the wiring portion, so that the portion of the wiring portion is formed. MOS with SOI structure as resistance part
Field effect transistor. 4. The device according to claim 1, wherein the resistance portion is included in a wiring portion, the wiring portion is formed on the second end side, and connects the gate electrode and the second contact portion. By electrically connecting, a part of the wiring part is made only of a polysilicon film, and another part of the wiring part is made of a structure including a polysilicon film and a silicide film, so that a part of the wiring part is made of the resistance part. A MOS field effect transistor having an SOI structure. 5. The body region according to claim 1, wherein the body region electrically connects the second contact portion and the source region, and a distance between the second contact portion and the source region is: By setting the distance to be equal to or longer than the minimum distance in the design rule, the body region is used as the resistance portion.
MOS field effect transistor of I structure. 6. The semiconductor device according to claim 1, further comprising a wiring portion, wherein the wiring portion is formed on the second end side and electrically connects the gate electrode and the second contact portion. An SOI structure MOS field effect transistor, wherein the length of the wiring portion is equal to or longer than the shortest distance between the second contact portion and the gate electrode, so that the wiring portion serves as the resistance portion. 7. The element isolation insulating layer according to claim 6, further comprising: an element isolation insulating layer positioned so as to surround the source region and the drain region, wherein the wiring portion bypasses on a plane of the element isolation insulating layer. S electrically connected to the second contact portion;
MOS field effect transistor with OI structure. 8. The SOI device according to claim 6, further comprising an interlayer insulating film covering the gate electrode, wherein the wiring portion passes over the interlayer insulating film and is electrically connected to the second contact portion. Structure M
OS field effect transistor. 9. The MOS field effect transistor according to claim 1, wherein the impurity concentration of the body region is a concentration at which the body region functions as the resistor. 10. The SOI-structure MOS field effect transistor according to claim 9, wherein said body region located under said second contact portion has a concentration functioning as said resistance portion. 11. The SOI structure MOS according to claim 9, wherein said body region located under said gate electrode has a concentration functioning as said resistance portion.
Field effect transistor. 12. The device according to claim 1, wherein the resistance value of the resistance portion is O
A MOS field effect transistor having an SOI structure having a larger resistance value than N. 13. The device according to claim 12, wherein the resistance value of the resistance portion is O
A MOS field effect transistor having an SOI structure that is at least 10 times larger than the N resistance value. 14. The SO according to claim 1, wherein the field-effect transistor is of a partially depleted type.
MOS field effect transistor of I structure. 15. The SO field-effect transistor according to claim 1, wherein the field-effect transistor is of a fully depleted type.
MOS field effect transistor of I structure. 16. A method of manufacturing a MOS field-effect transistor formed on an SOI substrate, comprising: (a) forming a body region having a first end and a second end on the SOI substrate; (B) forming a gate electrode extending in a direction from the first end to the second end on the body region; and (c) using the gate electrode as a mask. Implanting ions into the SOI substrate to form a source region and a drain region so as to sandwich the body region; and (d) inputting the gate electrode and the gate electrode on the first end side. Forming a first contact portion electrically connected to a gate signal line for transmitting a gate signal to be transmitted, and the gate electrode and the body region are electrically connected to the second end side. Second contact part Forming, in up to (e) wherein step (b) ~ wherein step (d),
Forming a resistance portion electrically connected to the gate electrode and the source region on the second end side. A method for manufacturing a MOS field effect transistor having an SOI structure, comprising: 17. The method according to claim 16, wherein the step (e) includes the step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion in the step (b). The wiring part forming step includes the step of patterning the wiring part such that a width of a part of the wiring part is smaller than a width of another part of the wiring part. Production method. 18. The wiring according to claim 16, wherein the step (e) includes a polysilicon film in the step (b) and electrically connects the gate electrode and the second contact portion. Forming a wiring part, wherein the wiring part forming step is such that an impurity concentration of a part of the wiring part is lower than an impurity concentration of another part of the wiring part. Production method. 19. The method according to claim 16, wherein the step (e) includes the step of forming a wiring portion for electrically connecting the gate electrode and the second contact portion in the step (b). The wiring part forming step includes the step of forming a part of the wiring part consisting of only a polysilicon film and the other part of the wiring part including a polysilicon film and a silicide film. Production method. 20. The method according to claim 16, wherein in the step (e), in the step (d), a distance between the second contact portion and the source region is a minimum distance on a design rule of the distance. A method of manufacturing a MOS field effect transistor having an SOI structure, comprising a step of forming the second contact portion at the position as described above. 21. The method according to claim 16, wherein the step (e) includes the step of forming a wiring section for electrically connecting the gate electrode and the second contact section in the step (b). The wiring portion forming step is such that, on a plane of an element isolation insulating layer located so as to surround the source region and the drain region, the wiring portion bypasses and electrically connects to the second contact portion. Patterning the wiring portion so as to be connected;
A method for manufacturing an OS field effect transistor. 22. The method according to claim 16, wherein in the step (e), after the step (c), a step of forming an interlayer insulating film so as to cover the gate electrode; and forming a through hole in the interlayer insulating film. And forming a wiring portion on the interlayer insulating film for electrically connecting the gate electrode and the second contact portion via the through hole. Method for manufacturing effect transistor.