JPH0969610A - Integrated semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] Thin film SO that can suppress substrate floating effect
I-MOSFET and this MOSFET are
A manufacturing method that can be formed by an OS process is provided. At least one active region is formed in one active region of an SOI layer.
Mixed NMOSFET and PMOSFET, NM
The channel of the OSFET is electrically connected to the source or drain of the PMOSFET. [Effect] Since holes generated in the channel of the NMOSFET are discharged from the diffusion layer of the PMOSFET, the substrate floating effect is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated semiconductor device and a method for manufacturing the same, and more particularly to an insulated gate field effect transistor formed by using a single crystal semiconductor film formed on an insulating film and a method for manufacturing the same.

[0002]

2. Description of the Related Art Thin film SOI-MOSFE formed on a thin silicon single crystal film (SOI film) formed on an insulating film
T (Silicon On Insulator-Metal Oxise Semiconductor
FieldEffect Transistor) can be integrated at a high density on one substrate by using a silicon microfabrication process, and the parasitic capacitance of the formed transistor is higher than that when a conventional single crystal semiconductor substrate is used. Since it is small, it has features such as being suitable for high-speed operation, and has attracted attention.

However, in the conventional case using a normal semiconductor substrate, a bias potential is applied to the channel portion using the substrate electrode to keep the channel portion at a predetermined potential, whereas in the SOI-MOSFET. Since there is an insulating layer under the SOI film, the channel portion cannot be biased, resulting in a state called "substrate floating", and there is a problem that stable operation is difficult.

That is, since holes are accumulated in the channel portion of the NMOS, a large leak current flows even in the off state, and even in the on state, a kink occurs in the current characteristic, and good characteristics are obtained. Problems such as not being reported have been reported. Such an unfavorable phenomenon is caused by PM
NMO with a relatively small OS but a large impact ionization coefficient
It is known that in S, it appears remarkably.

In order to solve this problem, a method of biasing a channel portion via a gate electrode is disclosed in, for example, IEE Electronic Device Letter, December 1994, p. 512 pages (IEE
E Electron Devices Letter, vol. 15, No. 12, pp. 510
-512, 1995).

FIG. 1 is a plan layout view showing the structure of the device. As is apparent from FIG. 1, this planar arrangement is the same as that of the conventional MOSFET formed on the single crystal substrate. This structure is characterized by the active region 100.
Is patterned to match the gate 500, and contacts from the wiring to the active region 100 (not shown)
However, it is formed at the same time as the contact 600 for the gate electrode 500.

FIG. 2 shows a planar shape of the active region 100 in the structure shown in FIG. 1, which has a so-called dockbone shape in which the contact portion of the gate is projected. As is clear from the cross-sectional shape shown in FIG. 3, the contact has a contact hole penetrating the gate 500. Therefore, not only for the gate 500 but also for the active region 100 provided under the gate 500. , The metal wiring 700 is contacted. In FIG. 3, symbol 120 represents a silicon substrate, 110 represents a silicon oxide film, and 910 represents a gate oxide film.

[0008]

SUMMARY OF THE INVENTION In the above-mentioned prior art,
When forming the active region 100, it is necessary to perform fine patterning in accordance with the gate 500. For forming a contact, an opening is formed so as to penetrate the gate 500 and not penetrate the thin silicon layer 100. There is a need to. In addition, the contract to the gate 500 is changed to the gate 5
The normal M, such as having to do only on the side of 00
There is a problem that it is not suitable for high integration because it is necessary to perform steps that are not performed in the OS transistor process.

An object of the present invention is to solve the above-mentioned conventional problems and to easily form an SOI-MOSFET and such an SOI-MOSFET in which substrate floating does not occur without performing the above-mentioned special process. A method of manufacturing a semiconductor device is provided.

[0010]

In order to achieve the above object, the present invention provides an NMOSFET in the active region of an SOI film.
And PMOSFET are formed, and the diffusion layers (source and drain) of the PMOSFET are arranged so as to be electrically connected to the channel of the NMOSFET.

[0011]

Function: The channel of NMOSFET is PMOSFET
Since it is biased through the diffusion layer of the substrate, the problem of substrate floating is solved. Also, PMOSFET and NM
Since the arrangement of the OSFETs is changed, no special process such as the above-mentioned conventional technique is required, and the OSFETs can be easily formed by the same processing as the conventional MOS process.

[0012]

The present invention will be described below in detail with reference to examples.

First Embodiment FIG. 4 shows a CMOS (Complimentaly) using NMOSFET and PMOSFET.
It shows a CMOS inverter, which is the basis of MOS). CMOS inverter has one NMOSFET
Can be formed only by combining one PMOSFET. In addition, since one of the FETs is turned off between the power supply wirings a and d, a current does not flow, and thus it is a basic unit when a circuit is configured by CMOS.

FIG. 5 shows a planar arrangement of the inverters of this embodiment. The gate 500 corresponds to the active region 100 indicated by a thick line.
Is provided across. Symbol 301 is NMOSF
A mask pattern for forming the source and drain of ET by ion implantation of impurities of the first conductivity type, 401 is a mask pattern for forming the source and drain of PMOSFET, and 600 is a contact to the gate electrode and the source and drain electrodes. , 700 indicate the positions of the wirings, respectively. However, FIG. 5 is for explaining an inverter which is a basic unit, and 700 partially shows wirings connected to each diffusion layer electrode.

In the inverter having the structure shown in FIG. 5,
The arrangement of the diffusion layer and the gate is shown in FIG. As is apparent from FIG. 6, the N-type high-concentration impurity region 300 and the P-type high-concentration impurity region 400 are arranged to face each other on both sides of the gate 500, and the N-type high-concentration impurity region 300 and the P-type high-concentration impurity region 300 are disposed. A P-type low-concentration space 450 is interposed between the regions 400. This space 450
When high-concentration impurity layers of opposite conductivity type are formed to overlap,
Since the withstand voltage significantly deteriorates, in order to prevent it, N
Type high concentration impurity region 300 and P type high concentration impurity region 40
It is provided between 0.

To operate as an inverter, NMO
Ground potential on the power supply electrode a of the SFET, and PMOSFET side d
To the positive potential Vcc. At this time, in the active region 100 on the power supply electrode side, since the PN junction between the N-type impurity diffusion layer 300 and the space 450 is biased in the forward direction, it is necessary to operate to suppress this inter-power supply leakage current. .

FIG. 1 shows the dependence of the current Is of the source electrode on the gate bias voltage Vg in the MOSFET of this embodiment.
The results are shown in FIG. The potential of the space 450 is the drain voltage V
matched to cc. I ₀ is the junction leakage current generated by the forward bias. FIG. 20 shows the junction characteristics of this PN junction, in which the potential on the space 450 side is shown as Vbb. PN by biasing in the positive direction
The junction turns on and current flows. However, since there is a so-called built-in potential, almost no current flows in the small Vbb region. That is, Vcc
The current I _{0 at} that time appears as the leak current in FIG. Therefore, if the channel current is used in a region larger than the leak current, the junction leak does not become a problem. For example, the impurity concentration of the space 450 is 10 ¹⁷ / c
If it is set to about m ³ , it can be operated at a power supply voltage of 0.4V. At this time, since the channel of the NMOSFET is connected to the P-type electrode 400 via the space 450, the holes generated in the channel flow into the diffusion layer 400 and the substrate floating is suppressed.

7 to 13 are views showing a manufacturing process of the semiconductor device of this embodiment, of which FIGS. 7 to 8 and 13 are sectional views taken along the line AA 'including the gate of FIG. The other figures show the BB 'cross section of FIG.

First, as shown in FIG. 7, a silicon oxide film 110 and a thickness of 100 nm are formed on a silicon substrate 120.
The single crystal silicon film 100 was formed by a known method to form an SOI substrate.

Next, as shown in FIG. 8, a well-known silicon oxide film having a thickness of 10 nm formed by the well-known thermal oxidation method and a silicon nitride film having a thickness of 100 nm formed by the CVD method are used. The exposed portion of the single-crystal silicon film 100 was oxidized by the LOCOS method to form a thick oxide film 900 for element isolation, and then the silicon nitride film and the oxide film used as the oxidation mask were removed.
After the surface of the single crystal silicon film 100 is thermally oxidized to form a gate oxide film 910 having a thickness of 5 nm, a known CV is used.
A high-concentration phosphorus-doped polycrystalline silicon film is formed by using the D method, and unnecessary portions are removed by the photoresist method to form a gate electrode 500 made of polycrystalline silicon.
Was formed.

Using the gate electrode 500 and the mask pattern 301 shown in FIG. 5 as a mask, the dose amount is 5 × 1.
Arsenic was ion-implanted under the conditions of 0 ¹⁵ / cm ² and accelerating voltage of 25 keV to form a low-resistance N-type diffusion layer 300 as shown in FIG.

Similarly, the gate electrode 500 and FIG.
Boron is ion-implanted under the conditions of a dose amount of 5 × 10 ¹⁵ / cm ² and an acceleration voltage of 5 keV using the mask pattern 401 shown in FIG. 10 as a mask to form a low-resistance P-type diffusion layer 400 as shown in FIG. did.

A BPSG (boron / phosphorus / silicate glass) film 920 is formed by using a well-known CVD method, and a heat treatment is performed to flatten the surface. Then, as shown in FIG. 11, well-known photo etching is performed. Then, a predetermined portion was selectively removed, and a contact hole was formed to expose the surfaces of the gate electrode 500, the N-type diffusion layer 300 and the P-type diffusion layer 400.

A known metal film is formed and photoetching is performed to form a metal wiring 700 as shown in FIGS. 12 and 13 to form a semiconductor device. FIG. 12 shows the N-type diffusion layer 3
00 and the formation of the wiring 700 connected to the P-type diffusion layer 400, and FIG. 13 shows the wiring 700 connected to the gate 500.
Shows the formation of In this case, unlike the conventional technique shown in FIG. 3, the contact hole only exposes the surface of the gate 500 and does not penetrate the gate 500. Therefore, the metal wiring 700 and the gate 500 are connected to each other on the upper surface of the gate 500, the contact area between them is large, and high reliability is obtained.

<Embodiment 2> FIGS. 14 and 15 are views showing the arrangement of 3-input NAND gates formed by applying the present invention. For example, as shown in FIG. 14, a plurality of N-conductivity type impurity diffusion layers 300 and P-conductivity type impurity diffusion layers 400 are arranged, and a desired one is selected from the plurality of impurity diffusion layers 300 and 400, Figure 1
As shown in FIG. 5, wirings 700 connect to each other. Needless to say, various circuits can be configured by changing the pattern of the wiring 700, and other than the pattern shown in FIG. 15, it can be modified according to the purpose.

FIG. 16 shows an example in which the pattern of the active region 100 is devised to reduce the area of the space 450 in order to reduce the leak current. The leakage current is the same as the N conductivity type impurity diffusion layer 300 and the space 4
It occurs in the PN junction between 50, but above the space 4
By reducing the area of 50 and reducing the area of the PN junction in this portion, the leak current could be effectively reduced.

FIG. 17 shows an example in which the area of the space 450 is further reduced to further reduce the leakage. In this case, there is a problem in alignment accuracy when patterning the space 450 and the gate electrode 500 by patterning, but since there is no junction that causes forward bias, a wide operating voltage range can be obtained.

FIG. 18 shows the gate 500 in FIG.
An example is shown in which the leakage current is reduced by changing the shape. Of course, both the shapes of the active region 100 and the gate 500 may be changed.

[0029]

By forming the NMOSFET and the PMOSFET in the same active region by a normal MOS process, holes generated in the channel of the NMOSFET can be absorbed in the diffusion layer of the PMOSFET, and the substrate floating Can be prevented.

In the above embodiment, an example in which the present invention is applied to a CMOS inverter is shown. However, since the CMOS inverter is the basis of various CMOS digitals, it can be used as it is in many conventional circuit configurations using the inverter. It goes without saying that you can do it.

[Brief description of drawings]

FIG. 1 is a diagram showing a planar arrangement of a conventional active region and a gate,

FIG. 2 is a view showing a planar shape of a conventional active region,

FIG. 3 is a sectional view showing a conventional SOI-MOSFET.

FIG. 4 is an equivalent circuit diagram for explaining the present invention,

FIG. 5 is a plan layout view for explaining the present invention,

FIG. 6 is a plan layout view for explaining the present invention,

FIG. 7 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 8 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 9 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 10 is a process drawing showing the manufacturing method of the first embodiment of the present invention,

FIG. 11 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 12 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 13 is a process drawing showing the manufacturing method of Example 1 of the present invention,

FIG. 14 is a plan view showing a second embodiment of the present invention.

FIG. 15 is a plan layout view showing Embodiment 2 of the present invention,

FIG. 16 is a plan layout view showing Embodiment 2 of the present invention,

FIG. 17 is a plan layout view showing Embodiment 2 of the present invention,

FIG. 18 is a plan view showing a second embodiment of the present invention.

FIG. 19 is a characteristic diagram for explaining the operation of the present invention,

FIG. 20 is a characteristic diagram for explaining the operation of the present invention.

[Explanation of symbols]

100 ... Active region, 110 ... Silicon oxide film, 12
0 ... Silicon substrate, 300 ... N-type high-concentration impurity diffusion layer, 301 ... N-type mask pattern, 400 ... P-type high-concentration impurity diffusion layer, 401 ... P-type mask pattern, 450 ... Space , 500 ... Gate, 600 ...
... contact, 700 ... metal wiring, 900 ... silicon oxide film, 910 ... gate oxide film, 920 ... interlayer insulating film.

Claims (11)

[Claims] 1. An insulating film formed on a semiconductor substrate, an active region made of a single crystal semiconductor film formed on the insulating film and surrounded by an insulating film for isolation, and an active region formed in the active region, respectively. At least a P-channel insulated gate field effect transistor and an N-channel insulated gate field effect transistor, wherein the channel region of the N-channel insulated gate field effect transistor is the source region of the P-channel insulated gate field effect transistor or An integrated semiconductor device, which is electrically connected to a drain region. 2. The integrated semiconductor device according to claim 1, wherein the P-channel insulated gate field effect transistor and the N-channel insulated gate field effect transistor have a common gate electrode. 3. The gate electrode is formed across the active region, and the source region and the drain region of the P-channel insulated gate field effect transistor and the N-channel insulated gate field effect transistor respectively have the gate electrode. The integrated semiconductor device according to claim 2, wherein the integrated semiconductor devices are arranged so as to face each other. 4. The width of the portion of the active region interposed between the source region and drain region of the P-channel insulated gate field effect transistor and the source region and drain region of the N-channel insulated gate field effect transistor. 4. The integrated semiconductor device according to claim 3, wherein the width is smaller than the width of the source region and the drain region. 5. The integrated semiconductor device according to claim 1, wherein the gate electrode is connected to a metal wiring outside the active region. 6. The integrated semiconductor device according to claim 6, wherein the metal wiring is connected to an upper surface of the gate electrode. 7. The integrated semiconductor according to claim 1, wherein an inverter circuit is constituted by the P-channel insulated gate field effect transistor and the N-channel insulated gate field effect transistor. apparatus. 8. The inverter circuit comprises a source electrode of the P channel insulated gate field effect transistor and the N electrode.
The leak current between the source electrodes of the channel insulated gate field effect transistor is operated in a voltage region smaller than the leak current when the N channel insulated gate field effect transistor is in an off state. 7. The integrated semiconductor device according to 7. 9. A step of forming a single crystal silicon film on an insulating film formed on the surface of a semiconductor substrate, and a step of surrounding the single crystal silicon film with an insulating film for isolation to form an active region, Forming a gate insulating film on the active region; forming a gate electrode having a predetermined shape on the gate insulating film; and forming an opening in a first portion of the gate electrode and the active region. A step of forming a first-conductivity-type high-concentration impurity region by doping a first-conductivity-type impurity into the first part through a mask; and a step different from the first part of the gate electrode and the active region. A method of manufacturing an integrated semiconductor device, comprising: doping a second conductivity type impurity into the second part through a mask having an opening in the second part to form a second conductivity type high concentration impurity region. 10. The gate electrode is formed by extending from one side of the isolation insulating film to a side of the isolation insulating film facing the one side through the gate insulating film. The method of manufacturing an integrated semiconductor device according to claim 10, wherein 11. A step of forming a protective insulating film covering the gate electrode after forming the gate electrode, and forming an opening in the protective insulating film outside the active region to expose the surface of the gate electrode. The method of manufacturing an integrated semiconductor device according to claim 11, further comprising a step of exposing and a step of forming a wiring connected to the gate electrode through an opening in the protective insulating film.