JP2000206568A - Electro-optical device and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide an input / output terminal that can be electrically connected well to an external circuit or the like, to reduce the number of steps in a manufacturing process and to display a high-quality image. TF
Provided is an electro-optical device of a T active matrix drive system. An electro-optical device includes a TFT array substrate (1).
0), a TFT (30), a data line (6a), a scanning line (3a), a capacitor line (3b), and a pixel electrode (9a) are provided thereon. The pixel electrode and the TFT are electrically connected by two contact holes (8a, 8b) via the barrier layer (80a). The input / output terminal includes a terminal conductive layer (80s) formed simultaneously from the same film as the barrier layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of an electro-optical device of an active matrix drive system and a method of manufacturing the same, and particularly relates to a pixel electrode and a thin film transistor for pixel switching (hereinafter referred to as TFT as appropriate). It belongs to the technical field of a method of manufacturing input, output or input / output terminals.

[0002]

2. Description of the Related Art Conventionally, an electro-optical device of this type has an electro-optical material such as a liquid crystal sandwiched between a pair of substrates, and one substrate is provided with a plurality of pixel electrodes in a matrix. And, for example, a switching element such as a TFT provided in each pixel needs to be connected to each other. However, between them, a laminated layer having a thickness of, for example, about 1000 nm (nanometer) or more including wirings such as scanning lines, capacitance lines, and data lines and a plurality of interlayer insulating films for electrically insulating these from each other. The presence of the structure makes it difficult to open a contact hole for electrical connection between the two.

On the other hand, in this type of electro-optical device,
In the image display area, data lines, scanning lines, capacitance lines, and the like are wired, and in a peripheral area located around the image display area on the substrate, for example, a wiring or A signal line for supplying various signals such as a clock signal, a control signal, a power signal, and an image signal to a built-in peripheral circuit for driving at least one of a scanning line and a data line and performing an operation test. Is done. In general, input / output terminals for connecting these signal wirings to an external circuit are provided in a terminal area which is a part of the peripheral area. More specifically, each signal line is mainly formed of the same film as a data line such as an Al (aluminum) film having the lowest resistance among the lines in the image display area, and other signal lines that need to intersect with the data lines. At least the intersections of the signal wirings are formed of the same film as the scanning lines such as a polysilicon film whose resistance has been reduced by doping with impurity ions. On the other hand, the pixel electrodes formed in the image display area are mainly made of ITO (Indium Tin) which is a transparent electrode.
Oxide) film.

[0004]

Under the general demand for cost reduction in this type of electro-optical device, the number of steps in the manufacturing process can be reduced and the manufacturing process can be reduced without sacrificing the quality of the displayed image. Simplification is very important.

However, in the manufacturing process for forming the input / output terminals in the terminal region as described above, the Al film, which constitutes the signal wiring, and the ITO film of the pixel electrode, particularly when brought into direct contact with each other, cause electrical corrosion of the Al film. Therefore, in the manufacturing process on the same substrate, before forming the pixel electrode in the image display area, a terminal opening (window) is formed in the interlayer insulating film on the signal wiring to be an input / output terminal in the terminal area. It is necessary to open the window by removing the unnecessary ITO film and the interlayer insulating film on the portion to be the window after forming the pixel electrode without leaving the hole. That is, according to the above-described conventional technology, in order to form input / output terminals in the terminal region, a dedicated photo for forming input / output terminals is formed separately from the step of forming pixel electrodes and the like in the image display region. Special processes such as a lithography process and an etching process are required, and the number of manufacturing processes is increased, and the manufacturing process is complicated.

On the other hand, if at least the vicinity of the input / output terminals of the signal wiring is formed from a polysilicon film forming a scanning line having good electrical compatibility with the ITO film of the pixel electrode,
The opening process of the window of the input / output terminal and the opening process of the contact hole for the pixel electrode as described above may be performed simultaneously. There is a problem that the wiring resistance to the wiring is increased, which causes a signal deterioration.

Further, since the connection surface of the input / output terminal is located in the window opened in the interlayer insulating film located as an upper layer, the height of the edge portion surface of the window and the height of the connection surface are reduced. And the connection between this surface and the FPC (flexible print circuit: flexible print circuit:
In the case where an external circuit such as a flexible printed circuit) is crimped and connected by an anisotropic conductive film (ACF) or the like, there is also a problem that an edge portion of the window disturbs and causes poor crimping. .

The present invention has been made in view of the above-mentioned problems, and has an input / output terminal which can be electrically connected well to an external circuit or the like, so that the number of steps in a manufacturing process can be reduced. An object of the present invention is to provide an electro-optical device capable of displaying high-quality images and a method of manufacturing the same.

[0009]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention has an image display area on a substrate,
A plurality of pixel electrodes, a plurality of scan lines and a plurality of data lines, a thin film transistor connected to each of the scan lines and each of the data lines, and a thin film transistor interposed between a semiconductor layer of the thin film transistor and the pixel electrode; A first conductive layer electrically connected to the semiconductor layer and electrically connected to the pixel electrode on the other side, and a part of a terminal located on the periphery of the image display region on the substrate, The second conductive layer is formed of the same film as the first conductive layer.

According to the electro-optical device of the present invention, in the image display area, the first conductive layer is interposed between the semiconductor layer and the pixel electrode, while being electrically connected to the semiconductor layer. And the other is electrically connected to the pixel electrode. Therefore, the first conductive layer functions as a relay conductive layer for electrically connecting the pixel electrode and the drain region of the semiconductor layer. For example, it is difficult to directly connect the two via one contact hole. Can be avoided.

On the other hand, the second conductive layer is made of the same film as the first conductive layer in the terminal, and at least partially constitutes the terminal. Therefore, in the manufacturing process of the electro-optical device, the step of forming the second conductive layer in the terminal region can be performed simultaneously with the step of forming the first conductive layer in the image display region. That is,
Since at least a part of the dedicated steps for forming the terminals can be reduced, the manufacturing process is simplified, and the electro-optical device can be manufactured relatively easily.

In one aspect of the electro-optical device of the present invention, the terminal is an external circuit connection terminal connected to an external circuit, and a vertical conduction terminal for supplying a common potential to an opposing substrate arranged opposite to the substrate. And at least one of inspection terminals for inspecting the electro-optical device.

According to this aspect, it is possible to reduce at least a part of a dedicated process for forming at least one of the external circuit connection terminal, the vertical conduction terminal, and the inspection terminal in the terminal region.

In another aspect of the electro-optical device according to the present invention, the second conductive layer is connected to one end of a signal wiring formed of the same film as the data line to form the terminal.

According to this aspect, the same film as the data line is, for example, an Al (aluminum) film, and the predetermined type of signal wiring is, for example, a wiring that is electrically connected to at least one of the scanning line and the data line, or a scanning line. Wiring for driving various signals such as a clock signal, a control signal, a power supply signal, and an image signal to a peripheral circuit such as a driving circuit for driving at least one of a data line and a data line or performing an operation test, a test circuit, and the like. And a constant potential wiring to the upper and lower conductive terminals connected to the opposite substrate. By forming the terminals of the signal wiring formed of the same film as the data lines from the second conductive layer in this manner, at least a part of a dedicated process for forming the terminals can be reduced. Further, by forming the second conductive layer from a low-resistance material, the resistance from the terminal to the signal wiring can be reduced.

In another aspect of the electro-optical device according to the present invention, the first conductive layer and the second conductive layer are interposed between the scanning line and the data line.

According to this aspect, in the image display area, the pixel electrode and the semiconductor layer can be electrically connected by the first conductive layer interposed between the scanning line and the data line. On the other hand, with regard to the terminal, by forming the terminal from the second conductive layer interposed between the scanning line and the data line, at least a part of a dedicated process for forming the terminal can be reduced.

In another aspect of the electro-optical device according to the present invention, the first conductive layer and the second conductive layer are interposed between the data line and the pixel electrode.

According to this aspect, in the image display area, the pixel electrode and the semiconductor layer can be electrically connected by the first conductive layer interposed between the data line and the pixel electrode. On the other hand, as for the terminal, by forming the terminal from the second conductive layer interposed between the data line and the pixel electrode, at least a part of a dedicated process for forming the terminal can be reduced.
Note that, in this aspect, a relay conductive layer which is formed of the same layer as the data line and relays the first conductive layer and the semiconductor layer is further provided.
The pixel electrode and the semiconductor layer may be electrically connected via two conductive layers, one conductive layer and a relay conductive layer.

In another aspect of the electro-optical device of the present invention, the electro-optical device further includes an interlayer insulating film interposed between the second conductive layer and the pixel electrode, wherein the second conductive layer is formed on the interlayer insulating film. It has an opening for a terminal that has been opened.

According to this aspect, since the second conductive layer is exposed as a terminal connection surface through the terminal opening formed in the interlayer insulating film, the second conductive layer is exposed through the terminal opening. The second conductive layer and an external circuit such as an FPC can be connected by an anisotropic conductive film or the like.

In another aspect of the electro-optical device according to the present invention, the electro-optical device may include an interlayer insulating film interposed between the second conductive layer and the pixel electrode, and a window formed in the interlayer insulating film. And a conductive thin film formed on the two conductive layers from the same film as the pixel electrode and exposed as a connection surface of the terminal.

According to this aspect, on the second conductive layer, a conductive thin film is formed from the same film as the pixel electrode on the second conductive layer viewed from the terminal opening formed in the interlayer insulating film. Since it is exposed as a terminal connection surface, the conductive thin film and an external circuit such as an FPC can be connected by an anisotropic conductive film or the like through the terminal opening. In particular, if the pixel electrode is I
In the case of using a TO film, a conductive thin film also made of an ITO film and an anisotropic conductive film can be connected with extremely good adhesion. In addition, since the conductive thin film constituting the connection surface of the terminal can be formed simultaneously with the step of forming the pixel electrode, the manufacturing process can be simplified.

In the aspect in which the terminal opening is opened, the second conductive layer is located on the substrate side of the second conductive layer located in the terminal opening when viewed in plan. At least one of the layers interposed between the substrate and the substrate is formed in an island shape, and the second conductive layer located in the terminal opening is raised corresponding to the island shape.

According to this aspect, in the terminal opening,
For example, one or more conductive layers made of the same film as the semiconductor layer, the same film as the scanning line, and the same film as the data line are formed in an island shape, and the second conductive layer is formed on the same in the terminal opening. The conductive layer is raised to correspond to the island shape. For this reason, when the anisotropic conductive film is crimped and connected to the connection surface of the terminal made of the second conductive layer or the conductive thin film inside the terminal opening, the height of the connection surface is reduced. It is possible to prevent poor crimping due to being too lower than the height of the edge surface of the terminal opening.

In another aspect of the electro-optical device according to the present invention, the first conductive layer and the second conductive layer include a high melting point metal.

According to this aspect, the first conductive layer and the second conductive layer are made of, for example, Ti (titanium), Cr (chromium), W
(Tungsten), Ta (tantalum), Mo (molybdenum), Pb (lead), and the like, including a metal simple substance, an alloy, a metal silicide, or the like. For this reason,
In the manufacturing process, the first conductive layer and the second conductive layer are not deformed or broken by high-temperature treatment in various steps performed after the formation of the first conductive layer and the second conductive layer. Further, the resistance from the terminal to the signal wiring can be reduced by forming the second conductive layer with a high melting point metal. However,
The first conductive layer and the second conductive layer may be formed from a polysilicon film whose resistance has been reduced by doping of impurity ions.

In order to solve the above problems, a first method for manufacturing an electro-optical device according to the present invention includes the steps of: forming a semiconductor layer of a thin film transistor in an image display region on a substrate;
Forming an insulating thin film on the semiconductor layer; forming a scanning line including a gate electrode on the insulating thin film; forming a first interlayer insulating film on the scanning line; A first interlayer insulating film communicating with the semiconductor layer;
Forming a first conductive layer on the first interlayer insulating film such that the first conductive layer is electrically connected to the semiconductor layer via the first contact hole; A second conductive layer that at least partially constitutes a terminal around the image display area;
A step of forming the same film as the conductive layer, a step of forming a second interlayer insulating film on the first conductive layer and the second conductive layer, and a step of forming a data line on the second interlayer insulating film Forming a third interlayer insulating film on the data line; and opening a second contact hole in the first interlayer insulating film and the second interlayer insulating film, the second contact hole communicating with the first conductive layer. Forming a terminal opening communicating with the layer; and forming a pixel electrode so as to be electrically connected to the first conductive layer via the second contact hole.

According to the first method of manufacturing the electro-optical device of the present invention, the semiconductor layer, the insulating thin film,
The scanning lines and the first interlayer insulating film are formed in this order. Next, a first contact hole leading to the semiconductor layer is opened in the insulating thin film and the first interlayer insulating film, and a first conductive layer is formed so as to be electrically connected to the semiconductor layer. At the same time, the second conductive layer at least partially constituting the terminal is formed from the same film as the first conductive layer. Further, a second interlayer insulating film, a data line, and a third interlayer insulating film are formed on the first conductive layer and the second conductive layer in this order. Next, in the image display area, a second contact hole leading to the first conductive layer is opened in the first interlayer insulating film and the second interlayer insulating film, and at the same time, a terminal is formed in the second conductive layer. An opening for a terminal is formed to communicate therewith. Then, in the image display area, a pixel electrode is formed so as to be electrically connected to the first conductive layer via the second contact hole. As described above, since the first conductive layer and the second conductive layer are simultaneously formed from the same film and the second contact hole and the terminal opening are simultaneously formed, at least one of the dedicated steps for forming the terminal is performed. Since the number of parts can be reduced, the manufacturing process can be simplified.

According to a second method of manufacturing an electro-optical device of the present invention, in order to solve the above-described problems, a step of forming a semiconductor layer of a thin film transistor in an image display area on a substrate;
Forming an insulating thin film on the semiconductor layer, forming a scanning line including a gate electrode on the insulating thin film, forming a first interlayer insulating film on the scanning line; Forming a first contact hole communicating with the semiconductor layer in the first interlayer insulating film, forming a data line on the first interlayer insulating film, and simultaneously forming a data line from the same film as the data line through the first contact hole. Forming a relay conductive layer so as to be electrically connected to the semiconductor layer, forming a second interlayer insulating film on the data line and the relay conductive layer, and forming the second interlayer insulating film on the second interlayer insulating film. Forming a second contact hole communicating with the relay conductive layer; and forming a first conductive layer on the second interlayer insulating film so as to be electrically connected to the relay conductive layer via the second contact hole. When formed At the same time, forming a second conductive layer at least partially constituting a terminal around the image display region on the substrate, and forming a third interlayer insulating film on the first conductive layer and the second conductive layer. Forming a third contact hole communicating with the first conductive layer in the third interlayer insulating film, and simultaneously opening a terminal hole communicating with the second conductive layer in the third interlayer insulating film; Forming a pixel electrode so as to be electrically connected to the first conductive layer through three contact holes.

According to the second method of manufacturing the electro-optical device of the present invention, the semiconductor layer, the insulating thin film,
The scanning lines and the first interlayer insulating film are formed in this order. Next, a first contact hole leading to the semiconductor layer is formed in the insulating thin film and the first interlayer insulating film, and a data line is formed thereon. At the same time, a first contact hole is formed in the semiconductor layer through the first contact hole. A relay conductive layer is formed from the same film as the data line so as to be electrically connected. Further, a second interlayer insulating film is formed on the data line and the relay conductive layer.
Next, in the image display area, a second contact hole leading to the relay conductive layer is opened in the second interlayer insulating film, and the first conductive layer is formed so as to be electrically connected to the relay conductive layer. At the same time, a second conductive layer that at least partially constitutes a terminal is formed from the same film as the first conductive layer. Next, a third interlayer insulating film is formed on the first conductive layer and the second conductive layer. Next, in the image display area, a third contact hole communicating with the first conductive layer is formed in the third interlayer insulating film. At the same time, with respect to the terminal, a terminal opening is formed in the third interlayer insulating film so as to communicate with the second conductive layer. As described above, since the first conductive layer and the second conductive layer are simultaneously formed from the same film, and the third contact hole and the terminal opening are simultaneously opened, at least a dedicated process for forming the terminal is performed. Since a part can be reduced, the manufacturing process can be simplified.

In one aspect of the first or second method of manufacturing an electro-optical device according to the present invention, in the step of forming the data line, a signal wiring having one end connected to the terminal from the same film as the data line. To form

According to this aspect, the same film as the data line is, for example, an Al film, and the signal wiring is, for example, a wiring conductive to at least one of the scanning line and the data line, or at least one of the scanning line and the data line. A wiring for supplying various signals to a so-called built-in peripheral circuit in which a peripheral circuit is formed together with a thin film transistor on a substrate to drive one of them is provided. By forming the terminals of the signal wiring formed of the same film as the data lines from the second conductive layer in this manner, at least a part of a dedicated process for forming the terminals can be reduced. Further, by forming the second conductive layer from a low-resistance material, the resistance from the terminal to the signal wiring can be reduced.

In another aspect of the first method for manufacturing an electro-optical device according to the present invention, in the step of forming the data line,
Forming a signal wiring having one end connected to the terminal from the same film as the data line, before forming the data line,
The method further includes the step of opening a contact hole for connecting the data line to the semiconductor layer and simultaneously opening a contact hole for connecting one end of the signal wiring to the terminal.

According to this aspect, by forming the terminal of the signal wiring formed of the same film as the data line from the second conductive layer, it is possible to reduce at least a part of a dedicated process for forming the terminal. Further, a contact hole for connecting the data line to the semiconductor layer and a contact hole for connecting one end of the signal wiring to the terminal can be formed simultaneously. In addition, by forming the second conductive layer from a low resistance material, the resistance from the terminal to the signal wiring can be reduced.

In another aspect of the first or second method of manufacturing an electro-optical device according to the present invention, in the step of forming the pixel electrode, a conductive film made of the same film as the pixel electrode is formed in the terminal opening. Form a thin film.

According to this aspect, the conductive thin film made of the same film as the pixel electrode is formed in the terminal opening, but the second conductive layer is formed from the terminal opening formed in the interlayer insulating film. A conductive thin film is formed on the second conductive layer from the same film as the pixel electrode, and is exposed as a connection surface for the terminal. An external circuit can be connected by an anisotropic conductive film or the like. In particular,
When the pixel electrode is composed of an ITO film,
The conductive thin film made of the O film and the anisotropic conductive film can be connected with extremely good adhesion. In addition, since the conductive thin film constituting the connection surface of the terminal can be formed simultaneously with the step of forming the pixel electrode, the manufacturing process can be simplified.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a first embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 2 shows an equivalent circuit such as various elements and wiring in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate shown in FIG.
It is A 'sectional drawing. FIG. 4 is a plan view of the input / output terminals in the terminal region, and FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. In FIGS. 3 and 5, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawings.

In FIG. 1, a plurality of pixels which are formed in a matrix and form an image display area of the liquid crystal device in the present embodiment include a plurality of pixel electrodes 9a and a plurality of TFTs 30 for controlling the pixel electrodes 9a. The data line 6a formed and supplied with the image signal is connected to the TFT 3
0 is electrically connected to the source. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and at a predetermined timing, the scanning line 3a
The scanning signals G1, G2,..., Gm are applied in a pulsed manner in this order. Pixel electrode 9
a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30 as a switching element for a predetermined period, the image signals S1, S2,... Write at the timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are provided by counter electrodes (described later) formed on a counter substrate (described later).
Is maintained for a certain period of time. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the incident light cannot pass through the liquid crystal portion according to the applied voltage. In the normally black mode, the incident light passes through the liquid crystal portion according to the applied voltage. The liquid crystal device emits light having a contrast corresponding to the image signal as a whole.
Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on a TFT array substrate of a liquid crystal device.
(The outline is indicated by a dotted line portion 9a '), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a.
The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a polysilicon film or the like via the contact hole 5a, and the pixel electrode 9a is connected to a region shown by oblique lines rising to the right in the figure. Conductive layers (hereinafter, referred to as barrier layers) 80a each formed and functioning as a buffer
And is electrically connected to a drain region described later in the semiconductor layer 1a through the first contact hole 8a and the second contact hole 8b. In addition, the semiconductor layer 1a
Channel region 1a '(a hatched region falling rightward in the figure)
The scanning line 3a is disposed so as to face the scanning line, and the scanning line 3a functions as a gate electrode. As described above, the TFTs 30 where the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided at the intersections of the scanning lines 3a and the data lines 6a.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding along the data line 6a from a position intersecting the data line 6a.

Further, a first light-shielding film 11a may be provided in a region shown by a thick line in the drawing so as to pass under the scanning line 3a, the capacitor line 3b and the TFT 30, respectively. More specifically, in FIG. 2, the first light-shielding films 11a are each formed in a stripe shape along the scanning lines 3a, and the portions that intersect with the data lines 6a are formed wide at the bottom in the figure. , This wide portion allows at least the channel region 1 of each TFT.
a ′ is provided at a position to cover each when viewed from the TFT array substrate side.

Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device comprises a TFT array substrate 10 which constitutes an example of one transparent substrate, and an example of another transparent substrate which is disposed to face the TFT array substrate 10. And the opposing substrate 20. The TFT array substrate 10 is made of, for example, a quartz substrate, and has a counter substrate 20.
Is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is, for example,
It is made of a transparent conductive thin film such as an ITO film. Also, alignment film 1
6 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode (common electrode). Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 22
Consists of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that performs switching control of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 is provided with a second light-shielding film 23 in the non-opening region of each pixel. For this reason, the incident light from the side of the opposing substrate 20 is applied to the channel region 1 a ′ of the semiconductor layer 1 a of the pixel switching TFT 30 or the source side LDD (Lightly Doped Drain).
It does not enter the region 1b and the drain-side LDD region 1c. Further, the second light-shielding film 23 has a function of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.

The space between the TFT array substrate 10 and the opposing substrate 20 having the above-described structure and in which the pixel electrode 9a and the opposing electrode 21 face each other is provided in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around them,
A gap material (spacer) such as glass fiber or glass beads for mixing the distance between the two substrates to a predetermined value is mixed.

Further, as shown in FIG. 3, a first light shielding film 11a is provided between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each of the pixel switching TFTs 30. First light shielding film 1
1a is preferably an opaque refractory metal Ti, C
It is composed of a simple metal, an alloy, a metal silicide, or the like containing at least one of r, W, Ta, Mo, and Pb. With such a material, the first light-shielding film 11a is not broken or melted by the high-temperature treatment in the step of forming the pixel switching TFT 30 performed after the step of forming the first light-shielding film 11a on the TFT array substrate 10. Can be. Since the first light shielding film 11a is formed, reflected light (return light) from the side of the TFT array substrate 10 is formed.
Pixel switching TFTs that are easily excited by light
30 channel regions 1a 'and source-side LDD regions 1b,
A situation in which the light enters the drain-side LDD region 1c can be prevented beforehand, and the characteristics of the pixel switching TFT 30 do not deteriorate due to generation of a photocurrent due to this.

Further, a base insulating film 12 is provided between the first light shielding film 11a and the plurality of pixel switching TFTs 30. The base insulating film 12 is formed by forming the semiconductor layer 1a constituting the pixel switching TFT 30 into a first light shielding film 11a.
It is provided for electrical insulation from Further, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the pixel switching TFT 30 is formed.
It also has a function as a base film for the purpose. That is, TFT
It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the array substrate 10 during polishing, dirt remaining after cleaning, and the like. The base insulating film 12 is made of, for example, NSG (non-doped silicate glass), PSG
(Phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphor silicate glass), or other high insulating glass, or a silicon oxide film, a silicon nitride film, or the like. The first light-shielding film 1 is formed by the base insulating film 12.
It is also possible to prevent a situation in which 1a contaminates the pixel switching TFT 30 and the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The first storage capacitor 70a is formed by extending the insulating thin film 2 including the film from a position facing the scanning line 3a to form a first dielectric film sandwiched between these electrodes. Further, a part of the barrier layer 80a facing the second storage capacitor electrode is used as a third storage capacitor electrode, and a first interlayer insulating film 81 is provided between these electrodes.
The first interlayer insulating film 81 functions as a second dielectric film,
A storage capacitor 70b is formed. And these first
The storage capacitor 70a and the second storage capacitor 70b are connected in parallel via the first contact hole 8a to form the storage capacitor 70. Here, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a to form a pixel switching TFT 30. Similarly, the capacitor line extending along the data line 6a and the scanning line 3a The first storage capacitor electrode 1f is disposed opposite to the portion 3b with the insulating thin film 2 interposed therebetween, and the insulating thin film 2 functions as a first dielectric film.

The pixel switching TFT 30 is an LDD
Having a structure, a scanning line 3a, a channel region 1a 'of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and an insulation including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a. Thin film 2, data line 6a, low concentration source region (source side LDD region) 1b of semiconductor layer 1a
And low concentration drain region (drain side LDD region) 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
A corresponding one of the plurality of pixel electrodes 9a is connected to e through the barrier layer 80a. Semiconductor layer 1a
Are formed by doping n-type or p-type impurity ions at a predetermined concentration depending on whether an n-type or p-type channel is to be formed, as described later. An n-type channel TFT has the advantage of a high operating speed, and is often used as a pixel switching TFT 30 that is a pixel switching element. In this embodiment, in particular, the data line 6a is formed of a light-shielding and conductive thin film such as a low-resistance metal film such as Al or an alloy film such as metal silicide. Also, the barrier layer 8
0a and the first interlayer insulating film 81, a contact hole 5a leading to the high concentration source region 1d and a barrier layer 80 are formed.
a formed with contact holes 8b each leading to a
An interlayer insulating film 4 is formed. The data line 6a is formed via the contact hole 5a to the high concentration source region 1d.
Are electrically connected to the high-concentration source region 1d. Further, a third contact hole 8b to the barrier layer 80a is formed on the data line 6a and the second interlayer insulating film 4.
An interlayer insulating film 7 is formed. The pixel electrode 9a is electrically connected to the barrier layer 80a via the contact hole 8b, and is further electrically connected to the high-concentration drain region 1e via the contact hole 8a via the barrier layer 80a. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.
As described above, the pixel switching TFT 30 preferably has the LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c, Self-aligned TFT in which high concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using a gate electrode comprising a part of line 3a as a mask
It may be.

In the present embodiment, the gate electrode of the pixel switching TFT 30 which is a part of the scanning line 3a is connected between the high-concentration source region 1d and the high-concentration drain region 1e.
Although only the single gate structure is used, two or more gate electrodes may be provided between them. On this occasion,
The same signal is applied to each gate electrode. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-state current can be further reduced, and a stable switching element can be obtained.

In the liquid crystal device of this embodiment, in particular, the data lines 6 a and the scanning lines 3 b are provided on the TFT array substrate 10 so as to intersect three-dimensionally via the second interlayer insulating film 4. The barrier layer 80a is formed of the semiconductor layer 1a
And the pixel electrode 9a, and electrically connects the high-concentration drain region 1e and the pixel electrode 9a via the contact holes 8a and 8b. For this reason, the diameter of each of the contact holes 8a and 8b can be reduced as compared with the case where one contact hole is opened from the pixel electrode 9a to the drain region. That is, when one contact hole is opened, if the selectivity at the time of etching is low, the etching accuracy decreases as the contact hole is opened deeper.
In order to prevent punch-through in a very thin semiconductor layer 1a of about 0 nm, dry etching capable of reducing the diameter of a contact hole is stopped halfway, and finally a hole is formed in the semiconductor layer 1a by wet etching. Must be put together. Alternatively, it becomes necessary to separately provide a polysilicon film for preventing penetration through dry etching. On the other hand, in the present embodiment, the pixel electrode 9a and the high-concentration drain region 1e are connected to two serial contact holes 8a and 8b.
These contact holes 8 can be used for connection.
a and the contact hole 8b can be respectively opened by dry etching. Alternatively, it is possible to shorten at least the distance for opening by wet etching. However, in order to slightly taper each of the contact hole 8a and the contact hole 8b, a relatively short wet etching may be performed after the dry etching.

As described above, according to the present embodiment, the diameters of the contact hole 8a and the contact hole 8b can be reduced, and the barrier layer 80 in the contact hole 8a can be reduced.
Since the depressions and irregularities formed on the surface of a can be small,
The flattening of the portion of the pixel electrode 9a located thereabove is promoted. Further, since the depressions and irregularities formed on the surface of the pixel electrode 9a in the contact hole 8b can be small, flattening of the pixel electrode 9a is promoted.

As shown in FIGS. 4 and 5, a terminal area which is a part of a peripheral area located around the image display area includes:
The input / output terminals are constituted by the terminal conductive layer 80s formed of the same film as the barrier layer 80a in the pixel portion. More specifically, the base insulating film 12, the insulating thin film 2, and the first interlayer insulating film 81 in the pixel portion shown in FIGS. 2 and 3 are also formed as they are in this terminal region. On the film 81, it is formed from the same film as the barrier layer 80a,
The terminal conductive layer 80s having an island shape in plan view is formed. The second interlayer insulating film 4 is formed on the terminal conductive layer 80s, and is electrically connected to the terminal conductive layer 80s via the plurality of contact holes 5s on the second interlayer insulating film 4. , The same film as the data line 6a (ie, Al film)
Is formed. Further, a third interlayer insulating film 7 is formed on the signal wiring 6s. The second interlayer insulating film 4 and the third interlayer insulating film 7 are each provided with a terminal opening (simply referred to as a window) 8s whose planar shape is slightly smaller than the terminal conductive layer 80s. The terminal conductive layer 80s is exposed as a connection surface of the input / output terminal in the window 8s. The input / output terminals are, for example, external circuit connection terminals connected to an external circuit, upper and lower conduction terminals for supplying a common potential to an opposing substrate disposed opposite to the substrate, and inspect the electro-optical device. And various terminals such as inspection terminals. Further, the input / output terminal is intended to include an input terminal, an output terminal, or both input and output terminals. On the other hand,
The signal wiring 6s is, for example, a wiring that is electrically connected to the scanning line 3a or the data line 6a, a scanning line driving circuit for driving the scanning line 3a or the data line 6a, or performing an operation test, a data line driving circuit, or an inspection circuit. Includes wiring for supplying various signals such as clock signals, control signals, power supply signals, image signals, etc. to built-in peripheral circuits such as, and constant potential wiring to upper and lower conductive terminals connected to the opposite substrate. , Are electrically connected to external circuits and the like via the input / output terminals.

Therefore, in the process of manufacturing the liquid crystal device of the present embodiment, the barrier layer 80a in the image display area
Of the terminal conductive layer 80 in the terminal region at the same time as the step of forming
The formation process of s can be performed. Furthermore, since the contact hole 5s in the terminal region is opened at the same time as the contact hole 5a for connecting the data line 6a in the pixel portion to the semiconductor layer 1a, a dedicated opening step is not required. Further, the window 8s is also provided with the pixel electrode 9a in the pixel portion.
Is formed at the same time as the second contact hole 8b for connecting to the barrier layer 80a. Thus, when the input / output terminal is provided by exposing the Al film of the same film as the data line 6a which has been conventionally performed, electric corrosion due to contact with the ITO film is prevented when the pixel electrode 9a is formed in the subsequent steps. The pixel electrode 9a
Since the step of opening the third interlayer insulating film 7, which has been performed after the formation, can be reduced, the manufacturing process can be simplified, the liquid crystal device can be manufactured relatively easily, and the cost is relatively low. Built as a liquid crystal device.

In this embodiment, particularly, the terminal conductive layer 80s
Is made of, for example, a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb. For this reason, the terminal conductive layer 80s is not deformed or broken by the high-temperature treatment in various steps performed after the formation of the terminal conductive layer 80s in the manufacturing process. Further, the terminal conductive layer 80 is made of a high melting point metal.
By forming s, the resistance from the connection surface of the input / output terminal to the signal wiring can be reduced.

In the present embodiment, the barrier layer 80a and the terminal conductive layer 80s are interposed between the scanning line 3a and the data line 6a, and the terminal conductive layer 80s is Also, since it is exposed as a connection surface of the input / output terminal through a window 8s opened in the third interlayer insulating film 7, the terminal conductive layer 80s and an external circuit such as an FPC are connected through the window 8s. The connection can be made by an anisotropic conductive film or the like.

(Second Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a second embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 7 is a plan view of an input / output terminal in a terminal region, and FIG.
It is CC 'sectional drawing of FIG. In the second embodiment shown in FIGS. 6 and 7, the same components as those in the first embodiment shown in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 7, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawing.

6 and 7, in the second embodiment, unlike the first embodiment, on the surface of the terminal conductive layer 80s in the window 8s, the same film as the pixel electrode 9a (that is, I
A conductive thin film 9s made of a (TO film) is formed, and is exposed as a connection surface of the input / output terminal. Other configurations are the same as those in the first embodiment.

Therefore, according to the second embodiment, the conductive thin film 9s and an external circuit such as an FPC can be connected via the window 8s by the anisotropic conductive film or the like. In particular, the conductive thin film 9s made of an ITO film and the anisotropic conductive film can be connected with extremely good adhesion. Since the conductive thin film 9s constituting the connection surface for such input / output terminals can be formed simultaneously with the step of forming the pixel electrode 9a in the pixel portion,
No special process is required, and the number of processes is not increased.

(Third Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
FIG. 9 is a plan view of an input / output terminal in a terminal region, and FIG.
It is DD 'sectional drawing of FIG. In the third embodiment shown in FIGS. 8 and 9, the same components as those in the first embodiment shown in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof will be omitted. Further, in FIG. 9, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawing.

8 and 9, in the third embodiment, unlike the first embodiment, a first light-shielding film 11a is provided below the terminal conductive layer 80s located in the window 8s in plan view.
An island-shaped light-shielding film 11s made of the same film as the above, an island-shaped semiconductor layer 1s made of the same film as the semiconductor layer 1a, and an island-shaped polysilicon film 3s made of the same film as the scanning line 3a are formed. The terminal conductive layer 80s located inside is raised corresponding to the island shape. Other configurations are the same as in the first embodiment.

Therefore, according to the third embodiment, in the window 8s, the terminal conductive layer 8 forming the surface for connecting the input / output terminal is formed.
When crimping connection between 0 s and an external circuit such as an FPC by an anisotropic conductive film or the like, to prevent poor crimping due to the height of the connection surface being too lower than the height of the edge surface of the window 8 s. Can be. And such a terminal conductive layer 80s
The island-shaped light-shielding film 11s, the semiconductor layer 1s, and the polysilicon film 3s for raising the pixel into an island form
Since the light-shielding film 11a, the semiconductor layer 1a, and the scanning line 3a can be formed at the same time as the step of forming the light-shielding film 11a, a dedicated step is not required.
Does not increase the number of processes.

(Fourth Embodiment of Electro-Optical Device) The structure of a liquid crystal device which is a fourth embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
0 is a plan view of the input / output terminal in the terminal region, and FIG. 11 is a cross-sectional view taken along the line EE ′ of FIG. In the fourth embodiment shown in FIGS. 10 and 11, the same components as those in the third embodiment shown in FIGS. 8 and 9 are denoted by the same reference numerals, and description thereof will be omitted. FIG.
In the above, in order to make each layer or each member a size recognizable in the drawings, the scale of each layer or each member is made different.

In FIGS. 10 and 11, the fourth embodiment differs from the third embodiment in that the surface of the terminal conductive layer 80s in the window 8s is made of the same film as the pixel electrode 9a (ie, an ITO film). A conductive thin film 9s is formed and is exposed as a surface for connecting input / output terminals. Other configurations are the same as those of the third embodiment.

Therefore, according to the fourth embodiment, the conductive thin film 9s and an external circuit such as an FPC can be connected via the window 8s by the anisotropic conductive film or the like. In particular, the conductive thin film 9s made of an ITO film and the anisotropic conductive film can be connected with extremely good adhesion. Since the conductive thin film 9s constituting the connection surface for such input / output terminals can be formed simultaneously with the step of forming the pixel electrode 9a in the pixel portion,
No special process is required, and the number of processes is not increased.

In the first to fourth embodiments described above,
Since the barrier layer 80a is made of a high-melting point metal film, the selectivity in the etching of the metal film and the interlayer insulating film is greatly different, so that there is almost no possibility that the barrier layer 80a penetrates by dry etching during the manufacturing process. . Further, the high-temperature treatment performed after the barrier layer 80a forming step can prevent the barrier layer 80a from being broken or melted. Similarly, in the terminal region, there is almost no possibility of the terminal conductive layer 80s penetrating, and the terminal conductive layer 80s can be prevented from being broken or melted. In addition, such a high melting point metal and I
Since the compatibility with the TO film is good, good contact can be obtained between the barrier layer 80a and the pixel electrode 9a via the contact hole 8b. Similarly, in the terminal region, good contact can be obtained between the terminal conductive layer 80s and the conductive thin film 9s. Further, the barrier layer 80a and the terminal conductive layer 80s
Is preferably, for example, about 50 nm or more and 500 nm or less. If the thickness is about 50 nm, the possibility that the contact hole 8b or the window 8s is pierced during the manufacturing process is reduced, and if the thickness is about 500 nm, the unevenness of the surface of the pixel electrode 9a does not matter or is relatively easy. This is because flattening is possible. Similarly, the likelihood of penetration when the window 8s is opened is reduced, and the depth of the window 8s does not cause poor pressure bonding or raises no problem if it is raised in an island shape.

However, the barrier layer 80a and the terminal conductive layer 80s may be made of, for example, a conductive low-resistance polysilicon film doped with phosphorus or the like, instead of the high-melting-point metal film. With this configuration, the barrier layer 80
a does not function as a light shielding film,
The function of increasing 0 and the inherent relay function of the barrier layer can be sufficiently exhibited. Further, since stress due to heat or the like hardly occurs between the second interlayer insulating film 4 and the second interlayer insulating film 4, the barrier layer 80a
And to help prevent cracks in and around it. At the same time, in the terminal region, the terminal conductive layer 80s can sufficiently function as an input / output terminal, and serves to prevent cracks in the terminal conductive layer 80s and its periphery.

(Fifth Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a fifth embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in an image display area. FIG. It is. FIG. 14 is a plan view of the input / output terminals in the terminal region, and FIG. 15 is a cross-sectional view taken along line GG ′ of FIG. In the fifth embodiment shown in FIGS. 12 to 15, the same components as those in the first embodiment shown in FIGS. 2 to 5 are denoted by the same reference numerals, and the description thereof will be omitted. In FIGS. 13 and 15, the scale of each layer and each member is different in order to make each layer and each member a size recognizable in the drawings.

First, as for the pixel portion, FIG. 12 and FIG.
3, in the fifth embodiment, instead of the barrier layer 80a in the first embodiment, the semiconductor layer 1a is connected to the high-concentration drain region 1e of the semiconductor layer 1a via a contact hole 88a and is formed of the same layer as the data line 6a. Relay conductive layer 6
b, and a barrier layer 90a connected to the pixel electrode 9a via a contact hole 88b. The relay conductive layer 6b and the barrier layer 90a are opposed to each other via the data line 6a and the second interlayer insulating film 4 formed on the relay conductive layer 6b. They are electrically connected to each other via a contact hole 88c. Regarding the configuration related to other pixel units,
This is the same as in the embodiment.

Next, regarding the terminal portion, FIG. 14 and FIG.
5, the fifth embodiment includes a terminal conductive layer 90s formed of the same film as the barrier layer 90a, instead of the terminal conductive layer 80s in the first embodiment. The signal wiring 6s and the terminal conductive layer 90s are opposed to each other with the second interlayer insulating film 4 interposed therebetween, and are electrically connected to each other through a contact hole 88t opened in the second interlayer insulating film 4. Connected. Then, the terminal conductive layer 90
s is exposed as a connection surface from a window 88 s opened in the third interlayer insulating film 7. The other configuration related to the terminal portion is the same as that of the first embodiment.

In the fifth embodiment, as the material of the barrier layer 90a and the terminal conductive layer 90s, the same material as the barrier layer 80a in the first embodiment is suitably used. In particular, the pixel electrode 9a is made of an ITO film and the data line 6a is made of Al.
When the barrier layer 90a is formed of a film, it is preferable that the barrier layer 90a be made of a high melting point metal such as Ti or Cr that is compatible with both.

Therefore, according to the fifth embodiment, in the pixel portion, the pixel electrode 9a and the high-concentration drain region 1e can be electrically connected via the relay conductive layer 6b and the barrier layer 90a. Further, the storage capacitance can be increased by the structure in which the capacitance line 3b and the relay conductive layer 6b are arranged to face each other via the first interlayer insulating film 81. Furthermore,
The position of the contact hole 88a can be set at an arbitrary position in a plane region where the data line 6a does not exist, and the position of the contact hole 88b can be set at an arbitrary position on the second interlayer insulating film 4, so that the degree of design freedom is increased. It is more advantageous.

Further, according to the fifth embodiment, the step of forming the terminal conductive layer 90s in the terminal area can be performed simultaneously with the step of forming the barrier layer 90a in the image display area. Further, since the contact hole 88t in the terminal region is opened at the same time as the contact hole 88c for interconnecting the relay conductive layer 6b and the barrier layer 90a in the pixel portion, a dedicated opening step is not required. Furthermore, window 8
8s is also opened simultaneously with the contact hole 88b for connecting the pixel electrode 9a in the pixel portion to the barrier layer 90a, so that a dedicated opening step is not required.
As described above, according to the present embodiment, a part of the dedicated process for forming the input / output terminals shown in FIGS. 14 and 15 can be reduced, so that the manufacturing process can be simplified, It can be easily manufactured and constructed as a relatively low cost liquid crystal device.

(Sixth Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a sixth embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
6 is a plan view of the input / output terminal in the terminal region, and FIG. 17 is a cross-sectional view taken along line HH ′ of FIG. 14 and FIG. 1 in the sixth embodiment shown in FIG. 16 and FIG.
For the same components as the fifth embodiment shown in FIG. 5,
The same reference numerals are given and the description is omitted. In FIG. 17, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawing.

16 and 17, unlike the fifth embodiment, the sixth embodiment differs from the fifth embodiment in that the surface of the terminal conductive layer 90s in the window 88s is made of the same film as the pixel electrode 9a (ie, an ITO film). The conductive thin film 9s is formed and is exposed as a surface for connection of input / output terminals. Other configurations are the same as those in the fifth embodiment.

Therefore, according to the sixth embodiment, the window 88s
The conductive thin film 9 s and an external circuit such as an FPC can be connected via an anisotropic conductive film or the like via the interface. In particular, the conductive thin film 9s made of an ITO film and the anisotropic conductive film can be connected with extremely good adhesion. Since the conductive thin film 9s constituting the connection surface of the input / output terminals can be formed simultaneously with the step of forming the pixel electrode 9a in the pixel portion, a dedicated step is not required, and the number of steps is increased. No

(Seventh Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is a seventh embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
8 is a plan view of the input / output terminal in the terminal region, and FIG. 19 is a cross-sectional view taken along the line II ′ of FIG. 14 and FIG. 1 in the seventh embodiment shown in FIG. 18 and FIG.
For the same components as the fifth embodiment shown in FIG. 5,
The same reference numerals are given and the description is omitted. In FIG. 15, the scale of each layer and each member is different for each layer or each member in order to make the size recognizable in the drawing.

In FIGS. 18 and 19, the seventh embodiment differs from the fifth embodiment in that the first light-shielding film 11a is provided below the terminal conductive layer 90s located in the window 88s in plan view. , An island-shaped semiconductor layer 1s made of the same film as the semiconductor layer 1a, and the scanning line 3
An island-shaped polysilicon film 3s made of the same film as a is formed, and the terminal conductive layer 90s located in the window 88s is raised corresponding to the island shape. Other configurations are the same as in the fifth embodiment.

Therefore, according to the seventh embodiment, the window 88s
When the terminal conductive layer 90s forming the connection surface of the input / output terminal and the external circuit such as the FPC are pressure-bonded and connected by an anisotropic conductive film or the like, the height of the connection surface is set at the edge of the window 88s. Insufficiency in pressure bonding due to too low a height of the surface can be prevented. And such a terminal conductive layer 9
Since the island-shaped light-shielding film 11s, the semiconductor layer 1s, and the polysilicon film 3s for raising 0s in an island shape can be formed simultaneously with the step of forming the first light-shielding film 11a, the semiconductor layer 1a, and the scanning line 3a in the pixel portion. Since a dedicated process is not required, the number of processes is not increased. In addition, the conductive film 6s ′ which can be formed in the same process as the signal wiring 6s in the same process may be formed in an island shape.

(Eighth Embodiment of Electro-Optical Device) The configuration of a liquid crystal device which is an eighth embodiment of the electro-optical device according to the present invention will be described with reference to FIGS. FIG.
0 is a plan view of the input / output terminal in the terminal region, and FIG. 21 is a cross-sectional view taken along the line JJ ′ of FIG.

20 and 21, in the eighth embodiment, unlike the seventh embodiment, the surface of the terminal conductive layer 90s in the window 88s is formed of the same film as the pixel electrode 9a (ie, an ITO film). The conductive thin film 9s is formed and is exposed as a surface for connection of input / output terminals. Other configurations are the same as those of the seventh embodiment.

Therefore, according to the eighth embodiment, the window 88s
The conductive thin film 9 s and an external circuit such as an FPC can be connected via an anisotropic conductive film or the like via the interface. In particular, the conductive thin film 9s made of an ITO film and the anisotropic conductive film can be connected with extremely good adhesion. Since the conductive thin film 9s constituting the connection surface of the input / output terminals can be formed simultaneously with the step of forming the pixel electrode 9a in the pixel portion, a dedicated step is not required, and the number of steps is increased. No

In the fifth to eighth embodiments described above,
The barrier layer 90a and the terminal conductive layer 90s are made of a high melting point metal film, but may be made of, for example, a conductive low-resistance polysilicon film doped with phosphorus or the like. With this configuration, since the barrier layer 90a and the terminal conductive layer 90s are less likely to generate stress due to heat or the like between the third interlayer insulating film 7 and the second interlayer insulating film 4, the barrier layer 90a and the It helps to prevent cracks around it. At the same time, in the terminal region, the terminal conductive layer 90s can sufficiently function as an input / output terminal, and serves to prevent cracks in the terminal conductive layer 90s and the periphery thereof.

(Manufacturing Process of Electro-Optical Device) Next, the manufacturing process of the liquid crystal device having the above-described configuration will be described with reference to FIGS. 22 to 25, taking the case of the first embodiment of the electro-optical device described above as an example. It will be described with reference to FIG. Particularly, as for the terminal region, an example in which a terminal portion having a relatively complicated layer structure of the fourth embodiment shown in FIGS. 10 and 11 is formed is shown as an example. That is, the input / output terminals according to the second to eighth embodiments can be manufactured by omitting any step or making a slight change in the manufacturing process of the input / output terminal portion described below. Is omitted. Here, FIG. 22 and FIG.
FIG. 4 is a process diagram showing each layer on the FT array substrate side corresponding to a cross section taken along line AA ′ of FIG. 3, showing a pixel switching TFT. FIGS. 24 and 25 show T in each step.
FIG. 11 is a process diagram showing each layer on the FT array substrate side corresponding to the EE ′ cross section shown in FIG. 10, showing an input / output terminal portion. Particularly, the steps (1) to (16) shown in FIGS. 22 and 23 and the steps (1) to (16) shown in FIGS. 24 and 25 are simultaneously performed in different regions on the same substrate. It is a process.

First, as shown in the step (1) in FIGS. 22 and 24, a T substrate such as a quartz substrate, a hard glass, or a silicon substrate is used.
An FT array substrate 10 is prepared. Here, preferably N
₂ Inert gas atmosphere such as (nitrogen) and about 900-130
Annealing is performed at a high temperature of 0 ° C., and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. In other words, T
The FT array substrate 10 is heat-treated at the same temperature or higher. Then, a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal alloy film such as a metal silicide is formed on the entire surface of the TFT array substrate 10 thus processed by sputtering to a thickness of about 100 to 500 nm. Preferably, the light-shielding film 11 having a thickness of about 200 nm is formed.
Note that an anti-reflection film such as a polysilicon film is formed on the light-shielding film 11 to reduce surface reflection, and the formed light-shielding film 11 is subjected to photolithography and etching to form a first light-shielding film 11a. To form

At the same time, as shown in step (1) of FIG.
An island-shaped light-shielding film 11s is formed in a region where the window 8s in the terminal portion is to be opened.

Further, on the first light-shielding film 11a and the island-shaped light-shielding film 11s, for example, TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl-boat) Rate) gas, T
A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, BPSG, or the like, a silicon nitride film, a silicon oxide film, or the like is formed by using MOP (tetramethyl oxyphosphate) gas or the like. The thickness of the base insulating film 12 is, for example, about 500 m to 2000 nm.

Next, as shown in step (2) of FIG. 22, a flow rate of about 400 to 60 ° C. is formed on the underlying insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C.
Low pressure CVD using 0 cc / min monosilane gas, disilane gas or the like (for example, CV with a pressure of about 20 to 40 Pa)
By D), an amorphous silicon film is formed. Thereafter, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 1
By performing the annealing treatment for 0 hour, preferably 4 to 6 hours, the amorphous silicon film is reduced to about 50 to 20 hours.
A polysilicon film is formed by solid phase growth to a thickness of 0 nm, preferably about 100 nm. As a method of solid phase growth, RTA (Rapid Thermal Anneal)
Annealing may be used, or laser annealing using an excimer laser or the like may be used. A semiconductor layer 1a is formed from the polysilicon film having undergone solid phase growth by a photolithography process, an etching process, or the like.

At the same time, as shown in step (2) of FIG.
The island-shaped semiconductor layer 1 is also formed on the base insulating film 12 in the terminal portion.
Form s.

Next, as shown in each step (3) of FIG. 22 and FIG. 24, the semiconductor layer 1a constituting the pixel switching TFT 30 and the semiconductor layer 1s of the terminal portion are reduced by about 90%.
The insulating thin film 2 is formed by performing thermal oxidation at a temperature of 0 to 1300 ° C., preferably at a temperature of about 1000 ° C. As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating thin film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 150 nm. It is about 100 nm thick. The insulating thin film 2
May have a multi-layer structure in which a silicon oxide film or a silicon nitride film is formed on a thermal silicon oxide film by a CVD apparatus or the like. With such a multilayer structure, it is possible to shorten the high-temperature thermal oxidation time, and it is possible to prevent warpage due to heat, particularly when a large substrate of about 8 inches is used.

Next, as shown in step (4) of FIG. 22 and FIG. 24, after the resist layer 500 is formed on the semiconductor layer 1a and the island-shaped semiconductor layer 1s except for the portion to be the first storage capacitor electrode 1f. For example, a dose of about 3 × 10 ¹² P ions
/ Cm ² to reduce the resistance of the first storage capacitor electrode 1f.

Next, as shown in a step (5) of FIG. 22, a polysilicon film is deposited by a low pressure CVD method or the like, and
The scanning line 3a and the capacitance line 3b are formed by subjecting the polysilicon film, which has been made to have low resistance by thermal diffusion of (phosphorus), to a photolithography step and an etching step. Scanning line 3
The thickness of the capacitor a and the capacitor line 3b is about 100 to 500 nm, preferably about 300 nm.

At the same time, as shown in step (5) of FIG.
An island-shaped polysilicon film 3s is formed in a region where the window 8s in the terminal portion is to be opened.

Next, as shown in step (6) of FIG. 22 and FIG. 24, in order to first form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a,
A group V element such as P ion is doped at a low concentration of 1 to 10 × 10 ¹³ / cm ^{2 using} a gate electrode which is a part of a as a mask. Thereby, the semiconductor layer 1 under the gate electrode
a becomes the channel region 1a '.

Next, as shown in step (7) of FIGS. 22 and 24, a part of the scanning line 3a is formed in order to form the high-concentration source region 1d and the high-concentration drain region 1e constituting the pixel switching TFT 30. After forming the resist layer 600 with a mask wider than the gate electrode, a group V element such as P is doped at a high concentration of 1 to 10 × 10 ¹⁵ / cm ² .

When the pixel switching TFT 30 is of a p-channel type, it is necessary to form a low-concentration source region 1b and a low-concentration drain region 1c and a high-concentration source region 1d and a high-concentration drain region 1e in the semiconductor layer 1a. , B or the like using a group III element dopant.

Next, as shown in step (8) of FIGS. 22 and 24, the TF is formed by a normal pressure CVD method, a plasma CVD method, or the like.
On the entire surface of the T array substrate 10, a first interlayer insulating film 81 made of a silicon oxide film or a silicon nitride film is formed.
By forming the first interlayer insulating film 81 as thin as about 10 nm to 200 nm, the pixel switching TFT is formed.
The 30 second storage capacitors 70b can be increased.

Next, as shown in step (9) of FIG. 22, a contact hole 8a for electrically connecting the barrier layer 80a and the high-concentration drain region 1e is formed by reactive ion etching, reactive ion beam etching, or the like. Are formed in the insulating thin film 2 and the first interlayer insulating film 81 by dry etching. Since such dry etching has high directivity, a contact hole 8a having a small diameter can be formed. Alternatively, wet etching which is advantageous for preventing the contact hole 8a from penetrating the semiconductor layer 1a may be used together. Since the contact hole 8a can be formed into a tapered shape by this wet etching, connection failure due to disconnection of the barrier layer 80a can be suppressed.

Next, as shown in step (10) of FIG.
The entire surface of the high-concentration drain region 1e viewed through the insulating thin film 2, the first interlayer insulating film 81 and the contact hole 8a is covered with T
After depositing a metal such as i, Cr, W, Ta, Mo, and Pb, or a metal alloy film such as a metal silicide by sputtering, a barrier layer 80a including a third storage capacitor electrode is formed by photolithography and etching. . still,
An anti-reflection film such as a polysilicon film may be formed on the barrier layer 80a to reduce surface reflection.

At the same time, as shown in step (10) of FIG. 25, an island-shaped terminal conductive layer 80s is formed from the region where the window 8s is to be opened in the terminal portion to the region where the signal wiring is formed. .

Next, as shown in each step (11) of FIG. 23 and FIG. 25, the NSG, PSG, A second interlayer insulating film 4 made of a silicate glass film such as BSG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. Second interlayer insulating film 4
Is preferably about 500 to 1500 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the data line 6
a and the parasitic capacitance between the scanning lines 3a is not so much or little of a problem.

Next, as shown in step (12) of FIG.
A contact hole 5a for electrically connecting the data line 6a to the high-concentration source region 1d of the semiconductor layer is formed by dry etching such as reactive ion etching or reactive ion beam etching. A hole is formed in the two-layer insulating film 4. Since such dry etching has high directivity, it is possible to open a small diameter contact hole 5a. The contact hole 5a may be tapered by performing wet etching for a short time. Thereby, disconnection of the data line 6a can be prevented.

At the same time, as shown in step (12) of FIG. 25, the terminal conductive layer 80s and the signal wiring 6
contact hole 5s for electrically connecting
A hole is formed in the interlayer insulating film 4.

Next, as shown in step (13) of FIG.
The data line 6a is formed from a conductive metal film such as Al by a sputtering method or the like.

At the same time, as shown in step (13) of FIG. 25, a signal wiring 6s is formed.

Next, as shown in each step (14) of FIG. 23 and FIG. 25, the NSG, PSG, A third interlayer insulating film 7 made of a silicate glass film such as BSG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. Third interlayer insulating film 7
Is preferably about 500 to 2000 nm. If the thickness of the second interlayer insulating film 4 is 500 nm or more, the data line 6
The parasitic capacitance between the pixel electrode a and the pixel electrode 9a has little or no problem.

Next, as shown in step (15) of FIG.
A contact hole 8b for electrically connecting the pixel electrode 9a and the barrier layer 80a is formed in the third interlayer insulating film 7 by dry etching such as reactive ion etching or reactive ion beam etching. Since such dry etching has high directivity, a contact hole 8b having a small diameter can be formed. The contact hole 8b may be tapered by performing wet etching for a short time. This can prevent poor connection of the pixel electrode 9a.

At the same time, as shown in step (15) of FIG. 25, a window 8s is formed in the terminal portion to expose the surface of the terminal conductive layer 80s.

Next, as shown in step (16) of FIG.
The pixel electrode 9a is formed of a transparent conductive film such as ITO.
The pixel electrode 9a is about 10 to 10 due to Newton's ring.
It is good to deposit to a thickness of about 200 nm. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

At the same time, as shown in step (16) of FIG. 25, a conductive thin film 9s is formed in the terminal portion so as to cover the exposed terminal conductive layer 80s. Thereby, AC
An ITO film having good adhesion to F can be used as a terminal material.

As described above, according to the manufacturing process of this embodiment, each of the steps (1) to (16) in the pixel portion is performed.
And the respective steps (1) to (16) in the terminal portion can be performed simultaneously. That is, it is possible to reduce the dedicated process for removing the interlayer insulating film on the input / output terminal after the pixel electrode 9a is formed, which is conventionally performed. Further, TF in the above-described manufacturing process
In parallel with the element forming process of T30, an n-channel TFT
And peripheral circuits such as a data line driving circuit and a scanning line driving circuit having a complementary structure composed of
It may be formed in a peripheral portion on the FT array substrate 10. As described above, in this embodiment, the pixel switching TFT
If the semiconductor layer 1a constituting the pixel 30 is formed of a polysilicon film, a peripheral circuit can be formed in substantially the same process when the pixel switching TFT 30 is formed, which is advantageous in manufacturing.

When the semiconductor layer 1a and the pixel electrode 9a are connected by the relay conductive layer 6b and the barrier layer 90a as in the fifth to eighth embodiments, the relay conductive layer 6b formed of the same film as the data line 6a is used. For example, in step (12) of the above-described manufacturing process, the contact hole 88a reaching the high-concentration drain region 1e may be opened, and the relay conductive layer 6b may be formed in step (13). Further, the second interlayer insulating film 4 and the barrier layer 90a may be formed on the data line 6a and the relay conductive layer 6b by a process similar to the processes (8) to (10) in the first embodiment. That is, also in the case of manufacturing the fifth to eighth embodiments, it is possible to reduce the dedicated process for removing the interlayer insulating film on the input / output terminal after the pixel electrode 9a is formed, which is conventionally performed.

In the above-described manufacturing process, a process for planarizing the surface of the third interlayer insulating film 7 on which the pixel electrode is formed is not performed. Finally, the underlying layers of the pixel electrode 9a and the alignment film 16 may be finally flattened by performing a flattening process. Such a planarization process is performed, for example, in a step of forming the third interlayer insulating film 7 by a CMP (Chemical Mechanical Polishing) process.
shing), spin coating, reflow method, etc., organic SOG (Spin On Glass), inorganic SOG,
It may be performed using a polyimide film or the like. Alternatively, a concave groove may be formed in the TFT array substrate 10 or each interlayer insulating film in a region where wirings and elements are formed.

(Overall Configuration of Electro-Optical Device) The overall configuration of the liquid crystal device in each embodiment configured as described above will be described with reference to FIGS. 26 and 27. Incidentally, FIG.
FIG. 27 is a plan view of the FT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side.
FIG. 27 is a sectional view taken along the line KK ′ of FIG. 26.

In FIG. 26, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 102 are provided on one side of the TFT array substrate 10. The scanning line driving circuit 1 is provided along the scanning line and drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing.
04 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area.
For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines are arranged along the opposite side of the image display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. In at least one of the corners of the counter substrate 20, upper and lower conductive terminals 106 having a conductive material for establishing electrical continuity between the TFT array substrate 10 and the counter substrate 20 are provided. Then, as shown in FIG. 27, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is fixed to the array substrate 10. Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, and the like, a sampling circuit 103 for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of data Forming a precharge circuit for supplying a precharge signal of a predetermined voltage level to the line 6a prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or shipping. Is also good.
According to the present embodiment, the second light shielding film 23 on the counter substrate 20 may be formed smaller than the light shielding area of the TFT array substrate 10. Further, the second light shielding film 23 can be easily removed depending on the use of the liquid crystal device.

In FIGS. 26 and 27, the input / output terminals in each of the above-described embodiments are suitably used for the external circuit connection terminal 102 and the upper / lower conduction terminal 106.

In each of the embodiments described above with reference to FIGS. 1 to 27, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, TN (Twisted) is provided on each of the side of the opposite substrate 20 on which the projected light is incident and the side of the TFT array substrate 10 on which the emitted light is emitted.
Nematic) mode, VA (Vertically Aligned) mode,
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a PDLC (Polymer Dispersed Liquid Crystal) mode or a normally white mode / a normally black mode.

Since the liquid crystal device in each of the embodiments described above is applied to a color liquid crystal projector, three liquid crystal devices are used as light valves for R (red), G (green), and B (blue), respectively. Light of each color separated through the dichroic mirror for RGB color separation is incident on each panel as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film. Alternatively, R on the TFT array substrate 10
It is also possible to form a color filter layer with a color resist or the like below the pixel electrode 9a facing the GB. In this way, the liquid crystal device in each embodiment can be applied to a color liquid crystal device such as a direct-view or reflection type color liquid crystal television other than the liquid crystal projector. Further, 1
A micro lens may be formed so as to correspond to one pixel. In this case, a bright liquid crystal device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color liquid crystal device can be realized.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
Embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area in a liquid crystal device according to a first embodiment of the electro-optical device.

FIG. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the liquid crystal device according to the first embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a plan view of each terminal portion formed in a terminal region in the liquid crystal device according to the first embodiment.

FIG. 5 is a sectional view taken along line B-B 'of FIG.

FIG. 6 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a second embodiment.

FIG. 7 is a sectional view taken along line C-C 'of FIG.

FIG. 8 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a third embodiment.

FIG. 9 is a sectional view taken along line D-D 'of FIG.

FIG. 10 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a fourth embodiment.

11 is a sectional view taken along line E-E 'of FIG.

FIG. 12 is a view illustrating a T in which a data line, a scanning line, a pixel electrode, and the like are formed in a liquid crystal device according to a fifth embodiment of the electro-optical device.
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the FT array substrate.

13 is a sectional view taken along the line F-F 'of FIG.

FIG. 14 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a fifth embodiment.

FIG. 15 is a sectional view taken along line G-G ′ of FIG. 14;

FIG. 16 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a sixth embodiment.

17 is a sectional view taken along the line H-H 'of FIG.

FIG. 18 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to a seventh embodiment.

19 is a sectional view taken along the line I-I 'of FIG.

FIG. 20 is a plan view of each terminal portion formed in a terminal region in a liquid crystal device according to an eighth embodiment.

21 is a sectional view taken along the line J-J 'of FIG.

FIG. 22 is a process diagram (part 1) illustrating each step of the image display area in the embodiment of the manufacturing process of the liquid crystal device in order.

FIG. 23 is a process diagram (part 2) illustrating each step of the image display region in the embodiment of the manufacturing process of the liquid crystal device in order.

FIG. 24 is a process diagram (part 1) for sequentially illustrating each step of a terminal region in the embodiment of the manufacturing process of the liquid crystal device.

FIG. 25 is a process diagram (part 2) illustrating each step of the terminal region in the embodiment of the manufacturing process of the liquid crystal device in order.

FIG. 26 is a plan view of the TFT array substrate in the liquid crystal device of each embodiment together with the components formed thereon as viewed from the counter substrate side.

FIG. 27 is a sectional view taken along line K-K ′ of FIG. 26;

[Explanation of symbols]

 1a semiconductor layer 1a 'channel region 1b low concentration source region (source side LDD region) 1c low concentration drain region (drain side LDD region) 1d high concentration source region 1e high concentration drain region 1f first accumulation Capacitance electrode 2 ... Insulating thin film 3a ... Scan line 3b ... Capacitance line (second storage capacitor electrode) 3s ... Polysilicon film 4 ... Second interlayer insulating film 5a ... Contact hole 6a ... Data line 6s ... Signal wiring 7 ... Third interlayer Insulating film 8a Contact hole 8b Contact hole 8s Window 9a Pixel electrode 9s Conductive thin film 10 TFT array substrate 11a First light-shielding film 12 Base insulating film 16 Alignment film 20 Counter substrate 21 Counter electrode Reference Signs List 22 alignment film 23 second light-shielding film 30 pixel switching TFT 50 liquid crystal layer 52 sealing material 53 third light-shielding film 70 accumulation The amount 70a ... first storage capacitor 70b ... second storage capacitor 80a ... barrier layer 80s ... conductive layer 81: first interlayer insulating film terminal

Continued on the front page F-term (reference) 2H092 GA59 HA25 JA25 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB54 JB58 JB63 JB69 JB77 KA04 KA07 KA16 KA18 KB14 KB23 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA22 MA27 NA25 NA27 NA29 PA06 PA08 QA07 QA15 QA18 RA05 5C058 EA26 5F110 AA18 BB01 CC02 DD02 DD03 DD05 DD12 DD25 EE09 EE28 FF02 FF03 FF09 FF23 FF29 GG02 NN13 NN24 NN03 NN03 NN24 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN03 NN45 NN46 NN72 PP02 PP03 PP10 QQ03 QQ11 QQ19 QQ30

Claims (14)

[Claims] A plurality of pixel electrodes; a plurality of scanning lines and a plurality of data lines; a thin film transistor connected to each of the scanning lines and each of the data lines; A first conductive layer interposed between the semiconductor layer and the pixel electrode, electrically connected to the semiconductor layer on the one hand, and electrically connected to the pixel electrode on the other hand, The electro-optical device according to claim 1, wherein a part of the terminal located around the image display area is formed of a second conductive layer made of the same film as the first conductive layer. 2. The terminal includes an external circuit connection terminal connected to an external circuit, an upper / lower conduction terminal for supplying a common potential to an opposing substrate disposed opposite to the substrate, and an inspection of the electro-optical device. 2. The electro-optical device according to claim 1, comprising at least one of the inspection terminals. 3. The electro-optical device according to claim 1, wherein the second conductive layer is connected to one end of a signal wiring formed of the same film as the data line to form the terminal. apparatus. 4. The first conductive layer and the second conductive layer,
The electro-optical device according to claim 1, wherein the electro-optical device is provided between the scanning line and the data line. 5. The first conductive layer and the second conductive layer,
The electro-optical device according to claim 1, wherein the electro-optical device is interposed between an interlayer between the data line and the pixel electrode. 6. The terminal opening formed in the interlayer insulating film, further comprising an interlayer insulating film interposed between the second conductive layer and the pixel electrode. The electro-optical device according to any one of claims 1 to 5, comprising: 7. An inter-layer insulating film interposed between the second conductive layer and the pixel electrode; and an opening for the terminal formed in the inter-layer insulating film, on the second conductive layer. 6. The device according to claim 1, further comprising: a conductive thin film formed of the same film as the pixel electrode and exposed as a connection surface of the terminal.
The electro-optical device according to any one of the above. 8. At least one of the second conductive layer portions located in the terminal opening portion when viewed in a plan view, on the side of the substrate, between the second conductive layer and the substrate. 8. The electric device according to claim 6, wherein the first conductive layer is formed in an island shape, and the second conductive layer located in the terminal opening is raised corresponding to the island shape. 9. Optical device. 9. The first conductive layer and the second conductive layer,
The electro-optical device according to any one of claims 1 to 8, further comprising a high melting point metal. 10. A step of forming a semiconductor layer of a thin film transistor in an image display area on a substrate; a step of forming an insulating thin film on the semiconductor layer; and forming a scanning line including a gate electrode on the insulating thin film. A step of forming a first interlayer insulating film on the scanning line; a step of forming a first contact hole in the insulating thin film and the first interlayer insulating film that communicates with each of the semiconductor layers; Forming a first conductive layer on the insulating film so as to be electrically connected to the semiconductor layer through the first contact hole, and at least partially forming a terminal around the image display region on the substrate; Constituting the second
Forming a conductive layer from the same film as the first conductive layer; forming a second interlayer insulating film on the first conductive layer and the second conductive layer; and forming data on the second interlayer insulating film. Forming a third interlayer insulating film on the data line; forming a first interlayer insulating film on the first interlayer insulating film and the second interlayer insulating film on the second interlayer insulating film;
Forming a second contact hole leading to the conductive layer, and simultaneously forming the terminal opening portion leading to the second conductive layer; and electrically connecting to the first conductive layer via the second contact hole. Forming a pixel electrode as described above. 11. A step of forming a semiconductor layer of a thin film transistor in an image display region on a substrate, a step of forming an insulating thin film on the semiconductor layer, and forming a scanning line including a gate electrode on the insulating thin film. Forming a first interlayer insulating film on the scanning line; forming a first contact hole in the insulating thin film and the first interlayer insulating film, which leads to the semiconductor layer; Forming a data line in a predetermined region on the film and simultaneously forming a relay conductive layer so as to be electrically connected to the semiconductor layer via the first contact hole from the same film as the data line; Forming a second interlayer insulating film on the relay conductive layer; forming a second contact hole communicating with the relay conductive layer in the second interlayer insulating film; A first conductive layer is formed on the insulating film so as to be electrically connected to the relay conductive layer via the second contact hole, and at least a terminal is provided around the image display area on the substrate. Forming a partially formed second conductive layer with the same film as the first conductive layer; forming a third interlayer insulating film on the first conductive layer and the second conductive layer; Forming a third contact hole communicating with the first conductive layer in the three-layer insulating film, and simultaneously opening the terminal hole communicating with the second conductive layer; and via the third contact hole Forming a pixel electrode so as to be electrically connected to the first conductive layer. 12. The electro-optical device according to claim 10, wherein, in the step of forming the data line, a signal wire having one end connected to the terminal is formed from the same film as the data line. Manufacturing method. 13. In the step of forming the data line, a signal line having one end connected to the terminal is formed from the same film as the data line, and the data line is connected to the data line before the step of forming the data line. 11. The electro-optical device according to claim 10, further comprising the step of opening a contact hole for connecting one end of the signal wiring to the terminal at the same time as opening a contact hole for connecting to a semiconductor layer. Device manufacturing method. 14. The method according to claim 10, wherein in the step of forming the pixel electrode, a conductive thin film made of the same film as the pixel electrode is formed in the terminal opening. 3. The method for manufacturing an electro-optical device according to claim 1.