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JP2000183474A - Metal insulating substrate for power semiconductor device and method of manufacturing the same - Google Patents

Metal insulating substrate for power semiconductor device and method of manufacturing the same

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Publication number
JP2000183474A
JP2000183474A JP10360147A JP36014798A JP2000183474A JP 2000183474 A JP2000183474 A JP 2000183474A JP 10360147 A JP10360147 A JP 10360147A JP 36014798 A JP36014798 A JP 36014798A JP 2000183474 A JP2000183474 A JP 2000183474A
Authority
JP
Japan
Prior art keywords
insulating layer
circuit conductor
metal
insulating
power circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10360147A
Other languages
Japanese (ja)
Other versions
JP3879291B2 (en
Inventor
Shoji Yamada
昭治 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP36014798A priority Critical patent/JP3879291B2/en
Publication of JP2000183474A publication Critical patent/JP2000183474A/en
Application granted granted Critical
Publication of JP3879291B2 publication Critical patent/JP3879291B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】パワー回路に板厚の厚い導体を採用した場合で
も高い放熱性を確保できるようにパワー半導体デバイス
用の金属絶縁基板を改良する。 【解決手段】金属ベース1の上に絶縁層2,およびパワ
ー回路導体3を積層したパワー半導体デバイス用の金属
絶縁基板において、前記パワー回路導体3を、その上面
を露呈して絶縁層2に埋め込み積層して構成するものと
し、その製造方法として金属ベース1の表面全域に絶縁
層2をプリプレグ状態で積層した上で、前記絶縁層の上
にパワー回路導体を重ね、次いで真空加圧プレスなどに
より加圧力を加えて回路導体3を絶縁層3に埋め込むと
ともに、絶縁層2を硬化させて組立てる。
[PROBLEMS] To improve a metal insulating substrate for a power semiconductor device so that high heat dissipation can be ensured even when a thick conductor is used for a power circuit. In a metal insulating substrate for a power semiconductor device in which an insulating layer and a power circuit conductor are laminated on a metal base, the power circuit conductor is embedded in the insulating layer with its upper surface exposed. As a manufacturing method, an insulating layer 2 is laminated in a prepreg state over the entire surface of the metal base 1, and a power circuit conductor is stacked on the insulating layer, and then a vacuum pressure press or the like is used. The circuit conductor 3 is embedded in the insulating layer 3 by applying a pressing force, and the insulating layer 2 is cured and assembled.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電動機を制御する
インバータ装置などのパワー半導体デバイスに適用する
金属絶縁基板,およびその製造方法に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to a metal insulating substrate applied to a power semiconductor device such as an inverter device for controlling an electric motor, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】頭記したパワー半導体デバイスは、回路
基板に形成した導体パターンにパワー半導体素子,その
他の電子部品(図示せず)を実装した構成になり、その
回路基板の種類の一つに金属絶縁基板がある。この金属
絶縁基板は、図3に示すように金属ベース(銅板)1の
上に熱伝導率を高めたフィラーエポシキ樹脂(エポシキ
樹脂にアルミナなどの粉末を混在させたもの)などの絶
縁層2を積層し、その上に回路導体3をパターン形成し
た構成であり、従来の金属絶縁基板では、回路導体3が
フォトプロセスによる無電解銅メッキ,あるいは銅箔エ
ッチング法などにより形成される。
2. Description of the Related Art The power semiconductor device described above has a configuration in which a power semiconductor element and other electronic components (not shown) are mounted on a conductor pattern formed on a circuit board. There is a metal insulating substrate. As shown in FIG. 3, this metal insulating substrate is provided with an insulating layer 2 such as a filler epoxy resin (a mixture of an epoxy resin and a powder such as alumina) having enhanced thermal conductivity on a metal base (copper plate) 1 as shown in FIG. The circuit conductor 3 is formed by laminating and patterning the circuit conductor 3 thereon. In a conventional metal insulating substrate, the circuit conductor 3 is formed by electroless copper plating by a photo process or a copper foil etching method.

【0003】この場合に、通電電流が大きいパワー半導
体デバイスでは、通電抵抗を低く押さえるために回路導
体の導体断面積を大きくとる必要があるが、限られた回
路基板の面積で回路をパターン形成するにはその導体幅
がむやみに大きくとることができないことから、従来の
金属絶縁基板では、基板を覆う銅箔にあらかじめ板厚の
厚い銅箔を用いて回路導体をエッチングする、あるいは
100〜140μm程度の薄い銅箔にエッチングを施し
て形成した導体パターンの上に別な銅板をはんだ付け
し、デバイスの通電容量に対応した300〜1000μ
m程度の厚さをもつパワー回路導体を形成するようにし
ている。
In this case, in a power semiconductor device having a large energizing current, it is necessary to increase the conductor cross-sectional area of the circuit conductor in order to keep the energizing resistance low. However, a circuit is formed with a limited circuit board area. In the conventional metal insulating substrate, the circuit conductor is etched using a thick copper foil in advance for the copper foil covering the substrate, or because the conductor width cannot be unnecessarily large, or about 100 to 140 μm. Another copper plate is soldered on a conductor pattern formed by etching a thin copper foil of 300 to 1000 μm corresponding to the current carrying capacity of the device.
A power circuit conductor having a thickness of about m is formed.

【0004】[0004]

【発明が解決しようとする課題】ところで、前記のよう
に絶縁層の上に板厚の厚い回路導体をパターン形成した
従来の金属絶縁基板(図3参照)では、基板に実装した
パワー半導体素子,および回路導体自身の放熱性が低下
するようになるといった問題が派生する。
By the way, in the conventional metal insulating substrate (see FIG. 3) in which a thick circuit conductor is patterned on the insulating layer as described above, a power semiconductor element mounted on the substrate is used. In addition, the heat dissipation of the circuit conductor itself is reduced.

【0005】すなわち、通電に伴うパワー半導体素子の
発生熱は、その大半が該素子をマウントした回路導体3
に伝熱し、さらに絶縁層2,金属ベース1を伝熱してヒ
ートシンク(図示せず)に放熱する。また、回路導体3
の発生熱は絶縁層2を介して金属ベース1に伝熱する。
この場合に、板厚の厚い回路導体3はその下面が比較的
伝熱性の高いフィラーエポシキ樹脂などの絶縁層2に接
しているが、回路導体の左右側面は絶縁層2に接してな
く露呈したままで放熱面として有効に機能してない。な
お、パワーデバイスでは、回路基板に半導体素子などを
実装した後、パッケージ内にシリコーンゲル,エポシキ
樹脂などを充填して電子部品を樹脂封止するようにして
いるが、前記封止樹脂の熱伝導率は低く熱放散には殆ど
寄与しない。
[0005] That is, most of the heat generated by the power semiconductor element due to energization is generated by the circuit conductor 3 on which the element is mounted.
To the insulating layer 2 and the metal base 1 to radiate heat to a heat sink (not shown). The circuit conductor 3
Is transferred to the metal base 1 via the insulating layer 2.
In this case, the thick circuit conductor 3 has its lower surface in contact with the insulating layer 2 such as a filler epoxy resin having relatively high heat conductivity, but the left and right side surfaces of the circuit conductor are exposed without being in contact with the insulating layer 2. As it is, it does not function effectively as a heat dissipation surface. In a power device, after a semiconductor element or the like is mounted on a circuit board, the package is filled with a silicone gel, epoxy resin, or the like, and the electronic component is sealed with a resin. The rate is low and contributes little to heat dissipation.

【0006】なお、前記封止樹脂にフィラー樹脂などの
高熱伝導率の材料を用いて半導体素子の放熱性を高める
ことも考えられるが、封止樹脂に熱伝導率の高い材料を
採用するとコスト高となる。
It is conceivable to improve the heat dissipation of the semiconductor element by using a material having a high thermal conductivity such as a filler resin for the sealing resin. However, if a material having a high thermal conductivity is used for the sealing resin, the cost increases. Becomes

【0007】本発明は上記の点に鑑みなされたものであ
り、その目的は前記課題を解決し、板厚が厚い回路導体
を採用した場合でも高い放熱性を確保できるように改良
したパワー半導体デバイス用の金属絶縁基板,およびそ
の製造方法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object to solve the above-mentioned problems and to improve the power semiconductor device so as to ensure high heat dissipation even when a thick circuit conductor is employed. It is an object of the present invention to provide a metal insulated substrate for use and a method for manufacturing the same.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、金属ベースに絶縁層,およびパワ
ー回路導体を積層したパワー半導体デバイス用の金属絶
縁基板において、前記パワー回路導体を、その上面を露
呈して絶縁層に埋め込み積層するものとする(請求項
1)。
According to the present invention, there is provided a metal insulating substrate for a power semiconductor device in which an insulating layer and a power circuit conductor are laminated on a metal base. Are buried in an insulating layer with its upper surface exposed and laminated.

【0009】上記の構成によれば、板厚の厚いパワー回
路導体の側面が熱伝導率の高い絶縁層(フィラーエポシ
キ樹脂など)に接触していることから、この側面部分も
伝熱面として有効に寄与し、下面のみが絶縁層に接して
いる従来構造と比べて回路導体/絶縁層間の伝熱性が高
まって金属絶縁基板の放熱性が向上する。また、前記構
成においては、絶縁層を上下二層に分け、その上層の絶
縁層にパワー回路導体を埋め込み積層する(請求項2)
構成がある。
According to the above configuration, since the side surface of the thick power circuit conductor is in contact with the insulating layer having high thermal conductivity (such as filler epoxy resin), this side surface portion is also effective as a heat transfer surface. As compared with the conventional structure in which only the lower surface is in contact with the insulating layer, the heat transfer between the circuit conductor and the insulating layer is increased, and the heat dissipation of the metal insulating substrate is improved. Further, in the above configuration, the insulating layer is divided into upper and lower layers, and the power circuit conductor is buried and laminated in the upper insulating layer.
There is a configuration.

【0010】かかる構成で、下層の絶縁層を硬化させた
後に、その上に積層した上層の絶縁層にパワー回路導体
を埋め込み積層することにより、絶縁層に埋め込んだ回
路導体が金属ベースに直接接触するおそれがなく、かつ
下層の絶縁層で所定の絶縁耐力が確保できる。
With this configuration, after the lower insulating layer is cured, the power circuit conductor is buried and laminated in the upper insulating layer laminated thereon, so that the circuit conductor embedded in the insulating layer directly contacts the metal base. There is no danger of occurrence, and a predetermined dielectric strength can be ensured by the lower insulating layer.

【0011】ここで、絶縁層の上層と下層を同種の絶縁
材料で形成する(請求項3)ことにより、上層の絶縁層
と下層の絶縁層との間の接着性が良く、かつ熱膨張差も
なくて剥離し難い絶縁層が得られる。また、絶縁層の上
層と下層を異種の絶縁材料で形成すれば(請求項4)、
下層,上層の絶縁層の材料をそれぞれ金属ベース,半導
体素子,封止樹脂との接着性、並びに絶縁層の誘電率,
誘電正接などのを考慮して材料の選択,組合せが可能と
なる。
Here, by forming the upper layer and the lower layer of the insulating layer from the same kind of insulating material (claim 3), the adhesiveness between the upper insulating layer and the lower insulating layer is good and the thermal expansion difference is improved. An insulating layer which does not easily peel off is obtained. Further, if the upper layer and the lower layer of the insulating layer are formed of different insulating materials (claim 4),
The material of the lower and upper insulating layers is made of a metal base, a semiconductor element, an adhesive property with a sealing resin, a dielectric constant of the insulating layer,
Materials can be selected and combined in consideration of the dielectric loss tangent and the like.

【0012】また、板厚の厚いパワー回路導体は、銅板
などの金属板をプレス打ち抜き,もしくはワイヤカット
してパターン形成したものを採用する(請求項5)こと
により、無電解メッキ,あるいはエッチング法などに比
べて回路導体を短時間で簡単に製作できる。
The thick power circuit conductor is formed by pressing a metal plate such as a copper plate or forming a pattern by wire cutting. Circuit conductors can be manufactured in a shorter time and more easily as compared with other methods.

【0013】一方、前記構成の金属絶縁基板は、本発明
により次記方法により製造するものとする。すなわち、
絶縁層が一層である構成では、金属ベースの表面全域に
絶縁層を非硬化状態で積層した上で、前記絶縁層の上に
パワー回路導体を重ねた状態で加圧により回路導体を絶
縁層に埋め込んで絶縁層を硬化させる(請求項6)。ま
た、絶縁層を上下二層に分けた構成では、まず、金属ベ
ースの表面全域に下層の絶縁層を積層し、前記の下層絶
縁層が硬化した状態でその上面全域に上層の絶縁層を非
硬化状態で積層した上で、該上層絶縁層にパワー回路導
体を重ねた状態で加圧により回路導体を上層の絶縁層に
埋め込んで上層の絶縁層を硬化させる(請求項7)。
On the other hand, the metal insulating substrate having the above structure is manufactured by the following method according to the present invention. That is,
In the configuration in which the insulating layer is a single layer, the insulating layer is laminated on the entire surface of the metal base in an uncured state, and then the circuit conductor is turned into an insulating layer by pressing the power circuit conductor on the insulating layer. The insulating layer is buried and cured (claim 6). Further, in the configuration in which the insulating layer is divided into upper and lower layers, first, a lower insulating layer is laminated on the entire surface of the metal base, and the upper insulating layer is not formed on the entire upper surface in a state where the lower insulating layer is cured. After laminating in a cured state, the circuit conductor is embedded in the upper insulating layer by applying pressure while the power circuit conductor is superimposed on the upper insulating layer, and the upper insulating layer is cured (claim 7).

【0014】かかる製造方法を採用することにより、手
間の掛かるインサート成形法などに頼らずに、一層,な
いし二層からなる絶縁層にパワー回路導体を埋め込み積
層した本発明の金属絶縁基板を高品質,かつ能率よく製
造できる。
By adopting such a manufacturing method, the metal insulating substrate of the present invention in which the power circuit conductor is embedded and laminated in one or two insulating layers without relying on a complicated insert molding method or the like can be manufactured with high quality. , And can be manufactured efficiently.

【0015】[0015]

【発明の実施の形態】以下本発明の実施の形態を図1,
図2,および図4,図5に示す実施例に基づいて説明す
る。なお、各実施例の図中で図3に対応する同一部材に
は同じ符号を付してしその説明は省略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.
The description will be made based on the embodiment shown in FIGS. In the drawings of the respective embodiments, the same members corresponding to FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted.

【0016】〔実施例1〕図1は本発明の請求項1に対
応する実施例の構成図であり、金属ベース1,絶縁層
2,パワー回路導体3の積層体からなる金属絶縁基板に
おいて、パワー回路導体3はその上面が露呈し、下面お
よび左右側面が絶縁層2の層内に埋没するように埋め込
み積層されている。ここで、絶縁層2はアルミナなどの
粉をエポシキ樹脂に混入して熱伝導率を高めたフィラー
エポシキ樹脂などが好適である。また、パワー回路導体
3は、例えば厚さ300μmの銅板をプレス打ち抜き,
あるいはワイヤカット法により所定のパターンに形成し
たものである。
[Embodiment 1] FIG. 1 is a structural view of an embodiment according to claim 1 of the present invention. In a metal insulating substrate comprising a laminate of a metal base 1, an insulating layer 2, and a power circuit conductor 3, FIG. The power circuit conductor 3 is buried and laminated such that its upper surface is exposed and its lower surface and left and right side surfaces are buried in the insulating layer 2. Here, the insulating layer 2 is preferably made of a filler epoxy resin or the like in which a powder such as alumina is mixed into an epoxy resin to increase the thermal conductivity. The power circuit conductor 3 is formed by pressing a copper plate having a thickness of, for example, 300 μm.
Alternatively, it is formed in a predetermined pattern by a wire cutting method.

【0017】上記構成によれば、パワー回路導体3はそ
の下面のみならず、左右側面も熱伝導率の高い樹脂層2
と伝熱的に接触することになるので、図3に示した従来
構造と比べて回路導体/絶縁層間の伝熱面積が増して回
路導体3に搭載したパワー半導体素子,回路導体自身の
発熱に対する放熱性が向上する。なお、前記構成で絶縁
層2の厚さAは回路導体3の厚さBよりも大きく設定
し、回路導体3の下面と金属ベース1との間に所定の絶
縁耐力に対応した絶縁層厚さCを確保するようにしてい
る。
According to the above configuration, the power circuit conductor 3 has not only the lower surface but also the left and right side surfaces of the resin layer 2 having high thermal conductivity.
As a result, the heat transfer area between the circuit conductor / insulating layer is increased as compared with the conventional structure shown in FIG. 3 so that the power semiconductor element mounted on the circuit conductor 3 and the heat generated by the circuit conductor itself are reduced. Heat dissipation is improved. In the above configuration, the thickness A of the insulating layer 2 is set to be larger than the thickness B of the circuit conductor 3, and the thickness of the insulating layer corresponding to a predetermined dielectric strength between the lower surface of the circuit conductor 3 and the metal base 1. C is secured.

【0018】次に、図1の構成になる金属絶縁基板の製
造方法を図4(a) 〜(c) で説明する。先ず、図4(a) の
工程で金属ベース1の上面全域に粘着性が無くなるBス
テージまで硬化させたプリプレグ状態の絶縁層(シート
状の樹脂)2を被着して仮固定する。次に、図4(b) の
工程で金属ベース1に仮固定した絶縁層2の上にパワー
回路導体3を位置決めして重ね合わせ、図4(c) の工程
で真空加圧プレス4により上下から加圧力Fを加えて回
路導体3をプリプレグ状態にある絶縁層2の層内に押し
込んで埋め込み積層するとともに、この状態で熱を加え
て絶縁層2の樹脂を硬化させる。なお、この加圧,硬化
工程で真空加圧プレス4を用いることで、絶縁耐力低下
の原因となるボイドの発生なしに絶縁層2の樹脂を硬化
させることができる。
Next, a method of manufacturing the metal insulating substrate having the structure shown in FIG. 1 will be described with reference to FIGS. First, in the step of FIG. 4A, an insulating layer (sheet-like resin) 2 in a prepreg state, which has been cured to the B stage where the tackiness is eliminated, is applied to the entire upper surface of the metal base 1 and temporarily fixed. Next, the power circuit conductor 3 is positioned and superimposed on the insulating layer 2 temporarily fixed to the metal base 1 in the step of FIG. 4B, and is vertically moved by the vacuum press 4 in the step of FIG. Then, the circuit conductor 3 is pressed into the insulating layer 2 in a prepreg state by embedding and laminating the circuit conductor 3, and the resin of the insulating layer 2 is cured by applying heat in this state. By using the vacuum press 4 in this pressurizing and curing step, the resin of the insulating layer 2 can be cured without generating voids that cause a decrease in dielectric strength.

【0019】〔実施例2〕図2は本発明の請求項2に対
応する実施例の構成図であり、この実施例においては絶
縁層2が上下2層に分けて形成されており、上層の絶縁
層2aにはパワー回路導体3が埋め込み積層され、該絶
縁層2aが金属ベース1の上に積層して硬化した下層の
絶縁層2bの上に重ね合わせて積層されている。なお、
下層の絶縁層2bはそれ自身で所定の絶縁耐力を確保す
る層厚さDに設定しておくものとする。
[Embodiment 2] FIG. 2 is a structural view of an embodiment according to a second aspect of the present invention. In this embodiment, an insulating layer 2 is formed in two upper and lower layers. The power circuit conductor 3 is buried and laminated in the insulating layer 2a, and the insulating layer 2a is laminated on the lower insulating layer 2b which is laminated on the metal base 1 and cured. In addition,
The lower insulating layer 2b is set to have a layer thickness D that ensures a predetermined dielectric strength by itself.

【0020】ここで、上層の絶縁層2a,下層の絶縁層
2bは共に熱伝導率の高いフィラー樹脂であって、絶縁
層2aと2bは同じ材料とするか、あるいは別な種類の
材料を採用して実施することができる。この場合に、絶
縁層2aと2bに同一材料を用いれば、絶縁層の間で高
い接着性が得られるほか、熱膨張率差に起因する接着面
の剥離などの問題もない。一方、絶縁層2aと2bを同
一材料に限定しなければ、金属ベース1,半導体素子と
の接着性の相性,および誘電率,誘電正接などの電気的
な特性を考慮してパワーデバイスに適した絶縁材料を自
由に選択することができる。
Here, the upper insulating layer 2a and the lower insulating layer 2b are both filler resins having a high thermal conductivity, and the insulating layers 2a and 2b are made of the same material or different materials. Can be implemented. In this case, if the same material is used for the insulating layers 2a and 2b, high adhesiveness can be obtained between the insulating layers, and there is no problem such as peeling of the bonding surface due to a difference in thermal expansion coefficient. On the other hand, if the insulating layers 2a and 2b are not limited to the same material, it is suitable for a power device in consideration of the compatibility of the metal base 1, adhesiveness with a semiconductor element, and electrical characteristics such as dielectric constant and dielectric loss tangent. The insulating material can be freely selected.

【0021】次に、図2の構成になる金属絶縁基板の製
造方法を図5(a) 〜(d) で説明する。先ず、図5(a) の
工程で金属ベース1の上面全域にBステージまで硬化さ
せたプリプレグ状態にある下層の絶縁層(シート状の樹
脂)2bを被着し、真空加圧プレスなどで絶縁層2bを
硬化させる。あるいは、あらかじめ硬化させたシート状
の絶縁層2bを接着剤で金属ベース1に接合することも
可能である。次に、図5(b) の工程で硬化済の状態にあ
る絶縁層2bの上面全域にBステージまで硬化させたプ
リプレグ状態にある上層の絶縁層2aを被着して仮固定
した後、図5(c) の工程で絶縁層2aの上にパワー回路
導体3を位置決めして重ね合わせ、図5(d) の工程で真
空加圧プレス4により上下から加圧力Fを加えて回路導
体3をプリプレグ状態にある絶縁層2aの層内に押し込
んで埋め込み積層するとともに、この状態で熱を加えて
絶縁層2aの樹脂を硬化させ、上層の絶縁層2aと下層
の絶縁層2bとを一体接合する。
Next, a method of manufacturing the metal insulating substrate having the structure shown in FIG. 2 will be described with reference to FIGS. 5 (a) to 5 (d). First, a lower insulating layer (sheet-like resin) 2b in a prepreg state cured to the B stage is applied to the entire upper surface of the metal base 1 in the step of FIG. The layer 2b is cured. Alternatively, it is also possible to bond the sheet-shaped insulating layer 2b which has been cured in advance to the metal base 1 with an adhesive. Next, the upper insulating layer 2a in the prepreg state, which has been cured to the B stage, is applied over the entire upper surface of the insulating layer 2b in the cured state in the step of FIG. In step (c) of FIG. 5, the power circuit conductor 3 is positioned and superimposed on the insulating layer 2a. In step (d) of FIG. The insulating layer 2a in the prepreg state is pressed and buried and laminated, and in this state, heat is applied to cure the resin of the insulating layer 2a, and the upper insulating layer 2a and the lower insulating layer 2b are integrally joined. .

【0022】この実施例によれば、パワー回路導体3を
上層の絶縁層2aに埋め込む工程では、下層の絶縁層2
bが既に硬化状態にあるので、プレス打ち抜き加工など
で回路導体3の切断面にばり,返しなどが生じていて
も、これが埋め込み積層状態で金属ベース1に直接接触
するおそれはなく、かつ下層の絶縁層2bの層厚Dで所
定の絶縁耐力を確保できる。
According to this embodiment, in the step of embedding the power circuit conductor 3 in the upper insulating layer 2a, the lower insulating layer 2a
Since b is already in a hardened state, even if the cut surface of the circuit conductor 3 is burred or turned back by press punching or the like, there is no danger that this will directly contact the metal base 1 in the buried laminated state, and the lower layer A predetermined dielectric strength can be secured by the layer thickness D of the insulating layer 2b.

【0023】[0023]

【発明の効果】以上述べたように本発明によれば、金属
ベースの上に絶縁層,およびパワー回路導体を積層した
金属絶縁基板において、前記パワー回路導体をその上面
を露呈して絶縁層に埋め込み積層したことにより、従来
構造と比べて回路導体/絶縁層間の伝熱面積が増加し、
パワー半導体デバイス用として熱放散性の優れた金属絶
縁基板を提供することができる。
As described above, according to the present invention, in a metal insulating substrate in which an insulating layer and a power circuit conductor are laminated on a metal base, the power circuit conductor is exposed to the insulating layer by exposing its upper surface. By embedding and laminating, the heat transfer area between the circuit conductor / insulating layer increases compared to the conventional structure,
A metal insulating substrate having excellent heat dissipation for a power semiconductor device can be provided.

【0024】また、前記絶縁層を上下2層に分け、その
上層の絶縁層にパワー回路導体を埋め込み積層した構成
により、金属絶縁基板として安定した絶縁耐力の確保が
得られるほか、上下各層の絶縁層を金属ベース,回路部
品との接着性,および誘電率,誘電正接など電気的を特
性を考慮して適正な材料の選択,組合せが行える。
In addition, the insulating layer is divided into upper and lower layers, and a power circuit conductor is buried and laminated in the upper insulating layer. As a result, a stable dielectric strength can be ensured as a metal insulating substrate. The selection and combination of appropriate materials can be performed in consideration of the characteristics of the layer such as a metal base, adhesion to circuit components, and electrical properties such as dielectric constant and dielectric loss tangent.

【0025】さらに、本発明の製造方法を採用すること
により、絶縁層へのパワー回路導体の埋め込み接合,並
びに絶縁層の硬化工程を手間の掛かるインサート成形法
などに頼らずに、高品質,かつ能率よく行うことができ
る。
Further, by adopting the manufacturing method of the present invention, high quality and high quality can be obtained without relying on the embedding and joining of the power circuit conductor into the insulating layer and the hardening step of the insulating layer by a complicated insert molding method. It can be performed efficiently.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1に対応する金属絶縁基板の構
成断面図
FIG. 1 is a configuration sectional view of a metal insulating substrate corresponding to a first embodiment of the present invention.

【図2】本発明の実施例2に対応する金属絶縁基板の構
成断面図
FIG. 2 is a configuration sectional view of a metal insulating substrate corresponding to a second embodiment of the present invention.

【図3】金属絶縁基板の従来例の構成断面図FIG. 3 is a sectional view of a configuration of a conventional example of a metal insulating substrate.

【図4】図1に示した金属絶縁基板の製造方法の説明図
であり、(a) 〜(c) はその組立状態を工程順に表した図
4A to 4C are explanatory diagrams of a method of manufacturing the metal insulating substrate shown in FIG. 1, wherein FIGS.

【図5】図2に示した金属絶縁基板の製造方法の説明図
であり、(a) 〜(d) はその組立状態を工程順に表した図
5 (a) to 5 (d) are views illustrating a method of manufacturing the metal insulating substrate shown in FIG.

【符号の説明】[Explanation of symbols]

1 金属ベース 2 絶縁層 2a 上層の絶縁層 2b 下層の絶縁層 3 パワー回路導体 4 真空加圧プレス DESCRIPTION OF SYMBOLS 1 Metal base 2 Insulating layer 2a Upper insulating layer 2b Lower insulating layer 3 Power circuit conductor 4 Vacuum press

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】金属ベースの上に絶縁層,およびパワー回
路導体を積層したパワー半導体デバイス用の金属絶縁基
板において、前記パワー回路導体を、その上面を露呈し
て絶縁層に埋め込み積層したことを特徴とするパワー半
導体デバイス用金属絶縁基板。
In a metal insulating substrate for a power semiconductor device in which an insulating layer and a power circuit conductor are laminated on a metal base, the power circuit conductor is embedded and laminated in an insulating layer with its upper surface exposed. Features Metal-insulated substrates for power semiconductor devices.
【請求項2】請求項1記載の金属絶縁基板において、絶
縁層を上下二層に分け、その上層の絶縁層にパワー回路
導体を埋め込み積層したことを特徴とするパワー半導体
デバイス用金属絶縁基板。
2. The metal insulating substrate for a power semiconductor device according to claim 1, wherein the insulating layer is divided into upper and lower layers, and a power circuit conductor is embedded and laminated in the upper insulating layer.
【請求項3】請求項2記載の金属絶縁基板において、絶
縁層の上層と下層を同種の絶縁材料で形成したことを特
徴とするパワー半導体デバイス用金属絶縁基板。
3. The metal insulating substrate for a power semiconductor device according to claim 2, wherein the upper layer and the lower layer of the insulating layer are formed of the same kind of insulating material.
【請求項4】請求項2記載の金属絶縁基板において、絶
縁層の上層と下層を異種の絶縁材料で形成したことを特
徴とするパワー半導体デバイス用金属絶縁基板。
4. The metal insulating substrate for a power semiconductor device according to claim 2, wherein the upper layer and the lower layer of the insulating layer are formed of different insulating materials.
【請求項5】請求項1,または2記載の金属絶縁基板に
おいて、パワー回路導体が、金属板をプレス打ち抜き,
もしくはワイヤカットしてパターン形成したものである
ことを特徴とするパワー半導体デバイス用金属絶縁基
板。
5. The metal insulating substrate according to claim 1, wherein the power circuit conductor is formed by pressing and punching a metal plate.
A metal insulating substrate for a power semiconductor device, which is formed by patterning by wire cutting.
【請求項6】金属ベースの表面全域に絶縁層を非硬化状
態で積層する工程と、前記絶縁層の上にパワー回路導体
を重ねた状態で加圧により回路導体を絶縁層に埋め込む
工程と、絶縁層を硬化させる工程からなることを特徴と
する請求項1記載のパワー半導体デバイス用金属絶縁基
板の製造方法。
6. A step of laminating an insulating layer in an uncured state over the entire surface of the metal base, and a step of embedding a circuit conductor in the insulating layer by applying pressure while the power circuit conductor is superimposed on the insulating layer. 2. The method according to claim 1, further comprising a step of curing the insulating layer.
【請求項7】金属ベースの表面全域に下層の絶縁層を積
層する工程と、前記絶縁層が硬化した状態でその上面全
域に上層の絶縁層を非硬化状態で積層する工程と、上層
絶縁層にパワー回路導体を重ねた状態で加圧により回路
導体を上層の絶縁層に埋め込む工程と、上層の絶縁層を
硬化させる工程からなることを特徴とする請求項2記載
のパワー半導体デバイス用金属絶縁基板の製造方法。
7. A step of laminating a lower insulating layer over the entire surface of the metal base, a step of laminating an upper insulating layer in an uncured state over the entire upper surface thereof in a state where the insulating layer is cured, and 3. The metal insulation for a power semiconductor device according to claim 2, further comprising: a step of embedding the circuit conductor in the upper insulating layer by pressing the power circuit conductor in a state where the power circuit conductor is superimposed on the power circuit conductor; and a step of curing the upper insulating layer. Substrate manufacturing method.
JP36014798A 1998-12-18 1998-12-18 Method for manufacturing metal insulating substrate for power semiconductor device Expired - Fee Related JP3879291B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36014798A JP3879291B2 (en) 1998-12-18 1998-12-18 Method for manufacturing metal insulating substrate for power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36014798A JP3879291B2 (en) 1998-12-18 1998-12-18 Method for manufacturing metal insulating substrate for power semiconductor device

Publications (2)

Publication Number Publication Date
JP2000183474A true JP2000183474A (en) 2000-06-30
JP3879291B2 JP3879291B2 (en) 2007-02-07

Family

ID=18468113

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3879291B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335835A (en) * 2006-05-15 2007-12-27 Shin Kobe Electric Mach Co Ltd Wiring board
JP2008198324A (en) * 2007-02-12 2008-08-28 Hutchinson Technol Inc Integrated lead flexure with embedded traces
JP2013149808A (en) * 2012-01-20 2013-08-01 Yamaichi Electronics Co Ltd Metal core flexible wiring board and manufacturing method of the same
JP2020502823A (en) * 2016-12-12 2020-01-23 アンスティテュ ヴェデコム Method and power electronics module for integrating a power chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335835A (en) * 2006-05-15 2007-12-27 Shin Kobe Electric Mach Co Ltd Wiring board
JP2008198324A (en) * 2007-02-12 2008-08-28 Hutchinson Technol Inc Integrated lead flexure with embedded traces
JP2013149808A (en) * 2012-01-20 2013-08-01 Yamaichi Electronics Co Ltd Metal core flexible wiring board and manufacturing method of the same
JP2020502823A (en) * 2016-12-12 2020-01-23 アンスティテュ ヴェデコム Method and power electronics module for integrating a power chip

Also Published As

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JP3879291B2 (en) 2007-02-07

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