GB2321769A

GB2321769A - Method of fabricating a stacked capacitor

Info

Publication number: GB2321769A
Application number: GB9701921A
Authority: GB
Inventors: Fang-Ching Chao
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 1996-08-16
Filing date: 1997-01-30
Publication date: 1998-08-05
Also published as: FR2752481B1; DE19720219A1; GB9701921D0; JPH1079486A; JP3024676B2; FR2752481A1

Abstract

A method for fabricating a semiconductor memory device with a tree-type stacked capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer 34 coupled to at least one branch-like conductive layer 36, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed successively depositing at least one insulating layer 26 and at least one conductive layer 28 over a pillar structure 24 such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The conductive layer 28 is divided into a number of segments by etching. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer 34, forming the trunk-like layer. The insulating material is wet-etched away, leaving the conductive segment attached to the truck-like layer as a branch-like conductive layer. A dielectric layer is formed over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and a further conductive layer is formed overlaying the dielectric layer to serve as an opposing electrode of the tree-type capacitor.

Description

2321769 METHOD OF FABRICATING A SEMICONDUCI'OR MEMORY DEVICE HAVING A

TREE-TYPE CAPACIMR

BACKGROUND OF THE INVENTION I. Field of the Invention:

This invention relates in general to semiconductor memory devices, and more 0 particularly to a structure of a dynamic random access memory (DRAM) cell substantially composed of a transfer transistor and.a charge storage capacitor.

2. Description of the Related Art:

Figure 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell is substantially composed of a transfer transiStor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain thereof is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposing electrode 8 of the capacitor C is connected to a constant power source. A dielectric film 7 is provided between the storage electrode 6 and the opposing electrode 8.

1 In t,he DRAM manufacturing process, a two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM having a storage 1 - capacity less than 1 NI (iiie(la=rnillion) bits In the case of a DRAM having a meniory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, so that the main surface is required to have a large area.

This type of a memory cell is therefore not suited to a DRAM having a high degree of integration. For a high integration DRAM such as a DRAM with more than 4M bits 9-3 of meniory, a three-dimensional capacitor, called a stacked-type or a trench-type capacitor, has been introduced With the stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory in a similar volume. However, to realize a semiconductor device ofan even higher degree of integration, such as a very-large-scaie integration (VLSI) circuit having a capacity of 64M bits, a capacitor of such a simple three dimensional structure as the conventional stacked-type or trench-type, turns out to be 0 insufficiient One solution for improving the capacitance of a capacitor is to use the so called fin-type stacked capacitor, which is proposed in Ema et al, "3Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pp. 592-595, Dec. 1988. The fin-type stacked capacitor includes electrodes and dielectric films which extend in a fin shape in a plurality of stacked layers.

DRAMs having the fin-type stacked capacitor are also disclosed in U.S. Patent Nos.

- 5,196,365 (Gotou), and 5,206,787 5,071,783 (Taguchi et al.); 5,126,8 10 (Gotou)l (Fujioka).

Another solution for improving the capacitance of a capacitor is to use the so called cylindrical-type stacked capacitor, which is propbsed in Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. A DRAM having the cylindrical-type stacked capacitor also is disclosed in the U.S. Patent No. 5,077,688 (Kurnanoya et at.).

With the trend toward increased integration density, the size of the DRAM cell in a plane (the area it occupies in a plane) Must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacity (capacitance). Additionally, as the capacitance is reduced, the likelihood of soft 25) errors arising from the incidence of (x-rays is increased. Therefore, there is still a need in this art to design a new structure of a storage capacitor which can achieve the sanie capacitance, vhile OCCLIJ)111.1,, a snialler area in a plane, arid a suitable niethod of fabricating the structure.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a method for fabricating a semiconductor memory device which is structured with a treetype capacitor that allows an increased area for char-e storaue.

In accordance with the foregoing and other objects of the invention, a new and improved method for fabricating a semiconductor memory device are provided.

The invention provides a method for fabricating a semiconductor memory device. The semiconductor memory device includes a substrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions. According to the method, a first insulating layer is first formed over the substrate, such that it covers the transfer transistor. An insulating pillar is then formed over the first insulating layer, the insulating pillar defining recess areas on either side thereof A first film of insulating material and a second film of conductive material are next alternately formed over the first insulatin_g layer in a recess area and over the insulating pillar. A-selected part of the second film that lies above the in.SUlating pillar is then removed and a first conductive layer is formed which penetrates at least through the second 1- 1111i, the first film, and the first insulating layer so as to be electrically coupled to one of the source/drain regions The first conductive layer and the second film in combination thus form a storage electrode of the charge storage capacitor. The insulating pillar and the first film are then removed. A dielectric layer is formed over exposed 25- SLirfaces.of the first conductive layer and the second film, and a second conductive layer is formed over the dielectric layer The second conductive layer thus functions as an opposing electrode of the charge storage capacitor, 1 A semiconductor memory device according to the invention is therefore formed having a tree-type capacitor of increased area for reliable storage thereon of electrical charges representative of data. By varying the number of conducting layers formed, interleaved with insulating layers, during fabrication, the total surface area of the capacitor electrodes can be controlled The size, shape, and placement of the insulating pillar and the size, shape. and construction of the second conductive layer may also be varied to change the shape of the tree-type capacitor in order to satisf' particular design needs.

D BREWDESCRIPTION OF DRAWINGS

Other objects, features, and advantages of the invention will become apparent from the following detailed descnption of the preferred but non-limiting embodiments.

The description is made with reference to the accompanying drawings in which

Z Figure I is a circuit diagram of a memory cell of a DR-AM device Figures 2A through 2G are cross-sectional views for explaining a first embodiment of a semiconductor memory cell having a tree-type capacitor accordincy to Z) the invention, and a method for fabricating the same according to the invention; Figures 3A through 3D are cross-sectional vie%s for explaining a second embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention and a method fbi- fabricating the same according to tile invention, Fig,ures 4A and 4B are cross-sectional views for explaining a third embodiment of a semiconductor memory ceit having a tree-type capacitor according to the invention and a method for fabricating the same according to the invention; Figures 5A through 5D are cross-sectional views for explaining a fourth C 2 5 embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention and a method for fabricating the same according to the inventioll, 1 C 1 Figures 6A and 6B are cross- sectional views for explaining a fifth embodiment 1 of a semiconductor memory cell having a tree-type capacitor according to the invention and a method for fabricating the same according to the invention, Figures 7A and 713 are cross-sectional views for explaining a sixth embodiment of a semiconductor memory cell having a tree-type capacitor according to the 0 invention and a method for fabricating the same according to the invention; Figures SA through 817 are cross-sectional views for explaining a seventh embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention and a method for fabricating the same according to the invention; Figures 9A through 9D are cross-sectional views for explaining an eighth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention and a method for fabricating the same according to the invention, and Figures 1 OA through 1 OD are cross-sectional views for explaining a ninth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention and a method for fabricating the same according to the invention.

1 1 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Preferred Embodiment A description will be given of a first embodiment of a semiconductor memory

I device havir,,_ a tree-type char-c. storage capacitor according to thein% mtion, by referrinu to Figures 2A through 2G. This embodiment of the semiconductor memory device can bc produced by a first preferred method for fabricating a semiconductor memory device according to the invention.

Referring to Figure 2A, a surface of a silicon substrate 10 is subjected to thernial oxidation by the LOCOS (local oxidation of silicon) technique, and thereby a 2 5 field oxi datiop film 12 having a thickness of approximately 3000 A (angstroms), for

I example, is formed Next, a gyate oxidation film 14 having a thickness of approximately 150 A, for example, is formed by subjecting the silicon substrate 10 to -.5 - I' 1) 0 2-5 the thermal oxidation process. Then a polyslilcon film having a thickness of approximately 2000 A, for example, is deposited on the entire surface of the silicon substrate 10 by CVD (chemical vapor deposition) or LPCVD (low pressure CVD). In order to obtain a polysilicon film of low resistance, suitable impurities such as D phosphorus ions, for example, are diffused into the polysillcon film. Preferably, a refractory metal layer is deposited over the polysificon film, and then an annealing process is carried out to form polycide, so that the film's resistance is further decreased. The refractory metal may be tungsten (W), and its thickness is, for example, approximately 2000 A. Thereafter, the polycide is subjected to a patteming process to form gate electrodes (or word lines) WL I through WL4, as shown in Figure 2A. Then, arsenic ions, for example, are diffused into the silicon substrate 10 at an energy of 70 KeV to provide an impunty concentration of approximately I x 10 1 5 atoMS/CM2, for example. In this step, the word lines WL I through WL4 are used as mask films. Thereby, drain regions 16a and 16b and source regions 18a and 18b are formed in the I Z) silicon substrate 10.

Refemng next to Figure 2B, in the subsequent step the CVD method is used to deposit a planarization insulating layer 20 of, for example, borophosphosilicate glass (BPSG), to a thickness of approximately 7,000A, for example. Thenthesame niethod is used to form an etching protection layer 22, which can be, for example, silicon nitride layer, having a thickness of approximately 1,000 A, for example. After that, a thick insulating layer of, for example silicon dioxide, is deposited over the wafer to a thickness of approximately 7,000 A, for example. Conventional photolithographic and etching processes are then used to define an insulating pillar 24 bounded by recesses 23. Although Figure 2B shows the insulating pillar 24 in a number of separate locations, the insulating pillar 24 is actually an integrated body, which is apparent when viewed from above.

Referrin.,; next to Figure 2C, in the subsequent step the CVD method is used successively to form a first Insulating layer 26. a polysilicon layer 28. and a second insulating layer 30. The first and second insulating layers 26, 30 are preferably formed of silicon oxide. The first insulating layer 26 and the polysilicon layer 28 are each deposited to a thickness of approximately 1,000 A, for example, and the second insulating layer 30 is deposited to a thickness of approximately, 7,000 A, for example.

Arsenic (As) ions can be diffused into the polysilicon layer 28 so as to increase its conductivity.

Referring next to Figure 2D, in the subsequent step, chemical mechanical polishing (CvT) is performed on the surface of the wafer of Figure 2C until an upper part of the polysilicon layer 28 is polished away. The remaining part of the polysilicon layer 28 includes a number of separate sections as designated by the numerals 28a, 28b shown in Figure 2D.

Referring next to Figure 2E, conventional photolithographic and etching processes are then carried out to selectively etch, in sequence, the insulating lay r 30 g e polysilicon layer sections 28a and 28b, insulating layer 26, etching protection layer 22, insulating layer 20, and gate oxidation film 14. As a result, storage electrode contact holes 32a and 321b are formed. The storage electrode contact holes 32a and 32b extend respectively from a top surface of the insulating layer 30 to a top surface of the drain regions 16a and 16b. A polysilicon film is then deposited and etched back, to retill the storage electrode contact holes 32a and 32b with polysillcon layers 34t and 34b Referring next to Figure 2F, in the subsequent step wet etching is performed on 1 => t) 1 the wafer with the etching protection layer 22 as the etch end point, so as to remove the insulating layers 26, 30 and the insulating pillar 24. The remaining tree trunk-like 2 D- poysilicon layers 34, 34b and the branch-like polysilicon layers 28a, 28b, in combination form a tree-like storage electrode for the capacitor of the DRAM. The trunk-like polysilicon layers 34a, 34b are respectively electrically coupled to the drain 11- 2.5 regions 16a and 16b of the transfer transistors in the DRAM. The branch- like polysillcon layers 28a, 28b are each substantially L-shaped in cross section and have the substantially horizontal sections in electrical contact with the trunk-like polysilicon layers 34a, 34b. With this particular shape, the storage electrodes are hereinafter in 0 this specification referred to as "tree-like storage electrodes", and the capacitors thus made are referred to as "tree-type capacitors".

Referring next to Figure 2G, in the subsequent step dielectric films 36a, 36b are respectively formed over the tree-like storage electrode (34a, 28a) and the tree-like storage electrode (34b, 28b). The dielectric films 36a, 36b can be formed of, for example, silicon dioxide, silicon nitride, NO (silicon nitride/silicon dioxide), ONO (silicon dioxide/silicon rutride/silicon dioxide), or the like. Next, an opposing electrode 38 of polysillcon, that opposes the storage electrodes (34a, 28a) and (34b and 28b), is formed over the dielectric films 36a, 36b. The process for forming the opposing electrode 38 includes a first step of depositing a polysilicon layer by the CVD method to a thickness of, for example, approximately 1,000 A, a second step of diffusing N-type impurities into the polysilicon layer so as to increase the conductivity thereof, and a final step of using conventional photolithographic and etching processes to etch away selected parts of the polysilicon layer. The fabrication of the tree-type capacitors in the DRAM is then complete.

To complete the fabrication of the DRAM chip, th_, subsequent steps include fabricating bit lines, bonding pads, interconnections, passivations, and packaging Z> I I I I In" These steps involve only conventional techniques and are not within the spirit and scope of the invention, so that a detailed description thereof will not be provided herein.

Second Pr&rred Embodiment In the foreg :>olng first embodiment, the disclosed tree-type capacitor has only a 1 - 1 - single branch electrode. However. the number of branches is not limited to one and can be two or more. In the following, a second embodiment of the tree-type capacitor, which includes two branches of electrodes, is described with reference to Figures 3 A through 3D. The tree-type capacitor of the second embodiment is based on the wafer structure of Figure 213 Elements in Figures 3A through 33D that are 1 -- identical to those in Figure 2-B are labeled with the same numerals.

Referring to Figure 3A together with Figure 2B, the CVD method is used to successively form alternate layers of insulation and polysilicon, including a first insulating layer 40, a first polysilicon layer 42, a second insulating layer 44, a second polysiliCon layer 46, and a third insulating layer 48. The insulating layers 40, 44, 48 are formed preferably of, for example, silicon oxide. The insulating layers 40, 44 and the polysilicon layers 42, 46 are each deposited to a thickness of approximately 1,000 A, for example, and the insulating layer 48 is deposited to a thickness of approximately 7,000 A, for example. The polysilicon layers 42, 46 can be diffused 11) with arsenic (As) ions so as to increase the conductivity thereof Referring next to Figure 3B, in the subsequent step the CW technique is applied to the surface of the wafer shown in Figure 3A, so as to polish away an upper part of the polysilicon layers 42, 46. The remaining part of the polysilicon layers 42, 46 includes a number of separate sections designated by the numerals 42a, 46a, and 1) 42b, 46b Referring next to Figure 3C, in the subsequent step conventional photolithographic and etching processes are used to form storage electrode contact holes which extend from the top surface of the insulating layer 48 (see Figure 313) to the surface of the drain regions 16a and 161b. The storage electrode contact holes are then refilled with polysilicon layers 50a, 50b by first using the CV1) method to deposit a polysilicon layer, and then etching back part of the polysilicon layer. Subsequently, wet etching is performed on the wafer, with the etchin- g protection layer 22 as the etch end point, so as to remove the Insulating lavers, 40, 44, 48 and the insulating pillar 24. The remaining trunk-like polysillcon layers 50a, 50b and the branch-like polysilicon layers 42a, 46b and 42b, 46b in combination form two tree-like storage electrodes. The trunk-like polysilicon layers 50a, 50b are respectively electrically coupled to the drain regions 16a and 16b of the transfer transistors in the DRAM. The branch-like polysilicon layers 42a, 46a and 42b, 46b are each substantially L-shaped in cross section, and have substantially horizontal sections in contact with the trunk-like polysilicon layers 50a, 50b.

Referring next to Figure 3D, in the subsequent step dielectric films 52a, 52b are respectively formed on the tree-like storage electrodes (50a, 46a, 42a) and (50b, 46b, 42b). Next, an opposing polysilicon electrode 54 is formed over the dielectric films 52a, 52b. The process for forming the opposing electrode 54 includes a first step of depositing a polysilicon layer by the CVD method, a second step of diffusing N-type impurities into the polysillcon layer so as to increase the conductivity thereof, and a final step of using conventional photolithographic and etching processes to etch away selected part of the polysillcon layer. After that, the fabrication for the treetype capacitors in the DRAM is complete.

) o Third Preferred Embodiment In the foregoing first and second embodiment--,, the bottom-most layer of the branch-like part of the tree-like storage electrode is separated from the etching protection layer 22. However, the invention is not limited to such a structure. In the following, a third embodiment of the invention in which the bottom-most layer of the branch-like part of each tree-like storage electrode is in contact with the etching protection layer 22 is described, xvith reference to Figures 4A and 4B.

The ree-type capacitors of the third embodiment are also based on the structure of Figure 2B. Elements in Figures 4A through 4D that are identical to those :> - W in Figure 2B are labeled with the same numerals.

Referring first to Figure 4A together with Figure 2B, the CVD method is used successively to form alternate layers of insulation and polysillcon including a first polysillcon layer 60, a first insulating layer 62, a second polysillcon layer 64, and a second insulating, layer 66.

Referring next to Figure 4B, in the subsequent step the CMP technique is applied to the surface of the wafer shown in Figure 4A, so as to polish away an upper part of the polysillcon layers 60, 64. The remaining parts of the polysilicon layers 60, 64 include a number of separate sections designated by the numerals 60a, 64a, and 60b, 64b. Next, conventional photolithographic and etching processes are used to form storage electrode contact holes. The storage electrode contact holes are then refilled with polysillcon layers 68a, 68b. After that, wet etching is performed on the wafer, with the etching protection layer 22 as the etch end point, so as to remove the insulating layers 62, 66.

The remaining trunk-like polysilicon layers 68a, 68b and the branch-like polysillcon layers 60a, 64b and 60b, 64b in combination form two treelike storage electrodes. The trunk-like polysilicon layers 68a, 68b are respectively electrically coupled to the drain regions 16a and 16b of the transfer transistor in the DRAM.

The branch-like polysillcon layers 60a, 64a and 60b, 64b are each substantially L 20,h:ipcd in cross section, and have substantially horizontal.cctions in contact \vith the trunk-like polysilicon layers 68a, 68b. In this embodiment. the branch- like polysillcon layers 60a, 60b of the tree-like stora,,,,e electrodes are in contact with the etching protection layer 22. A dielectric film and opposing polysilicon electrode may now be formed as described previously for the first, second and third embodiments.

2 5- After that, the fabrication for the tree-type capacitors in the DRAM is complete Fourth Preferred Embodiment - 11 In the foregoing three embodiments, tile trunk-like part of the tree-like storaue electrode of each tree-type capacitor is an integrally formed serniconductor element I However, the invention is not limited to such a structure. In the following, a fourth embodiment, in which the trunk-like part of each tree-like storage electrode is composed of a plurality of semiconductor elements, is described, with reference lo Figures 5 A and 5D.

The tree-type capacitor of the fourth embodiment is also based on the structure of Figure 2A. Elements in Figures 5A through 5D that are identical to those in Figure 2A are labeled with the same numerals.

Referring first to Figure 5A together with Figure 2A, the CVD method is used to deposit a planarization insulating layer 70 over the wafer of, for example, BPSG Then the same method is used to deposit an etching protection layer 72 of, for example, silicon nitride. After that, conventional photolithographic and etching processes are used to etch selected parts of the etching protection layer 72 and the plananzation insulating layer 70, so as to form storage electrode contact holes 76a, 76b which extend from the top surface of the etching protection layer 72 to the top surface of the drain regions 16a and 16b. Next, the CVD, method is used to deposit over the wafer a polysilicon layer which fills the storage electrode contact holes 762, 76b, The polysillcon layer can be diffiised with impurities so as to increase the conductivit", thereof Conventional -photolithographic --nd etching processes then are used to define T-shaped elements 74a, 74b, to form respective bottom parts of capacitor charge storage electrodes for memory cells in the DRAM.

Referring next to Figure 513, in the subsequent step a thick insulating layer of, for example, silicon dioxide, is deposited over the wafer. Then, conventional 2 5 photolithographic and etching processes are used to etch away selected parts of the insulating layer, so as to form insulating pillars 78. Next, the CVD method is used successively to form a first insulatin,(:,, layer 80, a polysilicon layer 82, and a second insulating layer 84, Referring next to Figure 5C, in the subsequent step the CMP technique is applied to the surface of the wafer shown in Figure 5B, so as to polish away an upper part of the polysillcon layer 82. The remaining part of the polysilicon layer 82 includes a number of separate sections designated by the numerals 82a, 82a Referring next to Figure 5D, in the subsequent step conventional photolithographic and etching processes are used to successively etch away selected parts of the second insulating layer 84, polysilicon layers 82a, 82b, and the first insulating layer 80, so as to form contact holes which extend from the top surface of the insulating layer 84 to the top surface of the T-shaped elements 74a, 74b of the tree-like storage electrodes. Then, the contact holes are refilled with polysillcon so as to form upper parts 86a, 86b of the tree-like storage electrodes. The process for refilling the polysilicon into the contact holes includes a first step of depositing a polysillcon layer by the CVD method, and a second step of etching back the same After that, wet etching is performed on the wafer, with the etching protection layer 72 as the etch end point, so as to remove the insulating layers 84, 80 and the insulating pillar 78. This completes the fabrication of the storage electrodes of the tree- type capacitors in the DRAM. The embodiment differs from that of Figure 2F in that the storage electrodes each include in addition a substantially horizontal section extended from the T-shaped elements, 774a, 74b on the botto-rn A dielectric film and opposing polysilicon electrode may now be formed as described previously for the first, second and third embodiments. After that, the fabrication for the tree-type capacitors in the DRAM is complete.

Fifth Preferred Embodiment In th6 foregoing four embodiments, the trunk-like part of the tree-like storage electrode is a solid semiconductor element. However, the invention is not limited to j such a structure. The following description discloses a fifth embodiment with reference to Figures 6A and 613, in which tile trunk-like part of each tree-like storag I ge electrode is hollow.

The tree-type capacitor of the fifth embodiment is based on the structure of Figure 2D. Elements in Figures 6A and 6B that are identical to those in Figure 2D are labeled with the same numerals- Referring first to Figure 6A together with Figure 2D, after the fabrication has reached the stage shown in Figure 2D, conventional photolithographic and etching processes are used to etch away selected parts of the insulating layer 30, the branchlike polysilicon layer 28a, 28b, the insulating layer 26, the etching protection layer 22, the planarization insulating layer 20, and the gate oxidation film 14, so as to form storage electrode contact holes 87a, 87b which extend from the top surface of the insulating layer 30 to the top surfaces of the drain regions 16a and 16b. Next, the CVD method is used to deposit a polysilicon layer in such a manner that the polysillcon layer is formed only on the inner walls of the storage electrode contact holes 87a, 871b, and do not fill up the holes. After that, conventional photolithographic and etching processes are used to define trunk-like polysilicon layers 88a, 88b for the respective storage electrodes of the memory cells in the DRAM. As illustrated in Figure 6A, the trunk-like polysillcon layers 88a, 88b are each g sUbstantially U-shaped in cross section. %%hilch provides an 'Increased area on ',011ch the storage electrodes can store large amounts of electric charge.

Referring next to Figure 613, in the subsequent step wet etching is performed 0 1-:1 C> on the wafer, with the etching protection layer 22 as the etch end point, so as to remove the insulating layers 30, 26 and the insulating pillar 24 This completes the ZD In fabrication of the storage electrodes of the tree-type capacitors in the DRAM. The embodiment Idiffers from that of Figure 2F in that the trunk- like parts of thestorage electrodes, namely the trunk-like polysilicon layers 88a, 88b, are holiow and have U- shaped cross sections, which provide the storage electrodes with an increased surface area. A dielectric film and opposing polysilicon electrode may now be formed as described previously for the first, second and third embodiments. After that, the fabrication for the tree-type capacitors in the DRAM is complete.

Sixth Preferred Embodiment A sixth embodiment of the invention is illustrated in Figures 7A and 7B. In this embodiment also, the trunk-like part of each tree-like storage electrode is hollow.

The tree-type capacitors of the sixth embodiment are based on the structure of Figure 5C. Elements in Figures 7A and 7B that are identical to those in Figure 5C are labeled with the same numerals.

Referfing first to Figure 7A together with Figure 5C, after the fabrication has reached the stage shown in Figure 5C, conventional photolithographic and etching processes are used to etch away selected parts of the insulating layer 84, the polysilicon layers 82a, 82b, and the insulating layer 80, so as to form contact holes 90a, 901b which extend downward from the top surface of the insulating layer 84 to the top surfaces of the T-shaped elements 74a, 74b of the storage electrodes. Next, the CVD method is used to deposit a polysilicon layer which is then etched back so as to form sidewall spacers 92a, 92b on the inner walls of the contact holes 90a, 901) The sideNvall spacers 92n. 92b constitute upper trunk-like parts of the tree- like stOr,-_'C electrodes, and are hollow with U-shaped cross sections, which provides the storage electrode with increased surface area, Referring next to Figure 7B, in the subsequent step wet etching is performed on the wafer, with the etching protection layer 72 as the etch end point, so as to remove the insulating layers 84, 80 and the insulating pillar 78 This completes the fabrication f6r the storage electrodes of the tree-type capacitors in the DRAM. The embodiment differs from that of Figure 5D in that the upper part of each trunk-like electrode is hollow, and has a U-shaped cross section A dielectric film and opposing polysilicon electrode may now be formed as described previously for the first, second and third embodiments. After that, the fabrication for the tree-type capacitors in the DRAM is complete.

J Seventh Preferred Embodiment In the foregoing six embodiments, the branch-like part of the tree-like storage electrode is L-shaped in cross section, so that it is crooked, with two straight segments. However, the invention is not limited to'such a structure. The number of straight segments can be increased to three or more. The following description, with reference to Figures 8A and 8F, is of a seventh embodiment in which the branch-like part of each tree-like storage electrode is crooked, Nkqth four straight segments.

The tree-type capacitors of the seventh embodiment are based on the structure of Figure 2A. Elements in Figures 8A through 8F that are identical to those in Figure 2A are labeled with the same numerals.

Referring first to Figure 8A together with Figure 2A, after the fabncation has reached the staoe shown Figure 2A, the CVD method is used to deposit a planarization insulating layer 100 of, for example, BPSG. Then the same method is used to deposit an etching protection layer, which can be, for example, a silicon nitride layer 102. A thick insulating layer of, for e\ample, silicon dio.\ide, is then deposited over the wafer After that, a conventional photolithographic process is used to form a photoresist layer 106 and then anisotropic etching is performed on the exposed silicon dioxide layer, so as to form protruding insulating layers 104 and an underlying insulated layer 103.

Referring next to Figure 8B, in the subsequent step a photoresist erosion technique is performed to erode away part of the photoresist layer 106, so as to form a photoresist la(yer 106a that is reduced both in breadth and thickness (height). Part of the surface of the protruding insulating layers 104 formerly underlying the uneroded 9.) photoresist laver 106 is thereby exposed Referring next to Figure SC, in the subsequent step anisotropic etching is performed on the exposed surface of the protruding insulating layers 104 and the underlying insulating layer 103, until the silicon nitride layer 102, which serves as 3 etching protection layer, is exposed. Protruding insulating layers 104a with stair-like sidewalls are thu,; formed. After that, the photoresist layer is removed.

Referring next to Figure 81), the subsequent steps are the same as those shown in Figures 2C and 2D in which the CVD method is used successively to form a first insulating layer 108, a polysilicon layer, and a second insulating layer 112, and then the CNT technique is applied to the surface of the wafer so as to polish away an upper part of the polysilicon layer. The remaining part of the polysilicon layer thus includes a number of separate sections designated by the numerals I I Oa, I I Ob.

Referring next to Figure 8E, in the subsequent step conventional photolithographic and etching processes are used to etch away successively selected parts of the insulating layer 112, the polysilicon layers I I Oa, I I Ob, the insulating layer 108, the silicon nitride layer 102, the planarization insulating layer 100, and the gate oxidation film 14, so as to form storage electrode contact holes 114a, 114b which extend from the top surface of the insulating layer 112 to the top surface of the drain regions 16a and 16b. After that, the storage electrode contact holes I 14a, I 14b are I 0 refilled with rolysilicon lavers 116a, 116b by first using the CVD method to deposit a polysilicon laver, and then etching back part of the polysillcon layer.

I Referring, next to Figure 8F, in the subsequent step, wet etching is performed on the wafer, with the silicon nitride layer 102 as the etch end point, so as to remove the insulating layers 112, 108 of silicon dioxide and the insulating pillar 104R. This completes the fabrication of the storage electrodes of the tree-type capacitors in the DR-AM A dielectric film and opposing polysilicon electrode may now be formed as described previOLISly for the first, second and third embodiments. After that, the fabrication for the tree-type capacitors in the DRAM is complete.

As illustrated in Figure 8F, the storage electrodes of the tree-type capacitors include trunk-like polysillcon layers 116a, 1 16b and branchlike polysilicon layers 1102, 1 10b which are each crooked, with four straight segments. The trunk-like polysilicon layers 116a, 116b are electrically coupled to the drain regions 16a and 16b of the transfer transistor in the DRAM. The bottom-most, horizontal segments of the branch-like polysilicon layers 11 Oa, 11 Ob are in contact with the trunklike polysilicon layers 116a, 116b, The insulating pillars or protruding insulating layers of this embodiment are modified in shape so as to form the branch-like polysilicon layers with increased area for charge storage. However, the particular shapes of the insulating pillars and protruding insulating layers are not limited to those disclosed Thus, referring to Figure 2B, for example, isotropic etching or wet etching can be used instead of anisotropic etching to etch away part of the thick insulating layer. This permits the formation of near tnangular-shaped insulating layers instead of the rectangular ones shown. In addition, also referring to Figure 2B, after the insulating pillar 24 is formed, sidewall insulating layers can be formed on the sidewalls of the insulating pillar 24, so as to form insulating pillars of different shape. Therefore, the branch-like polysilicon layers can be modified into various shapes.

If it is desired to fabricate the branch-hke polysilicon layers Xvith an increased number of straight segments, the wafer structure of Figures 8B and 8C can be used as the base and subsequently, the photoresist erosion technique and anisotropic etching g layers with an increased can be used repeatedly to form the protruding insulatin., number of step- like segments.

Eighth Pref6rired Embodiment In the foregoingseven embodiments, the CM11 technique i,, ussed to div. ide a - Is - single layer of polysilicon into separate sections used respectively to form individual storage electrodes. However, the invention is not limited to the use of the C.N.4P technique for that purpose. Instead, according to an eighth embodiment of the 1: gures 9A through 91), conventional photolithographic and invention i I I=) I I etching processes can be substituted for the CMP method, for dividing the sin,fle laver of polysilicon into the separate sections.

The tree-type capacitor of the eighth embodiment is based on the structure of' Figure 3A. Elements in Figures 9A through.91) that are identical to those in Figure 0 3 A are labeled with the same numerals.

Referring first to Figure 9A together with Figure 3A, after the fabrication has reached the stag ge shown in Figure 3A, the topmost layer of silicon dioxide 48 is etched away or polished by the CMP technique, until the topmost polysilicon layer 46 Is exposed. The resultant wafer structure is shown in Figure 9A.

Referring next to Figure 9B, a conventional photolithographic process is used to form a photoresist layer 120. After that, anisotropic etching is performed successively on the exposed parts of the polysilicon layer 46, the silicon dioxide layer 44, and the polysilicon layer 42. By such etching, the polysilicon layers 42, 46 are divided into a number of separate sections designated by the numerals 42c, 42d, and 46c, 46d.

Referring 1leN' io Figure 9C, conventional photolithographic and etching processes are then applied to form storage electrode contact holes 122a, 122b which extend from the top surface of the insulating layer 48 to the top surface of tile drall) regions 16a and 16b. Next, the storage electrode contact holes 122a, 122b are Z_ refilled with polysilicon layers 124a, 124b, by first using the CVD method to deposit a polysilicon layer and then etching back part of the polysilicon layer, Refer-ring next to Figure 91), in the subsequent step wet etching is performed on the wafer, with the eiching protection layer 22 as the etch end poini, so as io remove the insulating layers 40, 44, 48 of silicon dioxide and the insulating pillar 24 This completes the fabrication of the storage electrodes of the tree-type capacitors, A dielectric film and opposing polysilicon electrode may now be formed as described previously for the first, second and third embodiments. After that, the fabrication for the tree-type capacitors In the DRAM is complete.

These electrodes are composed of trunk-like polysilicon layers 124a, 124b and branch-like polysillcon layers 42c, 46c and 42d, 46d, each consisting of three straight segments. The trunk-like polysilicon layers 124a, 124b are electrically coupled respectively to the drain regions 16a and 16b of the transfer transistors in the DRANI.

The branch-like polysilicon layers 42c, 46c and 42d, 46d have their respective bottom- most, horizontal segments in contact with the trunk-like polysilicon layers 50a, 50b.

Ninth Preferred Embodiment In the foregoing first through seventh embodiments, the branch-11ke POlYsilicon I D_ layers have their topmost segments aligned substantially in the same horizontal plane, and in the eighth embodiment, the branch-like polysilicon layers have their topmost segments aligned substantially in the same vertical plane. However, the invention Is not limited to such structures. Instead, according to a ninth embodiment of the invention illustrated in Figures I OA through I OD, the topmost segments of the branchlike polysilicon layers are not aligned- The tree-type capacitor of the ninth embodiment is based on the structure of Figure 9A. Elements in Figures I OA through I OD that are identical to those in Figure 9A are labeled with the same numerals.

Referring first to Figure 10A together with Figure 9A, after the fabrication has reached the stage shown in Figure 9A, a conventional photolithographic process is used to forma photoresist layer 130 and anisotropic etching is performed on the exposed parts of the polysilicon layer 46 and the silicon dioxide layer 44 Thi-OL11111 Z_ this process, the polysilicon layer 46 is divided into a number of separate sections designated by the numerals 46e, 46f.

Referring next to Figure 1 OB, in the subsequent step the photoresIst erosion technique is used to erode away part of the photoresist layer 130, so as to form a photoresist layer 130a of reduced breadth and thickness. Part of the top surface of the polysillcon layers 46e, 46f is thus exposed Then, anisotropic etching is performed on the exposed paris of the polysilicon layers 46e, 46f, and 42. Through this process, parts of the polystlicon layers 46e, 46f are further etched away, thereby forming polysilicon layers 46g, 46h of reduced size. After that, anisotropic etching is again performed on the exposed parts of the silicon dioxide layers 44, 40 until the topmost surfaces of the polysilicon layers 42g, 42h are exposed. The photoresist layer is then removed.

Referring next to Figure I OC, in the subsequent step conventional photolithographic and etching processes are used to form storage electrode contact holes 132a, 132b which extend from the top surface of the insulating layer 48 to the top surfaces of the drain regions 16a and 16b. Then, the storage electrode contact holes 132a, 132b are refilled with polysilicon layers 134a, 134b, by first using the CVD method to deposit a polystlicon layer, and then etching back part of the polysilicon layer.

Referring finally to I- igure 1 OD, in the subsequent step, wet etching is performed on the wafer, with the etching protection layer 22 as the etch end point, so as to remove the insulating layers 40, 44, 48 of silicon dioxide and the insulating pillar 24 This completes the fabrication of the storage electrodes of the tree-type capacitors in the DRAM. A dielectric film and opposing polystlicon electrode may now be formed as described previously for the first, second and third cillbodiments Afler that, the fabrication for the tree-type capacitors in the DRAM is complete.

The -,toras,,e electrodes include trunk-like polysilicon layers 134a, 134b and branch-like polysilicon layers 42g, 46g and 42h, 46h having L-shaped cross sections. The trunk-like polysilicon layers 134a, 1341b are electrically coupled respectively to the drain region 16a and the drain region 16b, of the transfer transistors in the DRAM. The branch-like polysilicon layers 42g, 46g and 42h, 46h have bottom-most, horizontal segments in respective contact with the trunk-like polysilicon layers 134a, 134b, and the substantially vertical segments of the branch-like polysilicon layers 46g, 46h are more elevated than that of the branchlike polysilicon layers 42g, 42h.

It will be apparent to those skilled in the art of semiconductor fabrication that the foregoing disclosed embodiments can be applied either alone or in combination so 10 as to provide storage electrodes of various sizes and shapes on a single DRAM chip. These variations are all within the scope of the invention.

Although in the accompanying drawings the embodiments of the drains of the transfer transistors are based on diffusion areas in a silicon substrate, other variations, for example trench type drain regions, are possible.

Elements in the accompanying drawings are schematic diagrams for demonstrative purpose and not depicted in the actual scale. The dimensions of the elements of the invention as shown should by no means be considered limitations on the scope of the invention.

While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention Is not limited to the disclosed embodiments. To the contrary, it is intended to cover vanous modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims, which define the invention, should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

/-- 1

Claims

What is claimed is:

A method for fabncating a semiconductor memory de,ice including a substrate, ? 0 a transfer transistor having source/drain regions, formed in the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions, said method comprising the steps of I) formincg a first insulating layer over the substrate. the first insulating layer covering the transfer transistor-, (2) forming an insulating pillar over the first insulating layer, the insulating pillar defining recess areas on either side thereon; (3) forming a first conductive layer over the insulating pillar, and over the first insulating layer in the recess areasl (4) removing parts of the first conductive layer leaving a plurality of first conductive layer sections, (5) forming a second conductive layer in a recess area which penetrates at least =1 I I Z-) through the first conductive layer and the first insulating layer, so as to be electncally coupled to one of the source/drain regions, the second conductive layer forming a trunk-like conductive layer, and the first conductive layer forming a branch-like conductive layer substantially L-shaped in cross section, the L-shaped cross section havins4 one end connected to the trunk-like conductive layer, v,-herein the first conductive layer and the second conductive layer in combination form a storage electrode for the charge storage capacitor; (6) removing the insulating pillar (7) forming a dielectric layer over the first and second conductive layers, and (8) forming a third conductive layer over the dielectric layer, the third conductive layer serving as an opposing electrode of the charge storage capacitor Z - 2. A method as claimed in clairn 1, wherein the trunk-like conductive layei - 2" - includes a substantially upright segment having a bottom end electrically coupled to one of the source/drain regions.

3. A method as claimed in claim 1, further comprising, between said step (1) and step (2) the step of forming an etching protection layer over the first sai 1 _l> 1 =1 1 ing layer.

A method as claimed in claim 3, wherein said step (2) includes the steps of forming a thick insulating layer over the etching protection layer., forming a photoresist layer over the thick insulating layer, such that a first portion of the thick insulating layer is exposed, etching away part of the exposed first portion of the thick insulating layer to form the recess in the first exposed portion; eroding away a selected part of the photoresist layer so as to further expose a 0 1 DS second portion of the thick insulating layer, and etching the exposed second portion and further etching the exposed first C> ZP portion until the etching protection layer is exposed in the recess and so as to form the insulating pillar with a staircase-like cross section.

A method as cia'lnied in claim 4, whercin said step (4) includes the step of etching away the selected part of the first conductive layer that lies above the insulating pillar 6. A method as claimed in claim 4, wherein said step (4) includes the step of 2 D- performing chemical mechanical polishing so as to polish away the selected part of the first conduettve layer that lies above the insulating pillar.

7. A method as claimed in claim 4, ffir-ther comprising, between said step (3) and said step (4) the step of formino a second insulating layer over the first conductive layer, such that the second insulating layer substantially fills up the recess area; and wherein said step (5) includes the step of forming the second conductive layer to penetrate through the second insulating layer. and wherein said step (6) includes the step of removing the second insulating layer 1 8. A method as claimed in claim 4, further comprising, between said step (3) and said step (4), the steps of forming alternately at least a first film of insulating material and a second film of conductive material, over the first conductive layer, and forming a second insulating layer over the second film, so as to substantially fill up the recess; 1 1_) wherein said step (4) further includes the step of removing a selected upper pan of the second film that lies above the insulating pillar; wherein said step (5) further includes the step of forming the second 1.

conductive layer to penetrate successively through the second insulating layer, the second film, and the first film-1 and wherein said step (6) fur-ther includes the step of removing the second C> 2 CJ Insulating g la,.,ct and the first film 9. A method as claimed in claim 4, wherein said step (5) further includes the step of forming the second conductive layer with a substantially U- shaped cross section.

2D 10. A method as claimed in claim 3, wherein the recess area Is bounded at a bottom thereof by tre etching protection layer, the insulating pillar being formed on the etching protection laver 11. A method as claimed in claim 1, wherein said step (4) includes the step of etching away the selected part of the first conductive layer that lies above the insulating pillar, D 12. A method as claimed in claim 1, wherein said step (4) includes the step of using chemical mechanical polishing to polish away the selected pari: ofthe first conductive layer that lies above the insulating pillar.

13. A method as claimed in claim 1, further comprising, between said step (3) and id step (4) the step of forming a second insulating layer over the first conductive sai 1 It> layer, the second insulating layer substantially filling up the recess area.

wherein said step (5) includes forming the second conductive layer so as to penetrate through the second insulating layer; and wherein said step (6) includes removing the second insulating layer.

14. A method as claimed in claim 1, further comprising, between said step (3) and said step (4), the steps of.. forming alternately at least a first film of insulating material and a second film 20 ufLonductive material, over the first conductive layer, and forming a second insulating layer over the second film, so as to substantially fill up the recess area., wherein said step (4) further includes the step of removing a selected pail of the second film so as to remove an upper part of the second film that lies above the 2,1) insulatinu pillar. wherein said step (5) further includes the step of forming the second conductlx,e]aver to penetrate successively through the second insLilat'tn,.:, layer, the second film, and the first film. and wherein said step (6) further includes the step of removing the second insulating layer and the first film.

D 15. A method as claimed in claim 1, wherein said step (5) further includes the step of forming the second conductive layer with a substantially U-shaped cross section 16. A method as claimed in claim 1, further comprising, between said step (3)) and said step (4), the steps of..

forming alternately at least a first film of insulating material and a second film of conductive material, over the first conductive layer; and forming a second insulating layer over the second film, so as to substantially fill up the recess area.

wherein said step (4) further includes the steps of forming a photoresist layer without covering at least the insulating pillar, removing successively, exposed parts of the second film and the first film, of the second film, eroding away part of the photoresist layer so as to expose another part after sald step of eroding, reniovina the exposed another part of the second film and an exposed part of the first conductive layer., and removing the photoresist layer., wherein said step (5) further includes the step of forming the second conductive layer to penetrate successively throm gh the second Insulating layer, the 2 D- second film, and the first film, and wherein said step (6) further includes the step of removing the second insulatim, laver and the first film.

W 1 17. A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge D I - d method storage capac tor electrically coupled to one of the source/drain regnons, sai comprising the steps of (1) forming a first insulating layer over the substrate, the first insulating layer coverinu, the transfer transistor-, (2) forming an insulating pillar over the first insulating layer, the insulating pillar defining recess areas on either side thereof, (3) forming altemately a first film of insulating material and a second film of conductive material over the first insulating layer in a recess area and over the insulating pillar; (4) removing a selected part of the second film that lies above the insulating pillar, (5) forming a first conductive layer which penetrates at least through the second film, the first film, and the first insulating layer so as to be electrically coupled to one of the sourceldrain regions, wherein the first conductive layer and the second film in combination form a storage electrode of the chara 1 gc storage capacitor', (6) removing the insulating pillar and the first film, (7) forming a dielectric layer over exposed surfaces ofilie first conductive laver and the second film. and (8) forming a second conductive layer over the dielectric layer, the second conductive layer serving as an opposing electrode of the charge storage capacitor.

c W is. A method as claimed in claim 17, wherein the first conductive layer forms a trunk-like conductive layer and the second film forms a branch- like conductive layer substantially L-shaped in cross section, the branch- like conductive layer having one end connected to'the trunk-like conductive layer.

19. A method as claimed in claim 18, wherein the trunk-like conductive layer is substantially upright and has a bottorn end electrically coupled to one of the 3 sourceldrain regions, 20. A method as claimed in claim 17. further comprising, between said step (1) and id step (2), the step of forming an etching protection layer over the first insulating sai 1 t> 1 = layer.

21. A method as claimed in claim 17, wherein said step (4) includes the step of etching away the selected part of the second film that lies above the insulating pillar.

22. A method as claimed in claim 17, wherein said step (4) includes the step of using chemical mechanical polishing to polish away the selected part of the second film that lies above the insulating pillar.

23. A method as claimed in claim 17, further comprising, between said step (3) and said step (4), the step of forming a second insulating layer over the second film, such 0 that the second insulating layer substanilally fills up the recess area z 1 wherein said step (5) includes the step of forming the first conductive layer so as to penetrate through the second insulating layer. and W ZZ) id step (6) includes the step of removing the second insulating layer.

sai 1 1 - C, Z 24. A method as claimed in claim 17, wherein said step (5) further includes the step of forming the first conductive layer with a substantially U-shaped cross section.

25. A method as claimed in claim 20, wherein said step (2) further includes the steps of forming a thick insulating layer over the etching protection layer. forming a photoresist layer over the thick insulating layer, such that the recess j area is exposed, removing an exposed part of the thick insulating layer in the recess area eroding away part of the photoresist layer so as to expose a further part of the thick insulating layer., removing the further exposed part of the thick insulating layer to expose the etching protection layer, so as to form the insulating pillar with a staircase-iike cross section; and removing the photoresist layer.

26. A method as claimed in claim 25, wherein said step (4) includes the step of 15 etching away the selected part of the second film that lies above the insulating pillar.

27. A method as claimed in claim 25, wherein said step (4) includes the step of using chemical mechanical polishing to polish away the selected part of the second film that lies above the insulating pillar.

Z-> 28. A method as claimed in claim 25, further comprising, between said step (3) and said step (4), the step of forming., a second insulating layer over the _Recond film such that the second insulating layer substantially fills up the recess area, wherein said step (5) includes the step of forming the first conductive layer so 9 D- as to penetrate through the second insulating layer. and wherein said step (6) includes the step of removing the second insulating layer.

1 29. A method as claimed in claim 25, wherein said step (5) further includes the step of'foriiiin(:,, the first conductive layer with a substantially U-shaped cross section.

30. A method as claimed in claim 17, ffirther comprising the steps of.. step (3) to obtain in the recess area, tv..o first films ofinsulati g repeating sat 1 1 in.

material interleaved with two second films of conductive material, and forming a second insulating layer over the topmost second film, so that the 1 second insulating layer substantially fills up the recess area, wherein said step (4) includes the steps of (a) forming a photoresist layer over"the topmost second film such that part of the top most second film over the insulating pillar is exposed., (b) after said step (a), removing successively exposed parts of the topmost second film and the topmost first film; (c) eroding away part of the photoresist layer so as to expose another 0 part of the topmost second film; (d) removing the exposed another part of the second film; and (e) removing the photoresist layer after said step (d), wherein said step (5) further includes forming the first conductive layer to penetrate through the second insulating layer. and wherein said step (6) further includes the step of removing, the second insulating layer.

31. A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions formed on the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions, said method comprising the steps of 0) formino a first 'nSLIlatn(, layer over the substrate, the insulating layer I I Z) 1 - _) i - covering the transfer transistor., W (2) forming a first conductive layer which penetrates through at least the first 1 insulating layer so.as to be electrically coupled to one of the source/drain regions., (3) forming an insulating pillar over the first insulating layer, the insulating CP pillar defining recess areas on either side thereof., (4) forming alternately, a first film of insulating material and a second film of conductive material over the first insulating layer in a recess area and over the insulating pillar; (5) removing a selected part of the second film that lies above the insulating pillar.

(6) forming a second conductive layer which penetrates at least through the second film and the first film so as to be electrically coupled to one of the source/drain regions, the first and second conductive layers and the second film in combination forming a storage electrode of the charge storage capacitor; (7) removing the insulating pillar and the first film.

(8) forming a dielectric layer over exposed surfaces of the first and second conductive layers and the second film. and (9) forming a third conductive layer over the dielectric layer, the third conductive layer serving as an opposing g electrode for the charge storage capacitor.

32. A method as claimed in claim 3 1, wherein the second film is substantially L, shaped in cross section and has one end connected to the second conductive layer 33. A method as claimed in claim 32, wherein the first conductive layer is 2 5_ substantially T-shaped in cross section.

34. A method as clanned in claini 32, whercin the second conductIve layer IS substantially U-shaped in cross section.

35. A method as claimed in claim 31, further comprising, between said step (1) and said step (2), the step of forming an etching protection layer over the first insulating layer.

36. A method as claimed in claim 35, wherein said step (3) includes the steps of.. forming a thick insulating layer over the etching protection layer, forming a photoresist layer over the thick insulating layer, such that the recess area is exposed.

removing an exposed part of the thick insulating layer in the recess area; eroding away pari of the photoresist layer so as to expose a further part of the thick insulating layer. removing the further exposed part of the thick insulating layer to expose the etching protection layer, so as to form the insulating pillar with a staircase-like cross section, and removing the photoresist layer.

2D 37. A method as claimed in claim 36, wherein said step (5) includes the step of enching away the selected part of the second film that lies above the insulating pillar.

z> 1 - 38- A method as claimed in claim 36, wherein said step (5) includes the step of performing chemical mechanical polishing to polish away the selected part of the second film that lies above the insulating pillar.

39. A method as claimed in claim 36, further comprising, between said step (4) and said step (5), the step of forming a second layer over the second film, such 1 - j that the second insulating layer substantially fills up the recess area in the insulating pillar. wherein said step (6) includes the step of forming the second conductive layer so as to penetrate through the second insulating layer; and wherein said step (7) includes the step of removing the second insulating layer C> c 40. A method as claimed in claini 31, wherein said step (5) includes the step of etching away the selected part of the second film that lies above the insulating pillar.

41. A method as claimed in claim 30, wherein said step (5) includes the step of performing chernical mechanical polishing to polish away the selected part of the second film that lies above the insulating pillar.

42. A method as claimed in claim 31, further comprising, between said step (4) and 15) said step (5), the step of forming a second insulating layer over the second film, such that the second insulating layer substantially fills up the recess area; wherein said step (6) includes the step of forming the second conductive layer to penetrate through the second insulating layer., and id step (7) includes the step of removing the second insulating layer.

sai 1 1 W -P 43. A method as claimed in claim 31, further comprising repeating said step (4) to obtain in the recess area two first films of insulatinw material interleaved with two second films of conductive material., and forming a second insulating layer over the topmost second film, so that the second insulating layer substantially fills up the recess area., wherein said step (5) includes the steps of (a) forming, a photoresist layer over the topmost second filin such that 1)4 part of the topmost second film over the insulating pillar is exposed..

(b) removing successively exposed parts of the topmost second film and the topmost first film., (c) eroding away part of the photoresist layer so as to expose another part of the topmost second film., (d) removing the exposed another part of the second film., and (e) removing the photoresist layer after second said step (d). wherein said step (6) further includes the step of forming the second conductive layer to penetrate through the second insulating layer, and wherein said step (7) further includes the step of removing the second insulating layer.

44. A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge 1. 1 storage capacitor electrically coupled to one of the source/drain regions, said method comprising the steps of I (1) forming an insulating layer over the substrate, the insulating layer covering -:1 I I I the transfer transistor; (2) forming a trunk-like conductive layer having a bottom end electrically COUpled to one of ifie source/drain regions, the trunk-like CcMdUctive layer extending substantially upright from the bottom end-, (3) forming a branch-like conductive layer, including at least a first segment C) and a second segment, the first segment having a first end connected to the trunk-like conductive layer and a second end connected to the second segment, the second 2 5) segment being alloned at a first anole with respect to the first seizinent, wherein the trunk-like conductive layer and the branch-like conductive layer in combination form a storaue electrode of the charve storave capacitor', C.) n (4) forming a dielectric layer over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer., and (5) forming an overlaying conductive layer overlaying the dielectric layer, the overlaying conductive layer seR?ing as an opposing electrode for the charge storage capacitor.

45. A method for fabricating a semiconductor memory device including a substrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge storage capacitor electrically coupled to one of the source/drain regions, said method 10 comprising the steps of (1) forming an insulating layer over the substrate, the insulating layer covering the transfer transistor, (2) forming a trunk-like conductive layer having a bottom end electrically coupled to one of the source/drain regions of the transfer transistor, the trunk-like conductive layer extending substantially upright from the bottom end; (3) forming a branch-like conductive layer, including at least a segment having one end connected to the trunk-like conductive layer, extending outwards from the trunk-like conductive layer, wherein the trunk-like conductive layer and the branch-like conductive layer, in combination, form a storage electrode of the charge storage capacitor, (4) forming a dielectric layer over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer; and (5) forming an overlaying conductive layer overlaying the dielectric layer, the overlaying conductive layer serving as an opposing electrode of the charge storage 23 capacitor 46. A method 1-Or fabricatino a seri^conductor meniory dcv'ce iticiiid'n,, a subtrate, a transfer transistor having source/drain regions, formed on the substrate, and a charge storage capacitor electrically COLIpled to one of the source/drain regions, said method comprising the steps of I) forming an insulating layer over the substrate, the insulating layer covering the transfer transistor-, (2) forming a trunk-like conductive layer having a bottom end electrically coupled to one of the source/drain regions, the trunk-like conductive layer extending substantially upright from the bottom end; (3) forming a branch-like conductive layer, substantially L-shaped in cross section, the branch-like conductive layer having one -end connected to the trunk-like conductive layer, wherein the trunk-like conductive layer and the branch-like conductive layer, in combination, form a storage electrode of the charge storage capacitor', (4) forming a dielectric layer over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer; and (5) forming an overlaying conductive layer overlaying the dielectric layer, the Z> ID overlaying conductive layer serving as an opposing electrode of the charge storage capacitor.