GB2320809A - Forming a protective film in a semiconductor device - Google Patents
Forming a protective film in a semiconductor device Download PDFInfo
- Publication number
- GB2320809A GB2320809A GB9727080A GB9727080A GB2320809A GB 2320809 A GB2320809 A GB 2320809A GB 9727080 A GB9727080 A GB 9727080A GB 9727080 A GB9727080 A GB 9727080A GB 2320809 A GB2320809 A GB 2320809A
- Authority
- GB
- United Kingdom
- Prior art keywords
- film
- sog
- forming
- metal wires
- sog film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 8
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 238000005649 metathesis reaction Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- WCYWZMWISLQXQU-UHFFFAOYSA-N methyl Chemical compound [CH3] WCYWZMWISLQXQU-UHFFFAOYSA-N 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- -1 methyl-siloxane Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming a protective film which can decrease a parasitic capacitance between metal wires of a semi-conductor device comprises the steps of forming metal wires 32 on a substrate 31 depositing a silicon oxide film 33 on the substrate including the metal wires, forming a SOG film 34 on the silicon oxide film, hardening the SOG film and then forming a silicon nitride 35 film on the SOG film. The SOG film, which may be etched, is formed of a material having a lower dielectric constant than that of the silicon oxide film, e.g. methyl-silsesquioxane or hydrogen-silsesquioxane.
Description
2320809 METHOD OF FORMING A PROTECTIVE FILM IN A SEMICONDUCTOR DEVICE
BACKGROUND OF THE INVENTION Field of the invention
The present invention relates to a method of forming a protective film in a semiconductor device which can decrease a parasitic capacitance between the metal wires.
Description of the prior art
In general, a protective film in a semiconductor device is consisted of a silicon oxide film and nitride film in stack and formed by a plasma deposition. And the protective film is used for protecting a semiconductor device from the external environmental variation. However, since the silicon oxide film (dielectric constant k=4.2) and nitride film (dielectric constant k=6-8) have the high dielectric constant, if the width of metal and space between the metal wires are below lpm, a parasitic capacitance between wires increases rapidly so that the mutual interference of signal and signal transfer delay characteristic are generated. As a result, the operation characteristic of device is deteriorated.
The inferiority of device due to the parasitic capacitance between the wires occurs extremely in the high speed operation device. Also, a weak portion is generated at lower portion of the metal wire after forming a protective film 1 due to a step covering inferiority according to a height of metal wire and interval between metal wires, thereby lowering the reliability of device.
FIG. 1A is a sectional view of the device in which metal wires are formed and FIG. IB is an equivalent circuit showing a parasitic capacitance between the metal wires in FIG. 1A. Metal wires 12 are formed on a substrate 11, at this time, the parasitic capacitance between the metal wires 12 is considered as ideal parasitic capacitance because air whose dielectric constant is 1 exists between the metal wires 12.
FIG. 2A is a sectional view of the device in which a conventional protective film is formed. A silicon oxide film 23 and a silicon nitride 24 are formed on a substrate 21 including metal wires 23.
FIG. 2B is an equivalent circuit showing a parasitic capacitance between the metal wires in FIG. 1A. The parasitic capacitance between the metal wires 23 is proportioned to the metal wires and dielectric constant and is in inverse proportion to the distance between the metal wires. Therefore, the parasitic capacitance between the metal wires increase due to the oxide film 23 having a high dielectric constant (k=4.3) and nitride film 24 having a high dielectric constant(k=8), thereby generating the mutual interfering effect. In particular, a peripheral circuits around the circuit to which a driving voltage is applied are great effected. Also, as shown in FIG. 2A, a thickness of the oxide film 23 and the nitride film 24 is thinner at the low portion of the metal wires 22 so that a weak portion W is generated, thereby degrading a characteristic of the protective 2 film.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method of forming a protective film which can decrease a parasitic capacitance between metal wires and improve weak portion thereof.
To achieve this object, a method of forming a protective film comprises the steps of forming metal wires of a substrate, depositing a silicon oxide film on the substrate including the metal wires, forming a SOG film on the silicon oxide film, hardening the SOG film and then forming a silicon nitride film on the SOG film.
The SOG film is formed of a material having a lower dielectric constant than that of the silicon oxide film, and formed of one of methyl silsesquioxane and hydrogen- silsesquioxane.
Brief description of the drawings
Other objects and advantages of the present invention will be understood by the detailed explanation of the embodiment with reference to the accompanying drawings in which:
FIG. 1A is a sectional view of the device in which metal wires are formed', FIG. IB is an equivalent circuit of the device in FIG. 1A.
FIG. 2A is a sectional view of device in which a conventional protective 3 film is formed; FIG. 2B is an equivalent circuit of device in FIG. 2A; FIG. 3A is a sectional view of device in which a protective film according to the first embodiment of the present invention is formed; FIG. 3B is an equivalent circuit of device in FIG. 3A; FIG. 3C is a sectional view of device in which a protective film according to the second embodiment of the present invention is formed; FIG. 4 is a table illustrating the chemical structural fonnula of materials used as SOG in the prior arts and present invention; and
FIG. 5 is a graph to compare yields when a conventional protective film and a protective film of the present invention are used.
Detailed description of the drawings
FIG. 3A is a sectional view of device in which a protective film according to the first embodiment of the present invention is formed.
A thin silicon oxide film 33 is deposited on a substrate 31 including metal wires 32. A SOG (spin on glass) film 34 having a low dielectric constant (k=3) is coated on the silicon oxide film 33 and then is hardened. A silicon nitride film 35 is deposited on the SOG film 34. When the SOG film 34 is deposited, the substrate 31 is rotated. Therefore, a surface of the SOG film 34 is planarized and void does not exist in the SOG film 34 due to the fluidity of SOG. That is, density of SOG film 34 becomes higher.
4 In order to volatilize an oily materials contained in the coated SOG film 34, a bake process to the coated SOG 34 is performed in a temperature of 90 to 400 degree Celsius. At this time, temperature may be changed in response to the characteristic of the oily materials and SOG. A hardening process is performed executed to stabilize the chemical bond of the coated SOG film 34 at temperature of 400 to 500 degree Celsius. Also, a silicon oxide film may be formed on the SOG film 34 so that moisture can not be absorbed into the SOG film 34 and a reliability of device can increase.
The silicon nitride film 35 is used as a final protective film, and is uniforrrdy deposited on the SOG film 34 having an excellent plananizing characteristic. As shown in FIG. 3A, however, a topology in vertical direction is not generated due to the fluidity of SOG, thus a weak portion of the silicon nitride film 36 is not generated, Due to the silicon nitride film 35, the ability for protecting a device from an external environment such as external pressure and moisture penetration can be enhanced.
FIG. 313 is an equivalent circuit of device in FIG. 3A. Comparing with FIG. 2B, it can be seen that the parasitic capacitance between the metal wires 32 is more improved than that of the prior art by using the SOG film 34 having a low dielectjic constant (k=3) and the oxide film 33 having a dielectric constant (k=4.3).
FIG. 3C is a sectional view of a device in which a protective film according to the second embodiment of the present invention is formed.
A thin silicon oxide film 43 is deposited on a substrate 41 including metal wires 42. A SOG film 44 having a low dielectric constant (k=3) is coated on the silicon oxide film 43 and then is hardened. Then, the SOG film 44 is dry etched so that the silicon oxide film 43 fonned on the metal wires 44 is exposed.
It can be seen that a silicon nitride film 45 formed on the SOG film 44 is more planarized and penetration of moisture into the SOG film 44 can be prevented.
Here, of course, the parasitic capacitance between the metal wires 42 is same as that between the metal wires 32 as shown in FIG. 3B.
FIG. 4 illustrates the chemical structural formula of materials used as SOG film in the prior arts and the present invention.
In the present invention, methyl- silsesquioxane which is a kind of hydrocarbon metathesis type SOG or hydrogen- silsesquioxane which is a kind of hydrogen metathesis type SOG is used as the low dielectric SOG. SOG use in the present invention has a dielectric constant (k) of 3.0 or less while SOG of methyl-siloxane order and silicate order has a dielectric constant (k) of 3.8 or more. Hydrocarbon metathesis type SOG and hydrogen metathesis type SOG is obtained by improving a strong polarity characteristic between atoms of the conventional silicon-oxygen through methyl radical or hydrogenation.
A coating process of the low dielectric SOG is performed at various conditions in response to the height of the metal wire and space between the metal wires.
6 FIG. 5 is a graph for comparing yields when the conventional protective film, the first protective film formed SOG of siloxane order and silicate order having a dielectric constant of 3.8 or more and the second protective film formed of methyl- silsesquioxame or hydrogensilsesquioxane having a dielectric constant of 3.0 or less according to the present invention are formed, respectively.
As known in FIG. 5, when the protective film according to the present invention is formed. yield enhances about 2.25 times as much as the conventional protective film.
In the present invention, as described above, SOG used for forming a protective film and having a low dielectric constant has an excellent planarizing and filling characteristics so that a stable protective film can be obtained. Due to SOG having a low dielectric constant, parasitic capacitance between the metal wires is minimized, thus, the reliability of device can be enhanced.
The foregoing description, although described in its prefer-red embodiments with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be lirwited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.
7
Claims (8)
1. A method of forming a protective film in a semiconductor device, comprising the steps of; forn-iing metal wires of a substrate, depositing a silicon oxide film on said substrate including said metal wires; forming a SOG film on said silicon oxide film, said SOG film formed of a material having a lower dielectric constant than that of said silicon oxide film; and SOG film.
hardening said SOG film and then forming a silicon nitride film on said
2. The method of claim 1, wherein said SOG film is dried at temperature of 90 to 400 degree Celsius before perfon-rling hardening step.
3. The method of claim 1, wherein said SOG film is hardened at temperature of 400 to 500 degree Celsius.
4. The method of claim 1, wherein said SOG film is formed of one of methyl- silsesquioxane and hydrogen-silsesquioxane.
5. A method of forming a protective film in a semiconductor device, 8 comprising the steps of; forming metal wires of a substrate, depositing a silicon oxide film on said substrate including said metal wires; forming a SOG film on said silicon oxide film, said SOG film formed of a material having a lower dielectric constant than that of said silicon oxide film; hardening said SOG film and then etching portions of said SOG film; and forming a silicon nitride film on said SOG film.
6. The method of claim 5, wherein said SOG film is dried at temperature of 90 to 400 degree Celsius before performing hardening step.
7. The method of claim 5, wherein said SOG film is hardened at temperature of 400 to 500 degree Celsius.
8. The method of claim 5, wherein said SOG film is formed of one of methyl- silsesquioxane and hydrogen - silsesquioxane.
9
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960074957A KR19980055721A (en) | 1996-12-28 | 1996-12-28 | Method of forming protective film of semiconductor device |
Publications (4)
| Publication Number | Publication Date |
|---|---|
| GB9727080D0 GB9727080D0 (en) | 1998-02-18 |
| GB2320809A true GB2320809A (en) | 1998-07-01 |
| GB2320809A8 GB2320809A8 (en) | 1998-08-04 |
| GB2320809B GB2320809B (en) | 2001-09-12 |
Family
ID=19491706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9727080A Expired - Fee Related GB2320809B (en) | 1996-12-28 | 1997-12-23 | Method of forming a protective film in a semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH10199877A (en) |
| KR (1) | KR19980055721A (en) |
| CN (1) | CN1113398C (en) |
| DE (1) | DE19757879A1 (en) |
| GB (1) | GB2320809B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2358733A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Integrated circuit with multi-layer dielectric having reduced capacitance |
| GB2358734A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance |
| US7670961B2 (en) | 2004-06-08 | 2010-03-02 | Nxp B.V. | Reduction of cracking in low-k spin-on dielectric films |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444331C (en) * | 2003-11-11 | 2008-12-17 | 三星电子株式会社 | Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3745428A (en) * | 1970-01-30 | 1973-07-10 | Hitachi Ltd | Semiconductor device having a composite film as a passivating film |
| US4091407A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
| WO1987002828A1 (en) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Glass intermetal dielectric |
| US5057897A (en) * | 1990-03-05 | 1991-10-15 | Vlsi Technology, Inc. | Charge neutralization using silicon-enriched oxide layer |
| GB2308735A (en) * | 1995-12-23 | 1997-07-02 | Hyundai Electronics Ind | A method of manufacturing a semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374833A (en) * | 1990-03-05 | 1994-12-20 | Vlsi Technology, Inc. | Structure for suppression of field inversion caused by charge build-up in the dielectric |
-
1996
- 1996-12-28 KR KR1019960074957A patent/KR19980055721A/en not_active Application Discontinuation
-
1997
- 1997-12-23 GB GB9727080A patent/GB2320809B/en not_active Expired - Fee Related
- 1997-12-24 DE DE19757879A patent/DE19757879A1/en not_active Ceased
- 1997-12-25 CN CN97125706A patent/CN1113398C/en not_active Expired - Fee Related
- 1997-12-26 JP JP9370264A patent/JPH10199877A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3745428A (en) * | 1970-01-30 | 1973-07-10 | Hitachi Ltd | Semiconductor device having a composite film as a passivating film |
| US4091407A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
| WO1987002828A1 (en) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Glass intermetal dielectric |
| US5057897A (en) * | 1990-03-05 | 1991-10-15 | Vlsi Technology, Inc. | Charge neutralization using silicon-enriched oxide layer |
| GB2308735A (en) * | 1995-12-23 | 1997-07-02 | Hyundai Electronics Ind | A method of manufacturing a semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2358733A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Integrated circuit with multi-layer dielectric having reduced capacitance |
| GB2358734A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance |
| US7670961B2 (en) | 2004-06-08 | 2010-03-02 | Nxp B.V. | Reduction of cracking in low-k spin-on dielectric films |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2320809B (en) | 2001-09-12 |
| GB9727080D0 (en) | 1998-02-18 |
| CN1187027A (en) | 1998-07-08 |
| CN1113398C (en) | 2003-07-02 |
| GB2320809A8 (en) | 1998-08-04 |
| KR19980055721A (en) | 1998-09-25 |
| DE19757879A1 (en) | 1998-07-02 |
| JPH10199877A (en) | 1998-07-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20091223 |