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GB2358734A - Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance - Google Patents

Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance Download PDF

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Publication number
GB2358734A
GB2358734A GB0019969A GB0019969A GB2358734A GB 2358734 A GB2358734 A GB 2358734A GB 0019969 A GB0019969 A GB 0019969A GB 0019969 A GB0019969 A GB 0019969A GB 2358734 A GB2358734 A GB 2358734A
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United Kingdom
Prior art keywords
layer
low
recited
dielectric
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0019969A
Other versions
GB0019969D0 (en
Inventor
Jr Gerald W Gibson
Steven Alan Lytle
Mary Drummond Roby
Daniel Joseph Vitkavage
Thomas Michael Wolf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of GB0019969D0 publication Critical patent/GB0019969D0/en
Publication of GB2358734A publication Critical patent/GB2358734A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A process for fabricating integrated circuit comprising dielectric structural layer (101) and low dielectric constant (low-k) layer (102) disposed over substrate (100) is disclosed. The low k-layer (102) may exist between conductive elements (103) such as vias and trenches in a dual-damascene structure. The low-k layer (102) may have a dielectric constant below 3.7 and be composed of organic polymers including hybrido organo siloxane polymers, nanoporous silicate glass or organo silicate glass. The structural layer (101) may be composed of silicon dioxide (SiO<SB>2</SB>) or fluorine doped silicon dioxide (FSG), and have a Young's modulus between 60 and 120 GPa. The low k-layer (102) reduces the overall dielectric constant in the structure and the intralayer or line-to-line capacitance between conductive elements (103). A via may exist in the structural layer, or the structural layer may be disposed directly on a conductive layer.

Description

2358734 Process For Fabricating Low Dielectric Constant (Low-k) Layers In
Integrated Circuits
Cross-Reference To Related Applications
The present applications is related to (Attorney Docket No. Gibson 3 12-2-16-10), U. S. Patent Application Serial No. 09/385713, which is specifically incorporated by reference herein.
Field of the Inventio
The present invention relates to an integrated circuit structure and its method of manufacture having reduced line-to-line capacitance.
Background of the Invention
Integration and miniaturization in integrated circuits has resulted in a reduction in spacing between features in the integrated circuit. This reduction has resulted in the intralevel conductor, or line-to-line capacitance (CL.L), being the dominant component of parasitic capacitance within the integrated circuit. Materials having a low dielectric constant are used often as the inter-layer dielectric (ILD) with the integrated circuit to help reduce line-to-line capacitance.
The problem of increased CL-L may affect dual damascene conductor structures which combine trenches and vias. Accordingly, low dielectric constant (low-k) materials are used in conjunction with dual damascene structures. One technique is to use a single layer of low-k dielectric for both the trench and via layers. While the use of a single low-k dielectric layer may aid in reducing the line-to-line capacitance, fabricating a dual damascene structure with a single low-k layer may be difficult. The process requires the trench etch to be extremely well controlled. The trench etch must have excellent within wafer and wafer-to-wafer uniformity and the etch rate must be independent of the trench width. Furthermore, the bottom of the trench must be made substantially flat. This is difficult to obtain using many conventional etch tools.
1 Another technique to incorporate low-k material in a dual damascene structure uses an etch-stop layer between the trench layer and the via layer (again the same material is used for both the trench and via layers). While the etch-stop layer enables a highly selective etch between the trench and via dielectric layers the etch stop process is relatively complicated. The etch stop layer adds another step to the deposition process and in many cases the deposition tools needed for the etch stop are not the same as those used for the deposition of the trench and via dielectrics. T'his increases processing time and cost. Finally, control of the three layer film stack is difficult since optical film thickness measurements commonly used are difficult to perform on such complex structures.
In addition to the drawbacks discussed above, many of the available low-k dielectric materials are soft compared to silicon oxide which can make processing difficult.
Accordingly, what is needed is a technique for fabricating low-k layers in integrated circuits.
Summ= of the Invention ne present invention relates to a process for fabricating a multi-layer dielectric that reduces line-to-line capacitance (CL-L). The process may include forming a first dielectric layer which provides support for a second dielectric layer formed thereover. The second dielectric layer is a low-k layer that may be formed between conductive elements such as metal runners. Etch selectivity between the two dielectric layers fosters the fabrication of interconnections between levels of a multilevel integrated circuit.
Brief Descp:pt !on of the Drawin The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that in accordance with common practice in the semiconductor industry, the various features are not necessarily to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity.
- 2 Figure I is a cross sectional view of an exemplary embodiment of the invention of the present disclosure.
Figures 2(a)-2(e) are cross-sectional views of an exemplary embodiment of the present invention showing a process sequence for its fabrication.
Figure 3 is an exemplary embodiment of the present invention.
Figure 4 is an exemplary embodiment of the present invention.
Detailed DescdLtion of the Invention Briefly, the present invention is a method of fabricating a multi-layer dielectric for use in an integrated circuit that reduces parasitic capacitance in the integrated circuit. Turning to Figure 1, a first dielectric layer 101 is formed over a substrate 100 and a second dielectric layer 102 is formed over the first dielectric layer 101. The first dielectric layer 101 provides structural support for the second dielectric layer and has good thermal conduction properties. The second dielectric layer is a low dielectric constant (low-k) materiaL The low-k layer 102 may be formed between conductive elements 103 to aid in the reduction in the parasitic capacitance therebetween.
In the exemplary embodiment shown in Figure 1, the present invention reduces CL-L between conductive elements 103 which may be metal runners. The first dielectric layer 10 1 may be referred to as the structural layer and the second dielectric layer 102 may be referred to as the low-k dielectric layer. In the exemplary embodiments shown in Figures 2(a)-(e), 3 and 4, dual darna cene structures with reduced line-to-line capacitance are disclosed. In embodiments drawn to dual damascene structures, the first dielectric layer may be referred to as the via dielectric because this is the layer where a via is formed; and the second dielectric layer in these embodiments may be referred to as the trench dielectric because a trench is formed in this layer. Finally, the exemplary fabrication techniques for forming the structure shown in Figure 1 are substantially the same as those used in connection with the exemplary embodiments discussed below.
- 3 Turning to Fig. 2 (a), the substrate 201 has conductive elements 202 disposed thereover by standard technique. The substrate may be a semiconductor such as silicon, GaAs, or SiGe; or a dielectric material as well as other materials used in fabricating integrated circuits. The via layer 203 is formed over the substrate 201 by conventional deposition techniques and has an exemplary thickness of 600 to 900 nm.
Illustratively, this layer is formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD). The via dielectric material is chosen for its mechanical, thermal and plasma etching characteristics. To this end, this layer provides mechanical stability/rigidity to the trench layer 204. The via layer 203 may also dissipate heat better than the trench dielectric material and etches at a different rate than the trench dielectric as discussed in detail below. Materials having a Young's modulus in the range of about 60 GPa to GPa and a thermal conductivity in the range of about 9.0 mW/cm-K to 17.0 mW/cm-K may be used as the via dielectric layer. Exemplary materials include but are not limited to silicon dioxide and fluorine doped silicon dioxide (also know as fluorosilicate glass (FSG)).
After formation of the via dielectric, the trench dielectric 204 is formed over the via dielectric in an exemplary thickness of 300 to 800 mn. The trench dielectric layer may be deposited by a standard spin-on technique, as well as by PECVD.
Exemplary trench dielectric materials include: a low dielectric organic polymer (e.g., SILK a registered trademark of the DOW Chemical Company); hybrido organo siloxane polymer (e. g., Allied Signal Corporation tradename HOSP); nanoporousous silicate glass (e. g., Allied Signal Corporation tradename Nanoglass); and organo silicate glass (e. g., Applied Materials Corporation tradename Black Diamond or Novellus Corporation tradename COREL). In the exemplary embodiment, the dielectric constant of layer 204 is less than the dielectric constant of layer 203.
Illustratively, trench layer 204 may have a dielectric constant on the order of 2.0 to 3.7. However, it is within the purview of the present invention to use materials as the trench dielectric 203 having a dielectric constant of less than 2.0. The low-k trench dielectric reduces the overall dielectric constant of the interlayer dielectric (ILD) thereby reducing the line-to-line capacitance as is desired.
Turning to Fig. 2 (b) the via 205 is shown. In the exemplary embodiment, etching of the via 205 is carried out by reactive ion etching. The etch may be done by known techniques to achieve a vertical etch profile. The via etch 4 process is terminated at or slightly before a bottom passivation layer (not shown) located over the conductive element 202. Finally, conventional chemistries used to etch silicon dioxide and FSG are used in the via etch step.
A layer of photoresist 206 is used to define the trench, as is shown in Fig. 2 (c). Turning to Fig. 2 (d)the trench 207 is shown having been etched illustratively by reactive ion etching using processes which provide a high degree of selectivity between the trench layer 204 and via layer 203. Accordingly, the complexity of having an etch stop layer as is needed by prior techniques may be foregone.
Illustrative etch chemistries for some of the exemplary materials are as follows. In the example when a purely organic material such as SILK@ is used for the trench layer 204 and the via layer is Si% or FSG, the use of etch chemistries cont i i g oxygen and hydrogen (but not fluorine) will produce etch selectivities on the order of 20: 1. When the trench layer 204 is nano glass (porous Si02) and the layer 203 is SiO2 or FSG, conventional oxide etch chemistries such as CBIF3/CF4 or C4F8/CO produce etch selectivities on the order of 4:1 between layers 204 and 203.
As a result of the etch selectivity improved control of the trench depth within a wafer and from wafer-to-wafer results. Furthermore, the etching of the trench 207 may be carried out to achieve a vertical etch profile. Finally, the trench etch may employ an endpoint detection technique known to those skilled in the art to terminate the etch just after reaching the via. The resulting dual damascene structure is shown in Figure 2 (e) after the via 205 and trench 207 are filled with a conductor 208 by standard techniques.
Turning to Fig. 3 and Fig. 4, alternative fabrication techniques within the purview of the present invention are shown. The materials and processes used to effect the alternative embodiment shown in Fig. 3 are substantially identical to that discussed in connection with the structure in which the full via is fabricated first. Fig. 3 shows an exemplary embodiment of the invention of the present disclosure in which a trench is fabricated through the selectivity between layers 203 and 204. After the etching of the trench layer 204 to form the trench 207, a via photoresist 301 is disposed and a full via 205 is etched. In the structure shown in Fig. 4, a partial via is formed as is shown at 401. Thereafter, a trench photoresist 402 is disposed over the - 5. - trench layer 204. A plasma etching step is thereafter carried out by standard technique resulting in a W via and trench being fabricated.
The invention having been described in detail, it is clear that modifications and variations are within the purview of one of ordinary skill in the art having the benefit of present invention. To the extent that such modifications are within the teaching of the present disclosure drawn to an integrated circuit and its method of fabrication having a reduce ILD dielectric constant through the use of a multi-layer dielectric structure such are within the purview of one of ordinary skill in the art.
6 -

Claims (23)

What is Claimed:
1. A process for fabricating an integrated circuit, the process 2 comprising:
3 forming a multi-layer dielectric over a substrate, said multi-layer 4 dielectric further comprising a structural layer and a low-k layer.
1
2. A process as recited in claim 1, wherein said low-k layer is formed 2 between at least two conductive elements.
1
3. A process as recited in claim 1, wherein said low-k layer has a 2 dielectric constant in the range of 2.0 to 3.7.
1
4. A process as recited in claim 1, wherein said low-k layer has a 2 dielectric constant of less than 2.0.
1
5. A process as recited in claim 1, wherein said low-k layer is chosen 2 from the group consisting of SILK@, HOSP, Nanoglass and Black Diamond.
1
6. A process as recited in claim. 1, wherein said structural layer is 2 chosen from the group consisting Of Si02 and fluorine doped silicon oxide.
1
7. A process as recited in claim. 1, wherein said structural layer has a 2 Young's modulus in the range of 60 GPa to 120 GPa.
1
8. A process for fabricating an integrated circuit, the process 2 comprising:
3 disposing a layer over a substrate; 4 disposing a low-k layer on said layer; etching a via in said layer; and 6 etching a trench in said low-k layer.
1
9. A process as recited in claim 8, wherein said low-k layer has a 2 dielectric constant in the range of 2.0 to 3.7.
1
10. Aprocess as recited in claim 8, wherein said low-k layer has a 2 dielectric constant less than 2.0.
3
11. A process as recited in claim 8, wherein said layer has a Young's 4 modulus in the range of 60 GPa to 120 GPa.
- 7
12. A process as recited in claim 8, wherein said layer etches more 6 slowly than said low-k layer.
1
13. A process as recited in claim 8, wherein at least one conductive 2 element is disposed between said substrate and said layer.
1
14. A process as recited in claim 8, wherein said low-k material is 2 chosen from the group consisting of SIILK@, HOSP, nanoglass and Black Diamond.
1
15. A process as recited in claim 8, wherein said layer is chosen from 2 the consisting0f Si02and fluorine doped silicon dioxide.
1
16. A process as recited in claim 8, wherein conductive material is 2 disposed in said via and in said trench.
1
17. A process for fabricating an integrated circuit, the process 2 comprising:
3 forming a multi-layer dielectric over a substrate, said multi-layer 4 dielectric having a low-k layer formed over a structural layer and directly on at least 5 one conductive element. 1
18. A process as recited in claim 17, wherein said at least one 2 conductive element is formed on said structural layer. 1
19. A process as recited in claim 17, wherein said low-k layer has a 2 dielectric constant in the range of 2.0 to 3.7. 1
20. A process as recited in claim 17, wherein said low-k layer has a 2 dielectric constant less than 2. 1
21. A process as recited in claim 17, wherein said low-k layer is chosen 2 from the group consisting of SILK@, HOSP, Nanoglass and Black Diamond. 1
22. A process as recited in claim 17, wherein said structural layer is 2 chosen from the group consisting of SiC and fluorine doped silicon oxide. 1
23. A process as recited in claim 17, wherein said structural layer has a 2 Young's modulus in the range of 60 GPa to 120 GPa.
GB0019969A 1999-08-30 2000-08-14 Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance Withdrawn GB2358734A (en)

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US38571499A 1999-08-30 1999-08-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019642A1 (en) * 2001-08-23 2003-03-06 Applied Materials, Inc. Etch process for dielectric materials comprising oxidized organo silane materials

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996013856A1 (en) * 1994-10-28 1996-05-09 Advanced Micro Devices, Inc. Layered low dielectric constant technology
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
GB2306778A (en) * 1995-10-30 1997-05-07 Nec Corp Interlayer insulator
GB2320809A (en) * 1996-12-28 1998-07-01 Hyundai Electronics Ind Forming a protective film in a semiconductor device
US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
EP0975017A2 (en) * 1998-07-22 2000-01-26 Siemens Aktiengesellschaft Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication
EP1024526A1 (en) * 1999-01-26 2000-08-02 Lucent Technologies Inc. An integrated circuit device having a planar interlevel dielectric layer
EP1077483A2 (en) * 1999-08-17 2001-02-21 Lucent Technologies Inc. Method of making an integrated circuit device having a planar interlevel dielectric layer

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
WO1996013856A1 (en) * 1994-10-28 1996-05-09 Advanced Micro Devices, Inc. Layered low dielectric constant technology
GB2306778A (en) * 1995-10-30 1997-05-07 Nec Corp Interlayer insulator
US5886410A (en) * 1996-06-26 1999-03-23 Intel Corporation Interconnect structure with hard mask and low dielectric constant materials
GB2320809A (en) * 1996-12-28 1998-07-01 Hyundai Electronics Ind Forming a protective film in a semiconductor device
EP0975017A2 (en) * 1998-07-22 2000-01-26 Siemens Aktiengesellschaft Silicon oxynitride cap for fluorinated silicate glass film in intermetal dielectric semiconductor fabrication
EP1024526A1 (en) * 1999-01-26 2000-08-02 Lucent Technologies Inc. An integrated circuit device having a planar interlevel dielectric layer
EP1077483A2 (en) * 1999-08-17 2001-02-21 Lucent Technologies Inc. Method of making an integrated circuit device having a planar interlevel dielectric layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019642A1 (en) * 2001-08-23 2003-03-06 Applied Materials, Inc. Etch process for dielectric materials comprising oxidized organo silane materials
US6762127B2 (en) 2001-08-23 2004-07-13 Yves Pierre Boiteux Etch process for dielectric materials comprising oxidized organo silane materials

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JP2001110901A (en) 2001-04-20
KR20010030168A (en) 2001-04-16
GB0019969D0 (en) 2000-10-04

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