CN1187027A - Method of forming protective film in semiconductor device - Google Patents
Method of forming protective film in semiconductor device Download PDFInfo
- Publication number
- CN1187027A CN1187027A CN97125706A CN97125706A CN1187027A CN 1187027 A CN1187027 A CN 1187027A CN 97125706 A CN97125706 A CN 97125706A CN 97125706 A CN97125706 A CN 97125706A CN 1187027 A CN1187027 A CN 1187027A
- Authority
- CN
- China
- Prior art keywords
- film
- sog film
- sog
- metal line
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000001681 protective effect Effects 0.000 title abstract 2
- 239000002184 metal Substances 0.000 claims abstract description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 8
- 125000002947 alkylene group Chemical group 0.000 claims description 8
- 208000034189 Sclerosis Diseases 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- NCWQJOGVLLNWEO-UHFFFAOYSA-N methylsilicon Chemical compound [Si]C NCWQJOGVLLNWEO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 15
- 238000000151 deposition Methods 0.000 abstract description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000000576 coating method Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- -1 methylsiloxane Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 150000004760 silicates Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical group [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- WCYWZMWISLQXQU-UHFFFAOYSA-N methyl Chemical compound [CH3] WCYWZMWISLQXQU-UHFFFAOYSA-N 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming a protective film which can decrease a parasitic capacitance between metal wires of a semi-conductor device and improve vulnerable area,the method comprises the steps of forming metal wires on a substrate depositing a silicon oxide film on the substrate including the metal wires, forming a SOG film on the silicon oxide film, hardening the SOG film and then forming a silicon nitride film on the SOG film. The SOG film, which may be etched, is formed of a material having a lower dielectric constant than that of the silicon oxide film, e.g. methyl-silsesquioxane or hydrogen-silsesquioxane.
Description
The present invention relates to form in semiconductor device the method for diaphragm, this diaphragm can reduce the parasitic capacitance between metal line.
In general, the diaphragm in the semiconductor device is by silicon oxide film and silicon nitride film is stacked forms, and is formed by plasma deposition.The influence that diaphragm can protect semiconductor device not changed by external environment.Yet, because silicon oxide film (dielectric constant k=4.3) and silicon nitride film (dielectric constant k=6～8) have high dielectric constant, if the interval between metal width and metal line is less than 1 μ m, parasitic capacitance between the wiring then increases fast so, thus produce signal mutually in disturbing and signal transmits time-delay characteristics.Therefore, the operating characteristic of device degenerates.
Degenerate by the device property that causes of parasitic capacitance between wiring and to occur in mostly in the device of high speed operation.In addition, form diaphragm after owing to cover variation corresponding to the height of metal line and the step of the spacing between metal line, metal line produce vulnerable area than lower part, therefore reduced the reliability of device.
Figure 1A is the device profile map that forms metal line in it, and Figure 1B is the equivalent circuit diagram of the parasitic capacitance between metal line among Figure 1A.Metal line 12 is formed on the substrate 11, at this moment, is 1 air owing to there is dielectric constant between the metal line 12, so the parasitic capacitance between the metal line 12 can be thought desirable parasitic capacitance.
Fig. 2 A is the device profile map that forms the GPF (General Protection False film in it.Silicon oxide film 23 and silicon nitride film 24 are formed on the substrate 21 that comprises metal line 22.
Fig. 2 B is the equivalent circuit diagram of the parasitic capacitance between metal line among Fig. 2 A.Parasitic capacitance between the metal line 22 is proportional to metal line and dielectric constant, and is inversely proportional to the distance between metal line.Therefore, because oxide-film 23 has high-k (k=4.3) and nitride film 24 has high-k (k=8),, therefore produce the phase mutual interference so the parasitic capacitance between metal line increases.Particularly, the peripheral circuit that applies around the circuit of driving voltage is subjected to very big influence.In addition, shown in Fig. 2 A,, produce vulnerable area W at the thinner thickness of the bottom of metal line 22 oxide-film 23 and nitride film 24, thereby the performance degradation of diaphragm.
Therefore, the purpose of this invention is to provide a kind of method that forms diaphragm, this diaphragm can reduce the parasitic capacitance between metal line and improve its vulnerable area.
For reaching this purpose, the method that forms diaphragm may further comprise the steps: form the metal line of substrate, comprising silicon oxide deposition film on the substrate of metal line, form sog film on silicon oxide film, the sclerosis sog film forms silicon nitride film then on sog film.
Sog film is formed by the lower material of permittivity ratio silicon oxide film, and is formed by one of methyl-silicon sesquialter alkylene oxide and hydrogen-silicon sesquialter alkylene oxide.
By other purpose of the present invention and advantage being understood in the detailed briefing of embodiment below in conjunction with accompanying drawing.
Figure 1A is for being formed with the device profile map of metal line in it;
Figure 1B is the equivalent circuit diagram of device among Figure 1A;
Fig. 2 A is for being formed with the device profile map of GPF (General Protection False film in it;
Fig. 2 B is the equivalent circuit diagram of device among Fig. 2 A;
Fig. 3 A is the device profile map that forms diaphragm according to the first embodiment of the present invention;
Fig. 3 B is the equivalent circuit diagram of device among Fig. 3 A;
Fig. 3 C is for forming the device profile map of diaphragm according to a second embodiment of the present invention;
Fig. 4 is for being used as the chemical structural formula table of the material of SOG among explanation prior art and the present invention;
Fig. 5 is for using the rate of finished products comparison diagram of GPF (General Protection False film and diaphragm of the present invention.
Fig. 3 A is the device profile map that forms diaphragm according to the first embodiment of the present invention.
Thin silicon oxide film 33 is deposited on the substrate 31 that comprises metal line 32.SOG (spin-coating glass) film 34 with low-k (k=3) is coated on the silicon oxide film 33, then sclerosis.Silicon nitride film 35 is deposited on the sog film 34.When deposit sog film 34, rotation substrate 31.Therefore, since the flowability of SOG, the surface planarization of sog film 34, and do not have the space in the sog film 34.That is, the density of sog film 34 becomes higher.
For the oily material in the sog film 34 that vapors away coating, the sog film 34 to coating under 90 to 400 ℃ temperature bakes technology.At this moment, can be according to the characteristic changing temperature of oily material and SOG.Under 400 to 500 ℃ temperature, carry out hardening process, with the chemical bond of the sog film 34 of firm coating.In addition, on sog film 34, form silicon oxide film, so that sog film 34 does not absorb moisture, and the reliability of raising device.
Silicon nitride film 35 is used as last diaphragm, and is deposited on equably on the sog film 34 with excellent planar characteristic.Yet, as shown in Figure 3A,, therefore do not produce the vulnerable area of silicon nitride film 35 because the flowability of sog film 34 does not produce topological structure (topology) in vertical direction.Owing to there is a silicon nitride film 35, the ability that makes the protection semiconductor device not influenced by the external environment such as the intrusion of external pressure and moisture etc. strengthens.
Fig. 3 B is the equivalent circuit diagram of device among Fig. 3 A.Compare as can be seen with Fig. 2 B, owing to use sog film 34 with low-k (k=3) and the oxide-film 33 with high-k (k=4.3), the parasitic capacitance between metal line is greatly improved than prior art.
Fig. 3 C is for forming the device profile map of diaphragm according to a second embodiment of the present invention.
Thin silicon oxide film 43 is deposited on the substrate 41 that comprises metal line 42.Sog film 44 with low-k (k=3) is coated on the silicon oxide layer 43, then sclerosis.Afterwards, sog film 44 is carried out dry etching, so that expose the silicon oxide film 43 that is formed on the metal line 42.
As can be seen, be formed on the more complanation of silicon nitride film 45 on the sog film 44, and can prevent that moisture from entering in the sog film 44.
Certainly, the parasitic capacitance between the metal line 42 is identical with parasitic capacitance between the metal line 32 shown in Fig. 3 B.
Fig. 4 has shown the chemical structural formula that is used as the material of SOG among prior art and the present invention.
In the present invention, use the methyl-silicon sesquialter alkylene oxide of a kind of hydrocarbon displaced type SOG or the hydrogen of a kind of hydrogen displaced type SOG-silicon sesquialter alkylene oxide as low dielectric SOG.The dielectric constant of the SOG that uses among the present invention (k) is 3 or lower, and the dielectric constant of methylsiloxane class and silicates (k) is 3.8 or higher.Strong polarization characteristic by between the silicon-oxygen atom of methyl (methyl radical) or hydrogenation improvement routine obtains hydrocarbon displaced type SOG and hydrogen displaced type SOG.
According to the height of metal line and the interval between metal line, under different conditions, hang down the coating process of dielectric SOG.
Fig. 5 for when formation GPF (General Protection False film and according to the present invention respectively by dielectric constant be 3.8 or first diaphragm that forms of the SOG of higher siloxanes and silicate sturcture and by dielectric constant be 3 or lower methyl-silsesquioxane or hydrogen-silsesquioxane form second diaphragm time the comparison diagram of rate of finished products.
As can be known from Fig. 5, when forming according to diaphragm of the present invention, rate of finished products has increased about 2.25 times than conventional diaphragm.
In the present invention, as mentioned above, the SOG that is used to form diaphragm and has a low-k has good complanation and filling characteristic, therefore can obtain stable diaphragm.Because SOG has low-k, the parasitic capacitance between metal line can minimize, so the reliability of device strengthens.
Though the preferred embodiment of introducing has particularity to a certain degree, principle of the present invention has only been introduced in above explanation.Should be appreciated that the present invention is not limited to preferred embodiment open and that introduce here.Therefore, all distortion of making in scope and spirit of the present invention all comprise in other embodiments of the invention.
Claims (8)
1. in semiconductor device, form the method for diaphragm, may further comprise the steps:
Form the metal line of substrate;
Comprising silicon oxide deposition film on the described substrate of described metal line;
Form sog film on described silicon oxide film, described sog film is formed by the lower material of the described silicon oxide film of permittivity ratio;
The described sog film that hardens forms silicon nitride film then on described sog film.
2. according to the process of claim 1 wherein before carrying out cure step dry described sog film under 90 to 400 ℃ temperature.
3. according to the process of claim 1 wherein the described sog film of sclerosis under 400 to 500 ℃ temperature.
4. according to the process of claim 1 wherein that described sog film is formed by one of methyl-silicon sesquialter alkylene oxide and hydrogen-silicon sesquialter alkylene oxide.
5. in semiconductor device, form the method for diaphragm, may further comprise the steps:
Form the metal line of substrate;
Comprising silicon oxide deposition film on the described substrate of described metal line;
Form sog film on described silicon oxide layer, described sog film is formed by the lower material of the described silicon oxide film of permittivity ratio;
The described sog film that hardens, the part of corroding described sog film then; And
On described sog film, form silicon nitride film.
6. according to the method for claim 5, wherein before carrying out cure step, dry described sog film under 90 to 400 ℃ temperature.
7. according to the method for claim 5, described sog film wherein hardens under 400 to 500 ℃ temperature.
8. according to the method for claim 5, wherein said sog film is formed by one of methyl-silicon sesquialter alkylene oxide and hydrogen-silicon sesquialter alkylene oxide.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR74957/96 | 1996-12-28 | ||
| KR74957/1996 | 1996-12-28 | ||
| KR1019960074957A KR19980055721A (en) | 1996-12-28 | 1996-12-28 | Method of forming protective film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1187027A true CN1187027A (en) | 1998-07-08 |
| CN1113398C CN1113398C (en) | 2003-07-02 |
Family
ID=19491706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97125706A Expired - Fee Related CN1113398C (en) | 1996-12-28 | 1997-12-25 | Method of forming protective film in semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH10199877A (en) |
| KR (1) | KR19980055721A (en) |
| CN (1) | CN1113398C (en) |
| DE (1) | DE19757879A1 (en) |
| GB (1) | GB2320809B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444331C (en) * | 2003-11-11 | 2008-12-17 | 三星电子株式会社 | Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2358733A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Integrated circuit with multi-layer dielectric having reduced capacitance |
| GB2358734A (en) * | 1999-08-30 | 2001-08-01 | Lucent Technologies Inc | Process for fabricating integrated circuit with multi-layer dielectric having reduced capacitance |
| WO2005122227A1 (en) | 2004-06-08 | 2005-12-22 | Koninklijke Philips Electronics, N.V. | Reduction of cracking in low-k spin-on-dielectric films |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501872B1 (en) * | 1970-01-30 | 1975-01-22 | ||
| US4091407A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
| WO1987002828A1 (en) * | 1985-11-04 | 1987-05-07 | Motorola, Inc. | Glass intermetal dielectric |
| US5057897A (en) * | 1990-03-05 | 1991-10-15 | Vlsi Technology, Inc. | Charge neutralization using silicon-enriched oxide layer |
| US5374833A (en) * | 1990-03-05 | 1994-12-20 | Vlsi Technology, Inc. | Structure for suppression of field inversion caused by charge build-up in the dielectric |
| KR970052338A (en) * | 1995-12-23 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
-
1996
- 1996-12-28 KR KR1019960074957A patent/KR19980055721A/en not_active Application Discontinuation
-
1997
- 1997-12-23 GB GB9727080A patent/GB2320809B/en not_active Expired - Fee Related
- 1997-12-24 DE DE19757879A patent/DE19757879A1/en not_active Ceased
- 1997-12-25 CN CN97125706A patent/CN1113398C/en not_active Expired - Fee Related
- 1997-12-26 JP JP9370264A patent/JPH10199877A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100444331C (en) * | 2003-11-11 | 2008-12-17 | 三星电子株式会社 | Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2320809B (en) | 2001-09-12 |
| GB9727080D0 (en) | 1998-02-18 |
| CN1113398C (en) | 2003-07-02 |
| GB2320809A (en) | 1998-07-01 |
| GB2320809A8 (en) | 1998-08-04 |
| KR19980055721A (en) | 1998-09-25 |
| DE19757879A1 (en) | 1998-07-02 |
| JPH10199877A (en) | 1998-07-31 |
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Granted publication date: 20030702 Termination date: 20100125 |