GB2263018A - Static random access memories - Google Patents

Abstract

A static random access memory comprises a semiconductor device wherein a conductive layer (33) is separated from a semiconductor layer (35), which has semiconductor elements (35a, 35b) formed therein, by an insulator film (34). The conductive layer (33) is connected to the semiconductor elements (35a, 35b) via contact holes (36) in the insulator film (34), thereby forming a wiring arrangement. The wiring layer extends over the entire surface and provides a low resistance power supply wiring to the memory cells. <IMAGE>

Description

STATIC RANDOM ACCESS MEMORIES This invention relates to semiconductor memory devices of the static random access type.

Static random access memories (SRAMs) are classified into high-resistance load type, TFT load type and full CMOS type. The former two types are advantageous in that the memory cell size is reducible, and therefore these types are dominant among recent 4-Mbit and 16-Mbit SRAMs.

In comparison therewith, the cell size in a full CMOS type SRAM tends to be greater, because six MOS transistors are required per cell.

In any SRAM of the high-resistance load type or TFT load type, it is difficult to enhance the operating stability of each cell and the soft error tolerance. However, the full CMOS type SRAM has an advantage that the operating stability of each cell and the soft error tolerance can be enhanced. It is therefore urgently required to increase the integrating density of the full CMOS type SRAM. To meet this requirement, it is preferred that an SRAM be formed as an SOI type semiconductor device, because in an SOI layer, a P-channel MOS transistor and an n-channel MOS transistor can be formed close together. However, as reduction of both the width of each MOS transistor and the interval between adjacent MOS transistors is restricted by the resolution of photolithography, it has been impossible heretofore to attain sufficiently high-density integration.

In an SRAM, it is necessary to supply power to each memory cell. When data are written in a memory cell. a current flows from a power line to a bit line via a load means (a high resistance load or a load MOS transistor) and a switching (word) MOS transistor. The current reaches its maximum at the data writing time, and consequently a voltage drop is caused in the power line. Such voltage drop is equivalent to the product of the maximum current and the parasitic resistance of the power line, and it is necessary to minimize the value of this voltage drop.

In an SRAM where the load is a high-resistance element of polycrystalline silicon, the current flowing from the power line to the bit line at the data writing time can be sufficiently reduced since the load has a high resistance value. Thus the power line may be formed of polycrystalline silicon, whose sheet resistivity is relatively high.

Meanwhile, in a full CMOS type SRAM where an n-channel MOS transistor is employed as a driver transistor and a p-channel MOS transistor as a load transistor, the current I flowing at the writing time becomes large, because the load consists of a p-channel MOS transistor. Therefore a large voltage drop occurs in the power line, unless the resistance R of the power line is reduced to an extremely small value. Although such a full CMOS type SRAM has this problem of a large voltage drop in the power line, there also exists the advantages of superior operating stability of each cell and a high soft error tolerance.

In an exemplary case of a 4-Mbit full CMOS type SRAM where the current I flowing in one cell at a data writing time is approximately 60 pA, the maximum voltage drop caused in a power line is: AV =8RI Multiplication by eight occurs because the data are written in 8-bit cells simultaneously.

The maximum permissible value of the voltage drop AV caused in the power line is not so great is there are taken into consideration the supply voltage variations and the conditions (determined principally by the current driving capabilities of both transistors in the inverter) where an inverter (forming a flip-flop) in the memory cell performs its proper function.

Supposing now that the maximum permissible voltage drop is 1V, the resistance R of the power line to satisfy this condition is: R s 1/8 . I ? 2000 (#) This signifies that the resistance R of the power line needs to be less than 2kQ, although in practice the resistance R should be smaller than ikon.

Referring to Figure 1, in a full CMOS type SRAM, therefore, it is customary for a power line 1 for supplying power directly to cells a1, a2 .... an to be of aluminium as is a power line 2. However, if the power lines 1 and 2 are both aluminium, it follows that the area occupied by the cell array is large, with consequent poor integration density.

This technical difficulty results from the fact that some other elements to be formed of a first aluminium film lAl also exist in the SRAM. It is generally customary that bit lines are formed of a second aluminium film 2A1, whereas an earth line and a main word line need to be formed of the first aluminium film lAl.

In a case where a main word line is formed of an aluminium film lAl, it is usual for a word line to be formed of polycrystalline silicon. However, in an SRAM based on a divided word line system, a main word line is formed of an aluminium film lAl, while a section word line is formed of polycrystalline silicon. In any 1-Mbit or 4 Mbit SRAM, the divided word line system is adopted. Thus, where the power line for supplying a required voltage directly to each memory cell is formed of an aluminium film lAl, it is difficult to attain a higher integration density.

According to the invention there is provided an SRAM comprising a semiconductor device wherein a conductive layer is formed, through an insulator film, substantially on one entire surface of a semiconductor layer with semiconductor elements formed therein, and said conductive layer is connected to said semiconductor elements via contact holes in said insulator film, thereby forming a wiring arrangement.

Embodiments of the invention can provide an SRAM wherein a low-resistance wiring arrangement reduces the parasitic resistance of a power line and an earth line even where using a material of large sheet resistivity.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a plan view of elements in a known semiconductor memory device; Figures 2(A) to 2(D) are sectional views representing sequential process steps of a method of manufacturing a full CMOS type SRAM; Figure 3(A) is a plan view of a layout; Figure 3(B) is a circuit diagram of memory cells shown in Figure 3(A); Figures 4(A) and 4(B) graphically show the relationship between the width (Wd) of a driver MOS transistor, a node potential and the threshold voltage of an inverter; Figure 5(A) is a sectional view of elements in an embodiment where the semiconductor device of the present invention is applied to a full CMOS type SRAM; and Figure 5(B) is a plan view of the elements of Figure 5(A).

Referring first to Figure 2(A), in manufacturing a full CMOS type SRAM, a first mask layer 13 of SiO2 is formed on the entire surface of an SOI layer 11, and the first mask layer 13 is etched to be patterned while being masked with a resist film 14. The first mask layer 13 has a pattern and size suited to obtain semiconductor island layers where a driver MOS transistor (width B) and a load MOS transistor (width A) are to be formed. An insulator film 12 serves as a foundation for the SOI layer 11. Figure 2(A) illustrates the state after the step of patterning the first mask layer 13.

Subsequently, in Figure 2(B), the resist film 14 is removed, and then a second mask layer 15 of Si3N4 is formed. Thereafter the second mask layer 15 is etched while being masked with a resist film 16. The second mask layer 15 is so patterned as to cover a region where one of a driver MOS transistor and a load MOS transistor, for example a load MOS transistor, is to be formed, but not to cover a portion which serves as an isolating region between the driver MOS transistor and the load MOS transistor. Consequently the overlapped portion of the semiconductor island layer 13 and the second mask layer 15 becomes a region where either the driver MOS transistor or the load MOS transistor, the load MOS transistor in this embodiment, is to be formed. Figure 2(B) illustrates the state after the step of the etching the second mask layer 15.

Next, in Figure 2(C), the resist film 16 is removed, and then another resist film 17 is selectively formed. The resist film 17 is so patterned as completely to cover a region where the other of the driver MOS transistor and the load MOS transistor, for example the driver MOS transistor in this embodiment, is to be formed, but not to cover a portion 18 which serves as an isolating region between the driver MOS transistor and the load MOS transistor.

Thereafter the first mask layer 13 is etched while being masked with both the resist film 17 and the second mask layer 15, whereby the portion corresponding to the isolating region between the driver MOS transistor and the load MOS transistor on the first mask layer 13 is removed. A portion 13a is used to mask the region of the first mask layer 13 for forming one of the driver MOS transistor and the load MOS transistor, the load MOS transistor in this embodiment; while a portion 13b is used to mask the region of the first mask layer 13 for forming the other of the driver MOS transistor and the load MOS transistor, the driver MOS transistor in this embodiment. Figure 2(C) illustrates the state after the step of forming the portions 13a and 13b by selectively etching the first mask layer 13.

Subsequently, in Figure 2(D), the resist film 17 is removed, and the second mask layer 15 is also removed. Then the semiconductor layer 11 is etched while being masked with the first mask layer 13, thereby forming a semiconductor island layer lia where the load MOS transistor is to be formed, and also a semiconductor island layer lib where the driver MOS transistor is to be formed. An isolating region 18 is formed between the semiconductor island layers lla and llb.

Figure 2(D) illustrates a state after the step of etching the semiconductor layer 11. In this specification, the semiconductor island layer is defined as an isolated island-shaped semiconductor which is independent of any other semiconductor, and there exists no distinction in the definition as to whether it is an SOI layer or a polycrystalline silicon layer.

Figure 3(A) is a plan view of a principal component layout in an exemplary SOI type SRAM embodying the semiconductor device of the present invention. In this diagram, a two-dot chained line denotes an island formed of an SOI layer, while a one-dot chained line denotes gates of a driver MOS transistor Qn and a load MOS transistor Qp formed of polycrystalline silicon, and another one-dot chained line denotes a section word line including a gate of a switching MOS transistor Qw. Further a broken line denotes a first aluminium film lAl, while a solid line denotes a second aluminium film 2Al.

A wiring layer to be in contact with a source of the load MOS transistor Qp is composed of a polycrystalline silicon layer below the SOI layer formed on the entire surface under a memory cell array, and therefore such wiring layer does not appear in Figure 3.

Although an n-type impurity is diffused in both sources and drains of the driver MOS transistor Qn and the switching (word) MOS transistor Qw, with the gates thereof being used as a mask, such impurity-diffused regions are not shown.

With this method of manufacturing a full CMOS type SRAM, the width C of the semiconductor island layer with the driver MOS transistor and the load MOS transistor formed therein is determined by the single photolithographic step shown in Figure 2(A). The width C is the sum of the width A of the semiconductor island layer lla with the load MOS transistor, the width B of the semiconductor island layer lib with the driver MOS transistor, and the width D of the isolating region between the load MOS transistor and the driver MOS transistor.

Meanwhile the width A of the semiconductor island layer lla with the load MOS transistor formed therein is determined by the positional relationship between the resist film 14 in the step (A) and the resist film 6 in the step (B). This width A can be reduced beyond the limit based on the photolithographic resolution.

Similarly the width D of the isolating region between the load MOS transistor and the driver MOS transistor is determined by the positional relationship between the resist film 16 in the step (B) and the resist film 17 in the step (C), and such width D can also be reduced beyond the limit based on the photolithographic resolution.

Furthermore, the width B of the semiconductor island layer lib with the driver MOS transistor is determined by the positional relationship between the resist film 14 in the step (A) and the resist film 17 in the step (C), and the width B can also be reduced beyond the limit based on the photolithographic resolution.

Thus, the width A of the semiconductor island layer lla, the width D of the isolating region 18 between the load MOS transistor and the driver MOS transistor, and the width B of the semiconductor island layer llb with the driver MOS transistor are not determined by the single lithographic step respectively, but are determined by the positional relationship between the resist films 14, 16 and 17 which are formed by mutually different lithographic steps, so that each of such widths can be narrowed beyond the limit of the photolithographic resolution. Consequently it becomes possible to diminish the area occupied by the memory cells, hence realizing an enhanced integration density of the SRAM.

It is unavoidable that, due to masking errors, some slight variations are induced in the width A of the semiconductor island layer lla with the driver MOS transistor, and also in the width B of the semiconductor island layer lib with the load MOS transistor.

However, there exists no possibility that any harmful influence from such slight variations is exerted on the operation of the memory cell.

This point will now be described in detail.

The problem relative to the memory cell operation arises as follows in an exemplary case of reading out a "O" level signal from the node 21 shown in Figure 3(B). When a word MOS transistor Qwl for example is turned on, a current flows into the node 21 from a bit line B charged to a "1" level, whereby the potential at the node 21 is raised. If such potential exceeds the threshold voltage of the inverter, then the driver MOS transistor for the inverter on the opposite side with respect to the inverter having the node 21 is turned on consequently to invert the data in the memory cell.

Therefore it is necessary to prevent the potential from rising above the threshold voltage.

The raised potential at the node 21 is determined by the ratio of the driving capability of the driver MOS transistor Onl to that of the word MOS transistor Qwl, and the threshold voltage of the inverter is determined by the threshold voltage of the driver MOS transistor Qnl and that of the load MOS transistor Qpl.

Assume here that the driver MOS transistor (nMOS) and the load MOS transistor (pMOS) and the word MOS transistor (nMOS) have the following dimensions of width (W) and length (L) in pm. The numerical values enclosed with parentheses signify variations derived from masking errors.

Driver MOS transistor (nMOS): 0.44 (+0.21); 0.6 Load MOS transistor (pMOS) : 0.24 ((+0.15); 0.6 Word MOS transistor (nMOS) : 0.39; 0.6 Under such conditions, the raised potential at the node and the threshold voltage of the inverter mentioned above have the dependency of Figure 4 upon the width (Wd) of the driver MOS transistor. More specifically, the graphic representation of Figure 4 indicates that the node potential v, is raised in accordance with a decrease of the width (Wd) of the driver MOS transistor, but the variation in the width of the semiconductor island layer can be rendered free from exerting harmful influence upon the memory cell operation by properly setting the threshold voltage VTO of the word transistors Qwl and Qw2 to an adequate high value.

The dependency of the node potential VK and the threshold voltage Vth upon the width Wd of the driver MOS transistor graphically shown in Figure 4(A) represents the characteristics specific to the pattern arrangement of Figure 3.

Since the n-channel and p-channel MOS transistors of two inverters constituting a memory cell are disposed as shown in Figure 3, the harmful influence of the masking errors to the width of the pchannel MOS transistor for example is reversed with respect to each inverter. Therefore, the margin of the cell operation can be set to a greater value, as shown graphically in Figure 4(B), by changing the memory cell disposition in such a manner that the aforementioned influences from the masking errors are equalized.

As described above, the method of manufacturing a full CMOS type SRAM comprises the steps of forming a first mask layer on a semiconductor layer, and patterning the first mask layer by photolithography to form semiconductor island layers where a driver MOS transistor and a load MOS transistor are formable while being slightly spaced apart from each other, forming a second mask layer on the semiconductor layer inclusive of the first mask layer, and patterning the second mask layer of photolithography in such a manner as to overlap the region where one of the driver MOS transistor and the load MOS transistor in the first mask layer is formed, but not to overlap the isolating region between the driver MOS transistor and the load MOS transistor; masking, with a resist film, the region where the other of the driver MOS transistor and the load MOS transistor in the first mask layer is formed, and etching the first mask layer while masking the same with the resist film and the second mask layer; and etching the semiconductor layer while masking the same with the first mask layer, thereby forming mutually isolated semiconductor island layers where the driver MOS transistor and the load MOS transistor are formed respectively.Therefore, it becomes possible to determine the width of each semiconductor island layer, which includes the driver MOS transistor or the load MOS transistor therein, in conformity with the positional relationship between the resist masks formed by mutually different lithographic steps, hence realizing reduction of the width of each semiconductor island layer and the space of the isolating region beyond the limit based on the photolithographic resolution.

A second embodiment of the present invention will now be described in detail.

Figures 5(A) and 5(B) illustrate an example of applying the present invention to an SOI type full CMOS SRAM. In these diagrams, (A) is a sectional view of principal component elements, and (B) is a plan view thereof.

Also shown are an SOI substrate 31 composed of silicon Si, an insulator layer 32, and a wiring layer 33 of polycrystalline silicon serving as a power wiring arrangement to supply therethrough a required current from a power line 37 of aluminium to each memory cell. Namely, the wiring layer 33 functionally corresponds to the power line 1 shown in the example of Figure 1.

The wiring layer 33 of polycrystalline silicon is formed substantially on the entire surface in such a manner as to cover on the entire surface in such a manner as to cover at least the region where a memory cell array is existent, so that the resistance R of the power line can be diminished despite the relatively high sheet resistivity.

Further shown are an insulator film 34 formed as a foundation for the SOI layer formed on the wiring layer 33 of polycrystal silicon; a silicon dioxide layer 35 provided to isolate the SOI layer and furnished with MOS transistors; a source 35a of a p-channel MOS transistor in one memory cell formed in the SOI isolating layer 35; and a source 35b of an n-channel MOS transistor.

A contact hole 36 is formed in the insulator film 34. The source 35a of the p-channel MOS transistor is connected to the wiring layer 33 through the contact hole 36.

A power line 37 of a second aluminium film 2Al [ not shown in Figure 5(A) ] and connected to the wiring layer 33 through the contact holes 38, 38 .... formed in the insulator film 34 Currents i, i ....

in the individual portions towards the source of one load MOS transistor Qp taken here as an example. The sum of such currents amounts to a write current I.

Thus, in this SRAM, the wiring layer 33 is provided under the insulator film 34, which serves as a foundation for the SOI layer 35, in a manner to be laid substantially throughout the entire surface below at least the memory cell array, whereby the wiring layer 33 is rendered extremely wide. Consequently it becomes possible sufficiently to reduce the resistance of the power line even when the wiring layer 33 is formed of a conductive material having a relatively high sheet resistivity, such as polycrystalline silicon. As a result, there is eliminated the known disadvantage that the width of the power line is limited by the earth line or the section word line as observed in the prior art, hence realizing an improved structure where the wiring layer is laid on the entire surface, enabling the power line to be widened.

The power line resistance R in this embodiment is expressed as: R ,- (Ps/21r) ln (L-r)/r where Ps is the sheet resistivity of the polycrystalline silicon layer 33; L is the distance between the aluminium power lines 38, 38; and r is the radius of the contact hole 36 through which the source 35a of the p-channel load MOS transistor Qp is connected to the wiring layer 33. Where L=460.8 pm (in 128 bits), r=0.3 pm and Ps=300 Q/square, the power line resistance R can be reduced to the small value of about 350Q. Such value completely satisfies the aforementioned condition of R > lkn.

Thus, the power line need not be composed of the first aluminium film lAl, and the requirement in the memory cell array region is to form merely a backing word line and an earth line by using the first aluminium film lAl, hence attaining a higher integration density.

Attention is drawn to our copending application 9206123.3 (2 254 487) on which the present application is divided, and which describes and claims similar subject matter.

Claims (5)

1. An SRAM comprising a semiconductor device wherein a conductive layer is formed, through an insulator film, substantially on one entire surface of a semiconductor layer with semiconductor elements formed therein, and said conductive layer is connected to said semiconductor elements via contact holes in said insulator film, thereby forming a wiring arrangement.

2. An SRAM according to claim 1 wherein said conductive layer is used as a power wiring arrangement of an earth wiring arrangement in said semiconductor device.

3. An SRAM according to claim 1 or claim 2 wherein said conductive layer is formed under an insulator film which serves as a foundation for an SOI layer.

4. An SRAM substantially as hereinbefore described with reference to Figures 2 and 3 or Figure

5.