JPH04294576A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the resistance of wiring by forming a conductive layer in a nearly whole area of one surface of a semiconductor layer on which a semiconductor element is formed with an insulating film in between and making the wiring by connecting the conductive layer with the semiconductor element through a contact hole formed through the insulating film. CONSTITUTION:The principal part of this semiconductor device is constituted of an SOI substrate 1 made of silicon (Si), wiring layer 3 made of polycrystalline silicon, insulating film 4, semiconductor layer 5, contact hole 6, etc. In the layer 5, the source 5a of a p-channel MOS transistor and source 5b of an n-channel MOS transistor are formed and the sources 5a and 5b are connected to the layer 3 through the hole 6. The wiring layer 3 is formed below the entire area of the semiconductor layer 5. Therefore, the width of the layer 3 becomes broader and the resistance of power supply lines can be lowered.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which wiring with low resistance can be obtained even when formed of a material with high sheet resistance.

0002

2. Description of the Related Art In an S (static) RAM, power must be supplied to each memory cell. When writing data into a memory cell, a current flows from the power supply line to the bit line via the load means (high resistance load or load MOS transistor) and the switching (word) MOS transistor. Then, the current that flows when writing becomes the largest value, and a non-negligible voltage drop occurs in the power supply line, which is the product of this current and the parasitic resistance of the power supply line, and the value of this voltage drop is reduced. There is a need to do so.

However, in the case of a type of SRAM in which the load is formed of a high resistance element made of polysilicon, the load is high resistance, so the current flowing from the power supply line to the bit line during writing can be made sufficiently small, so the power supply line has a sheet resistance. There is no problem even if polycrystalline silicon is used, which cannot be said to be sufficiently small. The power supply line is actually made of polycrystalline silicon.

On the other hand, full CMOS type SR
In the case of an AM, that is, an SRAM that uses an n-channel MOS transistor as a drive transistor and a p-channel MOS transistor as a load transistor, the current I that flows during writing becomes considerably large because the load consists of a p-channel MOS transistor. Therefore, unless the resistance R of the power supply line is made considerably small, the voltage drop in the power supply line will become large. Full C like this
Although MOS type SRAMs have the problem of a large voltage drop in the power supply line, they have extremely large advantages such as stable cell operation and high resistance to soft errors.

[0005] By the way, 4M full CMOS type SRAM
For example, if the current I flowing through one cell during writing is approximately 60 μA, the maximum voltage drop ΔV on the power supply line is expressed by the following equation. ΔV=8RI Note that RI is multiplied by 8 because 8-bit cells are written at the same time.

On the other hand, the conditions for normal operation of the inverter (inverter constituting a flip-flop) in the memory cell (mainly the threshold voltage Vt of the drive MOS transistor)
The maximum permissible value of the voltage drop ΔV on the power supply line is not very large, taking into consideration factors such as (determined by h) and fluctuations in the power supply voltage. If this is assumed to be 1V, the resistance R of the power supply line that satisfies this condition is expressed by the following equation, ignoring the margin. R≦1/8・I≒2000 [Ω] That is, the resistance R of the power supply line must be 2KΩ or less. However, taking into consideration the fact that a margin must be ensured, it is actually necessary to reduce the resistance to 1KΩ or less.

Therefore, in a full CMOS type SRAM, as shown in FIG. 3, the power line b that directly supplies power to the cells a, a, . . . is also made of aluminum (1Al) like the power line c. Ta.

[0008]

[Problem to be Solved by the Invention] However, as mentioned above, the power supply line b that directly supplies power to cells a, a,...
However, if it is made of aluminum (1Al) like the power supply line c, the area occupied by the cells and cell arrays becomes large, making it difficult to achieve high integration of the RAM. This is because there are other parts of the RAM that must be made of 1Al. That is, the bit line is normally formed of 2Al (second layer aluminum film), but the ground line and main word line must be formed of 1Al, and in addition to these, the If even the power supply line b is made of 1Al, high integration of the RAM will be hindered due to the 1Al.

Regarding the point that the main word line is made of 1A, the word line is normally made of polycrystalline silicon, but in the divided word line type SRAM, the main word line is made of 1A.
The section word line is formed from polycrystalline silicon. Regardless of whether it is 1M or 4M, SRAM uses a divided word line method. As described above, as long as the power supply line that supplies the power supply voltage directly to each memory cell is made of 1Al, it has been difficult to achieve higher integration.

The present invention was made to solve these problems, and it is an object of the present invention to make it possible to obtain wiring with low resistance even when it is formed of a material with high sheet resistance.

[0011]

[Means for Solving the Problems] The semiconductor device of the present invention is characterized in that a conductive layer formed over the entire surface is used as wiring.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be explained in detail below according to the illustrated embodiments. 1A to 1C are for explaining one embodiment in which the present invention is applied to an SOI type full CMOSSRAM, in which (A) is a circuit diagram of a memory cell, and (B) is a main part. The sectional view shown in FIG. 12C is a plan view. In the drawing, Qp and Qp are p-channel load MOS
Transistor, Qn, Qn is n-channel drive MOS
The transistors Qw and Qw are n-channel switching MOS transistors, and these MOS transistors are formed in the SOI layer.

1 is an SOI substrate made of silicon Si, 2
3 is an insulating layer, and 3 is a wiring layer made of polycrystalline silicon, which serves as a power supply wiring for supplying a power supply current received from an aluminum power supply line (7) to be described later to each memory cell. That is, it plays a role corresponding to the power supply line b in the conventional example shown in FIG. The wiring layer 3 made of polycrystalline silicon is formed so as to cover the entire surface, at least in the area where the memory cell array is formed. First, it is possible to reduce the resistance R of the power supply line.

4 is a wiring layer 3 made of the above-mentioned polycrystalline silicon.
An insulating film that serves as a base for the SOI layer formed above, 5 is an SO
Each MOS transistor is formed in the SOI layer 5 in the I layer. 5a is the source of a p-channel MOS transistor of one memory cell formed in the SOI layer 5, and 5b is the source of an n-channel MOS transistor. 6 is a contact hole formed in the insulating film 4;
The source 5a of the p-channel MOS transistor is connected to the wiring layer 3 through the contact hole 6. Reference numeral 7 denotes a power supply line made of 2Al (not shown in FIG. 1B), which is connected to the wiring layer 3 through contact holes 8, 8, . . . formed in the insulating film 4, etc. i, i, . . . are currents flowing through each part toward the source of one load MOS transistor Qp, and the sum of these is the write current I.

[0015] In this way, in this SRAM, the SO
Since the wiring layer 3 is completely spread below the insulating film 4 which is the base of the I layer 5, at least under the memory cell array, the width of the wiring layer 3 is extremely wide. Therefore, even if the wiring layer 3 is formed of a conductive material with relatively high sheet resistance, such as polycrystalline silicon, the resistance of the power supply line can be made sufficiently small. Therefore, there is no need to worry about the width of the power supply line being restricted by the ground line or section word line as in the past, and it becomes possible to have a configuration in which the power supply line is completely laid out, which in turn allows the width of the power supply line to be made extremely wide. .

Incidentally, the power line resistance R in this embodiment is expressed by the following formula. R≒(ρs/2π)・1n(L-r)/rwhere, ρ
s is the sheet resistance of the polycrystalline silicon layer 3, L is the distance between the aluminum power supply lines 8 and 8, and r is the contact hole connecting between the source 5a of the p-channel MOS transistor Qp, which is a load MOS transistor, and the wiring layer 3. The radius is 6. And L=460.8 μm (128
Assuming that r=0.3 μm and ρs=300Ω/port, the resistance R of the power supply line can be set to a considerably low value of about 350Ω. That is, the above-mentioned condition of R≦1KΩ is fully satisfied.

Therefore, according to the present SRAM, there is no need to form a power supply line with 1Al, and in the memory array area, only the backing word line and ground line need to be formed with 1Al, so higher integration is possible than in the past. can be achieved.

FIG. 2 is a plan view showing the main part of the layout of an SOISRAM which is a specific example of the semiconductor device of the present invention. In the drawing, the two-dot chain line is an island made of an SOI layer, the one-dot chain line is an island made of polycrystalline silicon, and the drive M
OS transistor Qn and load MOS transistor Qp
and a section word line that forms the gate of the switching MOS transistor Qw. The broken line indicates 1Al, and the solid line indicates 2Al forming the bit line. Note that the wiring layer in contact with the source of the load MOS transistor Qp is formed of a polycrystalline silicon layer below the SOI layer that is completely spread under the memory cell array, and does not appear in FIG. Further, n-type impurities are diffused into the sources and drains of the drive MOS transistor Qn and the switching MOS transistor Qw using the gates as masks, but the impurity diffusion regions are not shown because the drawing is too crowded.

[0019]

Effects of the Invention In the semiconductor device of the present invention, a conductive layer is formed almost entirely on one surface of a semiconductor layer on which a semiconductor element is formed, with an insulating film interposed therebetween, and the conductive layer connects a contact hole in the insulating film. The device is characterized in that it is connected to the semiconductor element via a wire to form a wiring. Therefore, according to the semiconductor device of the present invention, wiring with low resistance can be obtained even if the conductive layer is formed of a material with high sheet resistance.

[Brief explanation of drawings]

1 (A) to (C) are for explaining one embodiment in which the semiconductor device of the present invention is applied to a full CMOS type SRAM, (A) is a circuit diagram of a memory cell, (B) (C) is a sectional view of a main part, and (C) is a plan view.

[Figure 2] Full CMOS type S implementing the semiconductor device of the present invention
FIG. 2 is a plan view showing a main part of a specific layout example of a RAM.

FIG. 3 is a plan view showing main parts of a conventional example.

[Explanation of symbols]

3 Conductive layer 4 forming wiring formed on almost the entire surface Insulating film 5 Semiconductor layer 6 Contact hole

Claims (1)

[Claims] 1. A conductive layer is formed substantially entirely on one surface of a semiconductor layer on which a semiconductor element is formed, with an insulating film interposed therebetween,
A semiconductor device characterized in that the conductive layer is connected to the semiconductor element through a contact hole in the insulating film to form a wiring.