JPH04294581A - Manufacture of full cmos sram - Google Patents

Abstract

PURPOSE:To reduce the size of a memory cell by deciding the width of an island semiconductor layer on which driver and load MOS transistors are formed by one step of lithography and the width of a separating area between both transistors by another step of lithography. CONSTITUTION:The first mask layer 3 is formed to such a pattern that semiconductor island layers 1a and 1b can be obtained from the pattern by etching by using a resist film 4 as a mask. Then the second mask layer 5 is formed to such a pattern that covers an area which becomes the layer 1 but does not cover another area which becomes a separating area 8 by etching by using a resist film 6 as a mask. After the layer 5 is formed, the layer 6 is formed to such a pattern that covers an area which becomes the layer 1b but does not cover the area which becomes the area 8. Thereafter, the island layers 1a and 1b are formed by etching the mask layer 3 by using a resist film 7 and mask layer 5 as masks and a semiconductor layer 1 by using the mask layer 3 as a mask.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is a full CMOS type SRA.
The present invention relates to a method of manufacturing M, particularly a method of manufacturing a novel full CMOS type SRAM that can reduce the memory cell size.

0002

[Prior Art] There are high resistance load type, TFT load type, and full CMOS type as SRAM.The high resistance load type and TFT type can reduce the memory cell size.
M, 16M is the mainstream SRAM. On the other hand, full CMOS type SRAM has 6 MOS per cell.
Since a transistor is required, the cell size tends to increase.

0003

However, it is difficult to improve the stability of cell operation and soft error resistance in high resistance load type and TFT load type SRAMs. On the other hand, a full CMOS type SRAM has the advantage of increasing the stability of cell operation and high soft error resistance. Therefore, there is a strong need to increase the integration density of full CMOS type SRAMs as much as possible. In order to meet this need, it has become clear that it is preferable to configure the SRAM with an SOI type semiconductor device. This is because the SOI layer allows p-channel MOS transistors and n-channel MOS transistors to be formed relatively close to each other. However, depending on the photolithography resolution, the width of the MOS transistor and the MOS
Since there is a restriction on narrowing the spacing between transistors, it has been impossible to achieve a high degree of integration comparable to that of high resistance load type or TFT load type SRAMs.

Therefore, the present invention aims to miniaturize the width of the driver MOS transistor and the load MOS transistor and the spacing between both MOS transistors beyond the limits imposed by the resolution of photolithography, thereby converting the full CMOS type SRAM into a high resistance load type and a TFT load type. The purpose is to enable high integration comparable to SRAM.

[0005]

[Means for solving the problems] The present invention full CMOS type S
In the RAM manufacturing method, the width of the island semiconductor layer in which the driver MOS transistor and load MOS transistor are formed is determined in the first regraphy,
The width of the isolation region between the S transistor and the load MOS transistor is determined by separate lithography.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a full CMOS type SRAM according to the present invention will be explained in detail below according to the illustrated embodiments. Figure 1(A)
2(A) to 2(D) are cross-sectional views showing one embodiment of the method for manufacturing a full CMOS type SRAM of the present invention in the order of steps;
B) shows one application example of the present invention, (A) is a plan view showing the main part of the layout, and (B) is a circuit diagram of a memory cell. Note that FIGS. 1(A) to (D) are 1-1 in FIG. 2(A).
This is a cross-sectional view of the area corresponding to the line. (A) A first mask layer 3 made of SiO2 is formed entirely on the SOI layer 1, and the first mask layer 3 is patterned by etching using the resist film 4 as a mask. The first mask layer 3 is a driver MOS transistor (width B
), the pattern and size are such that a semiconductor island layer in which a load MOS transistor (width A) is formed can be obtained. Note that 2 is an insulating film that is the base of the SOI layer 1. FIG. 1A shows the state after the first mask layer 3 is patterned.

(B) Next, the resist film 4 is removed,
A second mask layer 5 made of Si3 N4 is formed, and then the second mask layer 5 is etched using the resist film 6 as a mask. In this case, the second mask layer 5 covers the region where either the driver MOS transistor or the load MOS transistor, for example, the load MOS transistor, is to be formed, but does not cover the part that will become the isolation region between the driver MOS transistor and the load MOS transistor. Form into a pattern. Therefore, the overlapping portion of the semiconductor island layer 3 and the second mask layer 5 becomes a region where one of the driver MOS transistor and the load MOS transistor, in this example, the load MOS transistor is formed. FIG. 1B shows the state after the second mask layer 5 is etched.

(C) Next, the resist film 6 is removed,
A resist film 7 is selectively formed again. The resist film 7 completely covers the region where the other of the driver MOS transistor and the load MOS transistor, in this example the driver MOS transistor, is to be formed, and the portion (8) which becomes the separation region between the driver MOS transistor and the load MOS transistor is Form into an uncovered pattern. after that,
The first mask layer 3 is etched using the resist film 7 and the second mask layer 5 as masks. Then, the driver MOS transistor load MOS of the first mask layer 3
A portion that will become an inter-transistor isolation region will be removed. Note that 3a is a driver MOS of the first mask layer 3.
A portion 3b that masks a region of one of the transistor and the load MOS transistor, which becomes the load MOS transistor in this example, is the driver MO of the first mask layer 3.
This is a portion that masks the other of the S transistor and the load MOS transistor, which in this example becomes the driver MOS transistor. FIG. 1(C) shows the first mask layer 3
The state after forming the first mask layers 3a and 3b by selective etching is shown.

(D) After that, the resist film 7 is removed, the second mask layer 5 is removed, and the semiconductor layer 1 is etched using the first mask layer 3 as a mask, thereby forming the load MOS transistor. A semiconductor island layer 1a to be formed and a semiconductor island layer 1b in which a driver MOS transistor is to be formed are formed. 8 is a separation region between the semiconductor island layers 1a and 1b. (D
) shows the state of the semiconductor layer 1 after etching. In this specification, the semiconductor island layer refers to a layer in which a semiconductor exists independently from other semiconductors in the form of an island.
It does not matter whether it is an OI layer or a polycrystalline silicon layer.

FIG. 2A is a plan view showing the main part of the layout of an SOISRAM which is a specific example of the semiconductor device of the present invention. In the drawing, the two-dot chain line represents an island made of an SOI layer, and the one-dot chain line represents an island made of polycrystalline silicon.
What constitutes the gates of the driver MOS transistor Qn and the load MOS transistor Qp, and the switching MO
There is a section word line forming the gate of the S transistor Qw. The broken line indicates 1Al, and the solid line indicates 2Al forming the bit line. Note that the wiring layer that the source of the load MOS transistor Qp contacts is the SO layer that is completely covered under the memory cell array.
It is composed of a polycrystalline silicon layer below the I layer and does not appear in FIG. In addition, a driver MOS transistor Qn and a switching (word) MOS transistor Q
N-type impurities are diffused into the source and drain of W using the gate as a mask, but the impurity diffusion regions are not shown because the drawing is too crowded.

According to the present full CMOS type SRAM manufacturing method, the width C of the semiconductor island layer in which the driver MOS transistor and the load MOS transistor are formed is determined by one photolithography process shown in FIG. 1A. Ru. Note that the width C is the width A of the semiconductor island layer 1a where the load MOS transistor is formed and the driver M.
Semiconductor island layer 1b where OS transistors are formed
width B of the load MOS transistor/driver MOS
This is the sum of the width D of the isolation region 8 between transistors. On the other hand, the width A of the semiconductor island layer 1a in which the load MOS transistor is formed is the width A of the resist film 4 in step (A).
It is determined by the positional relationship between the resist film 6 in step (B) and can be narrowed beyond the limit due to the resolution of photolithography.

Furthermore, the width D of the isolation region 8 between the load MOS transistor and the driver MOS transistor is determined by the process (B
) is determined by the positional relationship between the resist film 6 in step (C) and the resist film 7 in step (C), and can be narrowed beyond the limit due to the resolution of photolithography. Furthermore, the width B of the semiconductor island layer 1b in which the driver MOS transistor is formed is determined by the positional relationship between the resist film 4 in step (A) and the resist film 7 in step (C), and is limited by the resolution of photolithography. can be narrowed beyond that.

As described above, the width A of the semiconductor island layer 1a, the width D of the isolation region 8 between the load MOS transistor and the driver MOS transistor, and the width B of the semiconductor island layer 1b in which the driver MOS transistor is formed are as follows.
Each is determined not by a single lithography process, but by the positional relationship of the resist films 4, 6, and 7 formed by mutually different lithography processes,
It can be narrowed beyond the resolution limits of photolithography. Therefore, the area occupied by the memory cell can be reduced, and the degree of integration of the SRAM can be increased.

It is inevitable that the widths A and B of the semiconductor island layer 1a in which the driver MOS transistor is formed and the semiconductor island layer 1b in which the load MOS transistor is formed vary somewhat due to mask alignment errors. However, it may not adversely affect the operation of the memory cell. This point will be explained in detail. To explain the problem of memory cell operation using an example of reading a "0" level signal from node 1 in FIG. Current flows into node 1 from bit line B, and the potential of node 1 increases. If that potential exceeds the threshold voltage of the inverter, the drive M of the inverter on the opposite side of the inverter having node 1
The OS transistor turns on, resulting in the data in the memory cell being inverted. Therefore, it is necessary to prevent the rising potential from exceeding the threshold voltage.

By the way, the rising potential of the node 1 is determined by the ratio of the driving capabilities of the driver MOS transistor Qn1 and the load MOS transistor Qp1, and the threshold voltage of the inverter is determined by the ratio of the driving capabilities of the driver MOS transistor Qn1 and the load MOS transistor Qp1.
is determined by the threshold voltage of load MOS transistor Qp1. Here, the driver MOS transistor (n
It is assumed that the finished size W (width)/L (length) [unit: μm] of the load MOS transistor (pMOS) is as follows. Note that the numbers in parentheses are variations due to mask misalignment. Driver MOS transistor (nMOS) 0.44
(±0.21)/0.6 load MOS transistor (p
MOS) 0.24 (±0.15)/0.6 word MOS transistor (nMOS) 0.39
/0.6

Then, the above-mentioned rising potential of the above-mentioned node and the threshold voltage of the inverter are determined by the width (Wd) of the driver MOS transistor.
It has a dependence as shown in FIG. Specifically, as the width (Wd) of the driver MOS transistor increases, the node potential decreases, but the threshold voltage also decreases. That is, the node potential and the threshold voltage have similar dependence on the width (Wd) of the driver MOS transistor. Therefore, even if the width Wd of the driver MOS transistor becomes narrower and the node potential at the time of reading becomes higher, the threshold voltage of the inverter also becomes higher in this case, so the difference between the node potential and the threshold voltage becomes higher. A margin can be secured in between, and the problem of data being inverted upon reading can be avoided. Therefore, even if there is variation in the width of the driver MOS transistor due to mask misalignment, it does not adversely affect the operation of the memory cell.

[0017]

Effects of the Invention In the method for manufacturing a full CMOS type SRAM of the present invention, a first mask layer is formed on a semiconductor layer, and a driver MOS transistor and a load MOS transistor are separated from each other by photolithography on the semiconductor layer. patterning into a pattern capable of forming parallel semiconductor island layers, and forming a second mask layer on the semiconductor layer including on the first mask layer,
The driver MOS transistor and load M of the first mask layer are formed by photolithography on the second mask layer.
A process of patterning into a pattern that overlaps the area that will become one of the OS transistors but does not overlap the area that will become the isolation region between the driver MOS transistor and the load MOS transistor, and a process of patterning the driver MOS transistor and load of the first mask layer with a resist film. A step of etching the first mask layer using a mask over the other region of the MOS transistor and using the resist film and the second mask layer as a mask, and etching the semiconductor layer using the first mask layer as a mask. The method is characterized by comprising a step of forming semiconductor island layers separated from each other in which a driver MOS transistor and a load MOS transistor are formed. Therefore, according to the method of manufacturing a full CMOS type SRAM of the present invention, the driver M
The width of each semiconductor island layer in which an OS transistor and a load MOS transistor are formed can be determined by the positional relationship of resist masks formed by different lithography processes, and the width of each semiconductor island layer can be determined by exceeding the resolution limit of photolithography. The width and separation region spacing can be reduced.

[Brief explanation of drawings]

[Fig. 1] (A) to (D) are full CMOS type SRs of the present invention.
FIG. 3 is a cross-sectional view showing one example of a method for manufacturing AM in the order of steps.

[Fig. 2] (A) and (B) show one example of application of the present invention, in which (A) is a plan view showing the main part of the layout, and (B)
) is a memory cell circuit.

FIG. 3 is a diagram showing the relationship between the width (Wd) of the driver MOS transistor, the node potential, and the threshold voltage of the inverter.

[Explanation of symbols]

1 Semiconductor layer 1a, 1b Semiconductor island layer 3 First mask layer 5 Second mask layer 6, 7 Resist film 8 Separation area

Claims (1)

[Claims] 1. A first mask layer is formed on a semiconductor layer, and a driver MOS transistor and a load MO are formed on the first mask layer at a slight distance from each other by photolithography.
patterning into a pattern capable of forming a semiconductor island layer in which S transistors are arranged in parallel;
A second mask layer is formed on the semiconductor layer including the first mask layer, and the second mask layer is applied to each of the driver MOS transistor and load MOS transistor of the first mask layer by photolithography. A process of patterning the driver MOS transistor and the load MOS transistor of the first mask layer with a resist film to form a pattern that overlaps the area that will become one of the driver MOS transistors and does not overlap the area that will become the isolation region between the driver MOS transistor and the load MOS transistor.
A step of etching the first mask layer by masking the region that will become the other of the OS transistors and using the resist film and the second mask layer as a mask, and etching the semiconductor layer using the first mask layer as a mask. By doing so,
a step of forming semiconductor island layers separated from each other in which a driver MOS transistor and a load MOS transistor are formed.
Manufacturing method of S-type SRAM.