GB2060250A

GB2060250A - Controllable Semiconductor Capacitors

Info

Publication number: GB2060250A
Application number: GB8006508A
Authority: GB
Original assignee: Clarion Co Ltd
Current assignee: Faurecia Clarion Electronics Co Ltd
Priority date: 1979-03-12
Filing date: 1980-02-26
Publication date: 1981-04-29
Also published as: SE8001862L; NL8001451A; NL186283B; AU5590080A; GB2060250B; AU535235B2; DE3009499A1; NL186283C

Abstract

A controllable semiconductor capacitor comprises at least one control portion 13, 14 which modulates a depletion layer 16 to vary the capacitance of a capacitor portion 12. The capacitor portion may comprise an MS, Schottky or PN junction capacitor and the control portions may comprise reverse biased PN junctions. The device may be used in tuned circuits or parametric applications. <IMAGE>

Description

SPECIFICATION Semiconductor Device with Multi-electrode Construction Equivalent to Variable Capacitance Diode This invention relates to a semiconductor device, and more particularly to a semiconductor device with a multi-electrode construction equivalent to a variable capacitance diode and to a parametric mixer using such semiconductor device.

In general, a p-n junction diode is used as a variable capacitance diode because, when a reverse bias is applied to the p-n junction, the carriers in the vicinity of the junction are moved to induce a depletion layer and the width of the resulting depletion layer is characteristic of depending upon the reverse-bias voltage.

The conventional variable capacitance diode has an essential construction such that an electrode applied with a bias voltage thereto functions as an electrode for reading out a change in capacitance therefrom in itself. Consequently, if a bulk having a uniformly distributed carrier concentration is provided, a C-V characteristic of the diode will represent a relatively gentle change in capacitance under a high reverse-bias condition and, therefore, it may be necessary to control a diffusion profile, for example by ion-implanation.

This means that the production of devices may encounter a difficulty and, if possible, the control thereof may be limited within a narrow range.

Also, for the sake of the construction as described above, it is a disadvantage that the degree of freedom is relatively small in a circuit design.

Further, since the conventional variable capacitance diode is such that the depletion layer induced by the movement of carriers is limited in its width, a ratio of a maximum capacitance Cmax to a minimum capacitance Cmin is nothing more than a relatively small value of about 20.

Additionally, as described above, the conventional variable capacitance diode has a single electrode construction such that an electrode applied with a bias voltage thereto functions as an electrode for reading out a change in capacitance therefrom in itself and has a disadvantage such that the change in capacitance may be within a relatively small range. Therefore, when the conventional variable capacitance diode was used as a parametric mixer, there was a problem as caused by the range of the change in capacitance and the single electrode construction in, for example, the degree of freedom in a circuit design, because of applying both a pump voltage and an input signal voltage to the single electrode.

Accordingly, an object of the present invention is to overcome the above described disadvantages of the prior art and to provide a novel semiconductor device with a multielectrode construction equivalent to a conventional variable capacitance diode, wherein an electrode applied with a reverse-bias thereto, that is, a control electrode for controlling the width of a depletion layer and a read-out electrode for bringing out a change in capacitance are constructed separately and independently.

Another object of the present invention is to provide a novel MIS type semiconductor device with a multi-electrode construction equivalent to the variable capacitance diode.

A further object of the present invention is to provide a novel Schottky type semiconductor device with a multi-electrode construction equivalent to the variable capacitance diode.

A further object of the present invention is to provide a novel p-n junction type semiconductor device with a multi-electrode construction equivalent to the variable capacitance diode.

A further object of the present invention is to provide a novel semiconductor device wherein an electrode applied with a reverse-bias thereto, that is, a control electrode for controlling the width of a depletion layer and a read-out electrode for reading out a change in capacitance are constructed separately and independently and a plurality of control electrodes are provided, thereby being capable of extending extremely the change in capacitance.

A still further object of the present invention is to provide a parametric mixer using the novel semiconductor device with a multi-electrode construction.

These and other objects and features of the present invention will be better understood from the following description taken in connection with the accompanying drawings.

Fig. 1 shows a concrete construction of a semiconductor device with a multi-electrode construction of the present invention; Fig. 2 shows an equivalent circuit of the semiconductor device as shown in Fig. 1; Fig. 3 shows a concrete construction of a MIS type semiconductor device with a multielectrode construction of the present invention; Fig: 4 shows a concrete construction of a Schottkytype semiconductor device with a multielectrode construction of the present invention; Fig. 5 shows a concrete construction of a p-n junction type semiconductor device with a multielectrode construction of the present invention; Fig. 6 shows a concrete construction of a vertical type semiconductor device with a multielectrode construction of the present invention; Fig. 7 shows a concrete construction of a horizontal type semiconductor device with a multi-electrode construction of the present invention; Fig. 8 shows an equivalent circuit each of the semiconductor devices as shown in Figs. 3 to 7; Fig. 9 shows a tuning circuit of a conventional RF amplifier, wherein a conventional variable capacitance diode with a single electrode construction is used;; Fig. 10 shows a tuning circuit of an RF amplifier, wherein the semiconductor device of the present invention is used; Fig. 11 shows a C-V characteristic curve in relation to the semiconductor device as shown in Fig. 1; Figs. 12 through 15 show parametric mixer circuits using the semiconductor device as shown in Fig. 1; Fig. 16 shows a block diagram of a usual FM front end model, wherein the parametric mixer circuits as shown in Figs. 12 to 15 are used; Figs. 17 through 20 show parametridmixer circuits using the MIS type semiconductor device as shown in Fig. 3; Figs. 21 through 24 show parametric mixer circuits using the Schottky type semiconductor device as shown in Fig. 4; Figs. 25 through 28 show parametric mixer circuits using the p-n junction type semiconductor device as shown in Fig. 5; and Figs. 29 through 32 show parametric mixer circuits using the vertical type semiconductor device as shown in Fig. 6.

Fig. 1 shows a concrete construction of a semiconductor device 10 of the present invention.

A capacitance read-out portion 12 with a capacitance read-out electrode (not shown) of metal materials is formed on the center of the upper surface of a bulk 1 1 which is of a semiconductor single crystal of, for example, ntype materials, and a first and second depletion layer control portions 13 and 14 which have control electrodes or bias electrodes (not shown), respectively, are formed on the both sides of the capacitance read-out portion 12. On the lower surface of the bulk 11, an ohmic electrode (opposite electrode) 15 is formed.In the concrete, the capacitance read-out portion 12 comprises any one of, for example, a MOS construction, a MIS construction, a Schottky barrier and a p-n type region for providing a p-n junction which are formed on the bulk 11 of the semiconductor single crystal, and also the first and second depletion layer control portions 13 and 14 comprises any one of, for example, the MOS construction, the MIS construction, the Schottky barrier, the p-type region for providng the p-n junction.

In the above constructions, when the first and second depletion layer control portions 13 and 14 are reverse-biassed through the respective control electrodes, a depletion layer 16 generated below the capacitance read-out portion 12 is changed in width, whereby the change can be read out through the capacitance read-out electrode.

Accordingly, the construction as shown in Fig. 1 acts as a device equivalent to a variable capacitance diode. In the case where the n-type and p-type regions in the above explanation are reversed in arrangement, it will be apparent that the device operates in the same manner. Further, in addition to providing the p-n junction by means of forming the p-type or n-type region on the upper surface of the bulk 1 1 as described above, it may be possible to provide the p-n junction by forming the p-type or n-type region within the bulk 1 1 and thereby to change the width of the depletion layer by reverse-biassing the p-n junction through an external control electrode.

Fig. 2 shows an equivalent circuit of the semiconductor device 10 of the present invention shown in Fig. 1. Terminals a and b are bias terminals, respectively for applying a reverse-bias signal to each of the first and second depletion layer control portions 13 and 14, and terminals c and dare capacitance read-out terminals, respectively, for bringing out a change in onn; tances Assuming that a differential capacitance of a depletion layer control portion at a zero-bias is C and a differential capacitance at the growth of a depletion layer is CD, a differential capacitance C read out through the capacitance read-out portion is equivalently as follows: 1 1 1 - + (1) C CO CD Also, assuming that the width of a depletion layer is d, the area of an electrode is S and the dielectric constant of a semiconductor single crystal is E., a differential capacitance of depletion layer CD is as follows:: E.S CD (2) d In order to enlarge the ratio of change in capacitance, as understood by the formula (1), it is necessary to reduce sufficiently the capacitance CD against CO, that is, as represented in the formula (2), to increase the width of depletion layer d.

Fig. 3 shows a concrete construction of a MIS type semiconductor device 1 OA of the present invention. P-type regions 1 2A and 1 3A are provided on the upper surface of a bulk 1 A of a semiconductor single crystal of n-type materials to form a first and second p-n junctions, respectively, and control electrodes (bias electrodes) 1 4A and 1 5A of metal materials are provided in contact with the p-type regions 1 2A and 1 3A, respectively. Also, an insulator 1 6A is provided on the upper surface of the bulk 1 A and, further, a capacitance read-out electrode 1 7A is provided on the upper surface of the insulator. That is, a MIS construction is formed in the center of the upper surface of the bulk 1 1 A.

On the other hand, on the lower surface of the bulk 1 1A, an ohmic electrode (opposite electrode) 1 8A is provided. In such construction, when the first and second p-n junctions are reverse-biassed, a depletion layer 1 9A generated below the MIS construction is changed in width, whereby the change can be read out from the capacitance read-out electrode 1 7A. Therefore, the construction shown in Fig. 3 acts as a device equivalent to a variable capacitance diode. In the case where the p-type and n-type regions in Fig. 3 are reversed in arrangement, the device operates obviously in the same manner.

Fig. 4 shows a concrete construction of a Schottky type semiconductor device 1 OB of the present invention. The Schottky barrier is formed on an interface between the center of the upper surface of a bulk 11 B which is of a semiconductor single crystal as n-type materials and a capacitance read-out electrode 1 2B of metal materials. P-type regions 13B and 14B are provided on the both sides of the Schottky barrier to form a first and second p-n junctions, respectively, and control electrodes (bias electrodes) 1 SB and 1 6B are provided in contact with the p-type regions 1 3B and 14B, respectively. On the lower surface of the bulk 1 1 B, an ohmic electrode (opposite electrode) 1 78 is provided.In such construction, if the first and second p-n junctions are reverse-biassed, a depletion layer 1 8B generated below the Schottky barrier is changed in width, whereby the change in capacitance can be read out through a capacitance readout electrode 128. Thus, the construction shown in Fig. 4 acts as a device equivalent to a variable capacitance diode.

Relating to Fig. 4, in the case where the p-type and n-type regions are reversed in arrangement, the device operates obviously in the same manner.

Fig. 5 shows a concrete construction of a p-n junction type semiconductor device 1 OC of the present invention. A p-type region 1 2C is provided in the center of the upper surface of a bulk 11 C of a semiconductor single crystal as ntype materials to form a first p-n junction portion, and a capacitance read-out electrode 1 3C of metal materials is provided in contact with the ptype region 1 2C. Provided on the both sides of the p-type region are different p-type regions 1 4C and 1 5C to form a second and third p-n junction portions, respectively, and control electrodes (bias electrodes) 1 6C and 1 7C are provided in contact with the p-type regions 1 4C and 1 so, respectively. On the lower surface of the bulk 1 1 C, an ohmic electrode (opposite electrode) 1 8C is provided.In the construction above, if the second and third p-n junction portions are reverse-biassed, a depletion layer 1 9C generated below the first p-n junction portion is changed in width, whereby the change in capacitance can be read out through the capacitance read-out electrode 1 3C. This means that the construction as shown in Fig. 5 acts as a device equivalent to a variable capacitance diode. In the case where the p-type and n-type regions in Fig. 5 are reversed in arrangement, the device operates obviously in the same manner.

Fig. 6 shows a concrete construction of a vertical type semiconductor device 1 OD of the present invention, which is capable of extending a change in capacitance. A capacitance read-out portion 1 2D with a capacitance read-out electrode (not shown) of metal materials is formed on the upper surface of a semiconductor single crystal bulk 11 D of, for example, n-type materials, and a plurality of p-type regions having control electrodes, respectively, of metal materials are formed apart from the capacitance read-out portion 1 2D.In the illustrated embodiment, a first to fourth p-type regions 1 3D, 1 4D, 1 5D and 1 6D are provided, only the control electrodes 1 7D and 1 8D associated with the first and second p-type regions, respectively, are shown in Fig. 6, but the control electrodes associated with the third and fourth p-type regions are not shown therein.The above construction such that the p-type regions exist in both the upper and inner portions of the bulk may be produced by the steps of diffusing a p-type impurity into a semiconductor single crystal of ntype materials to form the third and fourth p-type regions 1 5D and 1 6D, precipitation-growing the semiconductor single crystal by epitaxial growth, diffusing a p-type impurity into the semiconductor single crystal to form the first and second p-type regions 1 3D and 1 4D, forcing p-type regions to reach the third and fourth p-type regions 1 5D and 1 6D by doping, and forming control electrodes associated with the p-type regions, respectively.

The capacitance read-out portion 1 2D is formed of any one of, for example, a MOS construction, a MIS construction, a Schottky barrier and a p-type region for providing a p-n junction, which are formed on the bulk 1 D of a semiconductor single crystal. An ohmic electrode (opposite electrode) 1 9D is formed on the lower surface of the bulk 1 1 D.

When the first to fourth p-n junction portions comprising the first to fourth p-type regions 1 3D, 1 4D, 1 5D and 1 6D and the semiconductor single crystal of n-type materials are reverse-biassed in turn through the control electrodes associated therewith, a depletion layer DL generated below the capacitance read-out portion 1 2D is changed in width in the vertical direction (arrowheaded direction), whereby the extended change in capacitance can be read out through the capacitance read-out electrode. The construction shown in Fig. 6, therefore, acts as a device equivalent to a variable capacitance diode.

Fig. 7 shows a concrete construction of a horizontal type semiconductor device 1 OE of the present invention, which is capable of extending a change in capacitance. For example, an n-type impurity is diffused into the upper portion of a bulk 1 E of a semiconductor single crystal such as p-type materials to provide an n-type region 1 2E, and a p-type impurity is diffused into the n-type region 1 2E to provide a plurality of p-type regions.

Control electrodes of metal materials are formed on a plurality of the p-type regions, respectively.

Also, provided on the n-type region 1 2E are a capacitance read-out portion 1 3E with a capacitance read-out electrode (not shown) of metal materials and an ohmic electrode 14E which functions as an opposite electrode. The illustrated embodiment is shown such that a first to fourth p-type regions 1 so, 1 6E, 1 7E and 18E are formed as a plurality of the p-type regions and four control electrodes 1 9E, 20E, 21 E and 22E are formed to be associated therewith. In the concrete, the capacitance read-out portion 1 3E is formed of any one of, for example, a MOS construction, a MIS construction, a Schottky barrier and a p-type region for providing a p-n junction, which are formed on the bulk 1 E of the semiconductor single crystal.Alternatively, instead of a plurality of the p-type regions, any one of the MOS construction, the MIS construction and the Schottky barrier may be selectively formed on the bulk 11 E of the semiconductor single crystal, as a depletion layer control portion.

When the first to fourth p-n junction portions comprising the first to fourth p-type regions 1 so, 1 6E, 1 7E and 1 8E and the n-type region 1 2E, as shown in Fig. 7, are reverse-biassed in turn through the control electrodes associated therewith, a depletion layer DL generated below the capacitance read-out portion 1 3E is changed in width in the horizontal direction (arrowheaded direction), whereby the extended change in capacitance can be read out through the capacitance read-out electrode. Therefore, the construction shown in Fig. 7 acts as a device equivalent to a variable capacitance diode.

In the case where the n-type and p-type regions in the explanation in relation to Figs. 6 and 7 are reversed in arrangement, the same operation can be obviously accomplished.

Fig. 8 shows an equivalent circuit of the MIS type semiconductor device shown in Fig. 3.

Terminals a and b are bias terminals, respectively, for applying a reverse-bias signal to each of the first and second p-n junction portions, and terminals c and dare capacitance read-out terminals, respectively, for reading out a change in capacitance.

Assuming that a differential capacitance at a zero-bias disregarding a plat band shift of the MIS construction is CO and a differential capacitance at the growth of a depletion layer 1 9A is CD, a differential capacitance C read out through the capacitance read-out electrode 1 7A is equivalently as follows: 1 1 1 - =----+ = + (3) C CO CD Further, assuming that the width of a depletion layer is d, the area of an electrode is S and the dielectric constant of a semiconductor single crystal is E5, a differential capacitance of a depletion layer CD is as follows:: E9S CD= (4) d Thus, in order to enlarge the ratio of change in capacitance of the device, as shown by the formula (3), it is necessary to reduce sufficiently the capacitance CD against CO, that is, as shown by the formula (4), to increase the width of depletion layer d.

In the embodiment shown in Fig. 3, the ratio of change in capacitance, Cmax/Cmin, is given as follows: Cmax d Eo Eo do =~.~(~.~+ 1 ) (5) Cmin do E5 E, d where do represents the width of the insulator 1 6A and Eo the dielectric constant of the insulator 1 6A. Assuming that, in the concrete, d=1 Oiu and do=500A, the ratio of change in capacitance can be obtained by the order of about 70 which is an extremely large value in comparison with that of prior art as described above.

Fig. 8 also shows an equivalent circuit of the Schottky type semiconductor device as shown in Fig. 4, provided that CD represents a differential capacitance at the zero-bias of a Schottky barrier.

Fig. 8 also shows an equivalent circuit of the p-n junction type semiconductor device shown in Fig. 5, provided that terminals a and b are bias terminals, respectively, for applying a reverse-bias signal to the second and third p-n junction portions and CO represents a differential capacitance at the zero-bias of a p-n junction portion.

Fig. 8 also shows an equivalent circuit of the semiconductor device which is capable of extending a change in capacitance, shown in Figs.

6 and 7, provided that CO represents a differential capacitance at the zero-bias of a depletion layer control portion with control electrodes.

Consequently, a conventional variable capacitance diode with a single electrode construction, wherein a bias electrode functions as a capacitance read-out electrode in itself, is considerably limited in the width d of a grown depletion layer caused by the construction thereof. However, according to the semiconductor device with a multi-electrode construction of the present invention, the width of depletion layer d can be grown much larger than in the prior art by means of changing merely and adequately the shape of depletion layer control portions or p-n junction portions and, therefore, a change in capacitance, which is read out, can be expected to increase rapidly.

And now, the semiconductor device of the present invention, wherein a bias electrode for controlling the width of a depletion layer is completely separated from a capacitance readout electrode, will present many advantages as described below, if such device is applied to any concrete circuit devices.

Fig. 9 shows a tuning circuit of a conventional RF amplifier, wherein Field Effect Transistor FET is used and conventional two-terminal type variable capacitance diodes VC, and VC2 are used for a stage coupling circuit and a local oscillating circuit, respectively. On the other hand, Fig. 10 shows a tuning circuit of an RF amplifier, wherein the variable capacitance diodes as shown in Fig. 9 are replaced by the semiconductor device VC,' and2,, respectively, of the present invention, each of which has a multi-electrode construction.

As understood by comparing Fig. 9 with Fig.

10, although the circuit as shown in Fig. 9 has a capacitor C2 which functions as a DC voltage blocking capacitor for the variable capacitance diode VC, and a coupling capacitor, and a capacitor C3 which functions as a DC voltage blocking capacitor for the variable capacitance diode VC2, the circuit as shown in Fig. 10 is such that the DC voltage blocking capacitors fall into disuse and the capacitor C2 which functions as a coupling capacitor is merely moved and inserted into the side of a transformer Tr, since the control electrode each of the semiconductor devices VC,' and VC2, is separated from the capacitance readout electrode associated therewith. This difference between Figs. 9 and 10 in circuit construction has an important meaning in the case of integrating circuits.That is, when the variable capacitance diodes were formed within an integrated circuit, the capacitors C2 and C3 had to be provided as external parts because it was difficult to inform these capacitors within the integrated circuit in the prior art, and, therefore, this caused the pins of an integrated circuit element to increase in number. However, according to the present invention, the capacitor has no connection with the integration of the variable capacitance diodes and the capacitor C3 falls into disuse, whereby the pins of the integrated circuit element can be reduced in number. Additionally, in the circuit as shown in Fig.

10, a change in capacitance which may be caused by any voltage of a capacitance read-out electrode for reading out the change in capacitance of the semiconductor device can be minimized. Thus, a high frequency voltage scarcely changes any capacitance value of the semiconductor device, whereby the generation of distortion can be minimized.

Further, according to the semiconductor devices shown in Figs. 6 and 7, it may be possible to assemble a super wide-band electronic tuning circuit in the form of a single device.

Further, according to the semiconductor device of the present invention, when a bias voltage (such as -0.5 V) is suitably applied thereto, the capacitance of the device shows a rapid change, as shown by a C-V characteristic curve of Fig. 1 1, against a voltage applied to the control electrode of a depletion layer control portion.

Figs. 12 through 15 show parametric mixer circuits respectively, each of which uses one or two semiconductor devices with multi-electrode constructions, respectively, of the present invention. In the respective circuit as shown, V5 represents an input signal voltage, Vp represents an exciting (pumping) voltage (local oscillating signal voltage), VO represents an output signal voltage and VB represents a bias voltage.

If any one of the parametric mixer circuits as shown in Figs. 12 to 15 is applied to an FM front end wherein a VHF wave of an FM broadcasting is converted in frequency to 10.7 MHz, the frequency signal is stably amplified, if necessary, and then is detected to obtain an audio signal, assuming that a receiving frequency is f1, a local oscillating frequency is f2 and an intermediate frequency (10.7 MHz) is ~3, a mixing can be accomplished in the relation of f2=f+f3 or f2=f1 -f3, provided that the local oscillating frequency f2 is obtained from the upper side of the receiving frequency f, or is obtained from the lower side thereof.If, in particular, there is a relation, f2=2f1, between the receiving frequency f, and the local oscillating frequency ~2, the parametric mixers shown in Figs. 1 2 to 15 function as parametric amplifiers, respectively.

Fig.16 shows a block diagram of a usual FM front end model which is constructed to compare in performance the parametric mixer of the present invention, as used therein, with the most popular double balance mixer using a conventional Schottky barrier diode. In Fig.16, SG represents a signal generator, MIX represents a mixer, AMP represents an intermediate frequency amplifier (noise factor NF=.2dB, power amplification degree Gyp=30 dB), and a DET represents an FM detector.

In the above case, when the FM front end, as shown in Fig.16, using the double balance mixer was operated, provided that the local oscillating frequency was obtained from the upper side of the receiving frequency, that is, the mixing was accomplished in the relation of f2=f1+f3, and f=120 MHz, f2=130.7 MHz (+23 dBm), f3=1 0.7 MHz and Vin (which is an input of the mixer MIX)=3.2 MV, the value of S/N was 36 dB and the loss of the mixer MIX was 5.5 dB.On the other hand, when the FM front end, as shown in Fig.16, using the parametric mixer of the present invention, as shown in Fig. 12, was operated under the same condition, that is, f,=l 20 MHz, ~2=130.7 MHz (+10 dBm), ~3=10.7 MHz and Vin=3.2 yV, the value of S/N was 36 dB and the loss of the mixer MIX was 8 dB. Accordingly, according to the parametric mixer of the present invention, although the mixer has a relatively large loss, the value of S/N equal to that of the mixer using a conventional Schottky barrier diode can be obtained.

Thus, although the mixer of the present invention has the relatively large loss in comparison with the prior art, it does not cause the value of S/N to reduce. This teaches that the loss in the prior art is caused by any inside resistance and, therefore, is converted to a heat energy, while the loss of the present invention means that the energy of a pumping signal is transferred to an output signal.

As described above, the parametric mixer of the present invention which is capable of obtaining a good performance as well as the double balance mixer using a Schottky barrier diode which may be appreciated as the best device therefor in the present time can be realized by the simple semiconductor device with a multielectrode construction, as described above, which has an extended degree of freedom in a circuit design, and, therefore, it will be possible to facilitate the design and production of, for example, an FM receiver with a high performance and to provide it at a moderate price.

Figs. 17 through 20 show parametric mixer circuits, respectively, each of which uses one or two MIS type semi-conductor devices shown in Fig. 3.

Figs. 21 through 24 show parametric mixer circuits, respectively, each of which uses one or two Schottky type semiconductor devices shown in Fig. 4.

Figs. 25 through 28 show parametric mixer circuits, respectively, each of which uses one or two p-n junction type semiconductor devices shown in Fig. 5.

Figs. 29 through 32 show parametric mixer circuits respectively, each of which uses one or two semiconductor devices shown in Fig. 6, thereby being capable of extending a change in - capacitance.

Claims

1. A semiconductor device with a multi electrode construction equivalent to a variable capacitance diode, characterized in that a capacitance read-out portion with a capacitance read-out electrode and at least one depletion layer control portion with a control electrode are formed on a bulk of a semiconductor single crystal, a depletion layer within said bulk is changed in width when said depletion layer control portion is reverse-biassed through said control electrode, whereby a change in capacitance can be read out through said capacitance read-out electrode.

2. The device as set forth in Claim 1, wherein said capacitance read-out portion is a MOS construction which is formed on said bulk.

3. The device as set forth in Claim 1, wherein said capacitance read-out portion is a MIS construction which is formed on said bulk.

4. The device as set forth in claim 1, wherein said capacitance read-out portion is a Schottky barrier which is formed on said bulk.

5. The device as set forth in Claim 1, wherein said capacitance read-out portion is any one of a p-type region and an n-type region which are formed on said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

6. The device as set forth in Claim 1 ,wherein said depletion layer control portion is a MOS construction which is formed on said bulk.

7. The device as set forth in Claim 1, wherein said depletion layer control portion is a MIS construction which is formed on said bulk.

8. The device as set forth in Claim 1, wherein said depletion layer control portion is a Schottky barrier which is formed on said bulk.

9. The device as set forth in Claim 1, wherein said depletion layer control portion is any one of a p-type region and an n-type region which are formed on the said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

10. The device as set forth in Claim 1, wherein said depletion layer control portion is any one of a p-type region and an n-type region which are formed within said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

11. A MIS type semiconductor device with a multielectrode construction equivalent to a variable capacitance diode, characterized in that an insulator with a capacitance read-out electrode and at least one p-n junction portion with a control electrode, which is formed between a semiconductor single crystal and any one of a ptype region and an n-type region formed therein, are formed on the bulk of said semiconductor single crystal, a depletion layer within said bulk is changed in width when said p-n junction portion is reverse-biassed through said control electrode, whereby a change in capacitance can be read out through said capacitance read-out electrode.

12. A Schottky type semiconductor device with a multi-electrode construction equivalent to a variable capacitance diode, characterized in that a Schottky barrier with a capacitance read-out electrode, which is formed on an interface between said capacitance read-out electrode and a semiconductor single crystal, and at least one p-n junction portion with a control electrode, which is formed between said semiconductor single crystal and any one of a p-type region and an ntype region formed therein, are formed on the bulk of said semiconductor single crystal, a depletion layer within said bulk is changed in width when said p-n junction portion is reversebiassed through said control electrode, whereby a change in capacitance can be read out through said capacitance read-out electrode.

13. A p-n junction type semiconductor device with a multi-electrode construction equivalent to a variable capacitance diode, characterized in that a first p-n junction portion with a capacitance read-out electrode, which is formed between a semiconductor single crystal and any one of a ptype region and an n-type region formed therein, and at least one second p-n junction portion with a control electrode, which is formed between the semiconductor single crystal and any one of a ptype region and an n-type region formed therein, are formed on the bulk of said semiconductor single crystal, a depletion layer within said bulk is changed in width when said second p-n junction portion is reverse-biassed through said control electrode, whereby a change in capacitance can be read out through said capacitance read-out electrode.

14. A semiconductor device with a multielectrode construction equivalent to a variable capacitance diode, characterized in that a capacitance read-out portion with a capacitance read-out electrode and a plurality of depletion control portions with control electrodes, respectively, are formed in a bulk of a semiconductor single crystal, a depletion layer within said bulk is changed in width when a plurality of said depletion control portions are reverse-biassed in turn through said control electrodes, whereby a change in capacitance can be read out through said capacitance read-out electrode.

15. The device as set forth in Claim 14, wherein said capacitance read-out portion is a MOS construction which is formed on said bulk.

1 6. The device as set forth in Claim 14, wherein said capacitance read-out portion is a MIS construction which is formed on said bulk.

1 7. The device as set forth in Claim 14, wherein said capacitance read-out portion is a Schottky barrier which is formed on said bulk.

18. The device as set forth in Claim 14, wherein said capacitance read-out portion is any one of a p-type region and an n-type region which are formed on said bulk, thereby forming a p-n junction between said semiconductor single crystal and the region.

1 9. The device as set forth in Claim 14, said depletion layer control portions are MOS donstructions which are formed on said bulk.

20. The device as set forth in Claim 14, wherein said depletion layer control portions are MIS constructions which are formed on said bulk.

21. The device as set forth in Claim 14, wherein said depletion layer control portions are Schottky barriers which are formed on said bulk.

22. The device as set forth in Claim 14, wherein said depletion layer control portion is any one of a p-type region and an n-type region which are formed on said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

23. The device as set forth in Claim 14, wherein said depletion layer control portion is any one of a p-type region and an n-type region which are formed on and/or within said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

24. A parametric mixer using a multi-electrode semiconductor device such that a capacitance read-out portion with a capacitance read-out electrode and at least one depletion layer control portion with a control electrode are formed on a bulk of a semiconductor single crystal, a depletion layer within said bulk is changed in width when said depletion layer control portion is reversebiassed through said control electrode, whereby a change in capacitance can be read out through said capacitance read-out electrode, characterized in that a first signal is applied to said control electrode and a second signal is applied to said capacitance read-out electrode to carry out a mixing operation.

25. The parametric mixer as set forth in Claim 24, wherein said capacitance read-out portion is a MOS construction which is formed on said bulk.

26. The parametric mixer as set forth in Claim 24, wherein said capacitance read-out portion is a MIS construction which is formed on said bulk.

27. The parametric mixer as set forth in Claim 24, wherein said capacitance read-out portion is a Schottky barrier which is formed on said bulk.

28. The parametric mixer as set forth in Claim 24, wherein said capacitance read-out portion is any one of a p-type region and an n-type region which are formed on said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

29. The parametric mixer as set forth in Claim 24, wherein said depletion layer control portion is a MOS construction which is formed on said bulk.

30. The parametric mixer as set forth in Claim 24, wherein said depletion layer control portion is a MIS construction which is formed on said bulk.

31. The parametric mixer as set forth in Claim 24, wherein said depletion layer control portion is a Schottky barrier which is formed on said bulk.

32. The parametric mixer as set forth in Claim 24, wherein said depletion layer control portion is any one of a p-type region and an n-type region which are formed on said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

33. The parametric mixer as set forth in Claim 24, wherein said depletion layer control portion is any one of a p-type region and an n-type region which is formed within said bulk, thereby forming a p-n junction between said semiconductor single crystal and said region.

34. A semiconductor device substantially as herein described with reference to each of the embodiments shown in Figures 1-8 of the accompanying drawings.

35. A parametric mixer substantially as herein described with reference to each of the embodiments shown in Figures 12~32 of the accompanying drawings.