FR3076398B1 - Transistor et son procede de fabrication - Google Patents
Transistor et son procede de fabrication Download PDFInfo
- Publication number
- FR3076398B1 FR3076398B1 FR1763408A FR1763408A FR3076398B1 FR 3076398 B1 FR3076398 B1 FR 3076398B1 FR 1763408 A FR1763408 A FR 1763408A FR 1763408 A FR1763408 A FR 1763408A FR 3076398 B1 FR3076398 B1 FR 3076398B1
- Authority
- FR
- France
- Prior art keywords
- transistor
- active layer
- dimension
- extension
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6743—Silicon
- H10D30/6744—Monocrystalline silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
La présente invention concerne un transistor porté par un substrat comprenant une couche active, le transistor comprenant : a) au moins une zone source (3a) et au moins une zone drain (3b) ; b) au moins une zone de contact électrique (3c) ; c) au moins un canal de conduction ; d) au moins une grille (4a) ; ledit transistor étant caractérisé en ce que ladite grille (4a) comprend : (1) une portion longitudinale (4b) ; (2) une portion transversale (4c) s'étendant de part et d'autre d'une portion de la couche active (1 a) et comprenant : (a) au moins une première partie (4c1) s'étendant au-delà d'une partie d'un premier côté de ladite portion de la couche active (1a) sur une première dimension d'extension I2 ; (b) au moins une deuxième partie (4c2) s'étendant au-delà d'une partie d'un deuxième côté de ladite portion de la couche active (1a) sur une deuxième dimension d'extension I3 ; et en ce que : I2 > I3 avec I3 ≠ 0.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1763408A FR3076398B1 (fr) | 2017-12-29 | 2017-12-29 | Transistor et son procede de fabrication |
US16/232,826 US11031505B2 (en) | 2017-12-29 | 2018-12-26 | Transistor and its manufacturing process |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1763408 | 2017-12-29 | ||
FR1763408A FR3076398B1 (fr) | 2017-12-29 | 2017-12-29 | Transistor et son procede de fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3076398A1 FR3076398A1 (fr) | 2019-07-05 |
FR3076398B1 true FR3076398B1 (fr) | 2019-12-27 |
Family
ID=61873503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1763408A Active FR3076398B1 (fr) | 2017-12-29 | 2017-12-29 | Transistor et son procede de fabrication |
Country Status (2)
Country | Link |
---|---|
US (1) | US11031505B2 (fr) |
FR (1) | FR3076398B1 (fr) |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6307237B1 (en) * | 1999-12-28 | 2001-10-23 | Honeywell International Inc. | L-and U-gate devices for SOI/SOS applications |
JP4614522B2 (ja) * | 2000-10-25 | 2011-01-19 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US6620656B2 (en) * | 2001-12-19 | 2003-09-16 | Motorola, Inc. | Method of forming body-tied silicon on insulator semiconductor device |
JP2003318405A (ja) * | 2002-04-25 | 2003-11-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP4294935B2 (ja) * | 2002-10-17 | 2009-07-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US6905919B2 (en) * | 2003-07-29 | 2005-06-14 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a partially depleted silicon on insulator (PDSOI) transistor with a pad lock body extension |
US7011980B1 (en) * | 2005-05-09 | 2006-03-14 | International Business Machines Corporation | Method and structures for measuring gate tunneling leakage parameters of field effect transistors |
JP4565512B2 (ja) * | 2006-09-27 | 2010-10-20 | Okiセミコンダクタ株式会社 | Fetの容量取得用tegおよび容量取得方法 |
US8946819B2 (en) * | 2013-05-08 | 2015-02-03 | Globalfoundries Singapore Pte. Ltd. | Silicon-on-insulator integrated circuits with local oxidation of silicon and methods for fabricating the same |
US9685364B2 (en) * | 2014-09-05 | 2017-06-20 | Globalfoundries Singapore Pte. Ltd. | Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same |
US9421087B1 (en) * | 2015-04-27 | 2016-08-23 | International Business Machines Corporation | Artificial electronic skin |
US9780207B2 (en) * | 2015-12-30 | 2017-10-03 | Globalfoundries Singapore Pte. Ltd. | Self-aligned high voltage LDMOS |
-
2017
- 2017-12-29 FR FR1763408A patent/FR3076398B1/fr active Active
-
2018
- 2018-12-26 US US16/232,826 patent/US11031505B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR3076398A1 (fr) | 2019-07-05 |
US20190245097A1 (en) | 2019-08-08 |
US11031505B2 (en) | 2021-06-08 |
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