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FR2957189B1 - Procede de realisation d'une structure multicouche avec detourage post meulage. - Google Patents

Procede de realisation d'une structure multicouche avec detourage post meulage.

Info

Publication number
FR2957189B1
FR2957189B1 FR1051485A FR1051485A FR2957189B1 FR 2957189 B1 FR2957189 B1 FR 2957189B1 FR 1051485 A FR1051485 A FR 1051485A FR 1051485 A FR1051485 A FR 1051485A FR 2957189 B1 FR2957189 B1 FR 2957189B1
Authority
FR
France
Prior art keywords
making
multilayer structure
post grinding
grinding
post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1051485A
Other languages
English (en)
Other versions
FR2957189A1 (fr
Inventor
Alexandre Vaufredaz
Sebastien Molinari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1051485A priority Critical patent/FR2957189B1/fr
Priority to DE102011002546.4A priority patent/DE102011002546B4/de
Priority to US13/043,088 priority patent/US8298916B2/en
Publication of FR2957189A1 publication Critical patent/FR2957189A1/fr
Application granted granted Critical
Publication of FR2957189B1 publication Critical patent/FR2957189B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Micromachines (AREA)
FR1051485A 2010-03-02 2010-03-02 Procede de realisation d'une structure multicouche avec detourage post meulage. Expired - Fee Related FR2957189B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1051485A FR2957189B1 (fr) 2010-03-02 2010-03-02 Procede de realisation d'une structure multicouche avec detourage post meulage.
DE102011002546.4A DE102011002546B4 (de) 2010-03-02 2011-01-12 Verfahren zum Herstellen einer mehrschichtigen Struktur mit Trimmen nach dem Schleifen
US13/043,088 US8298916B2 (en) 2010-03-02 2011-03-08 Process for fabricating a multilayer structure with post-grinding trimming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1051485A FR2957189B1 (fr) 2010-03-02 2010-03-02 Procede de realisation d'une structure multicouche avec detourage post meulage.

Publications (2)

Publication Number Publication Date
FR2957189A1 FR2957189A1 (fr) 2011-09-09
FR2957189B1 true FR2957189B1 (fr) 2012-04-27

Family

ID=42710764

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1051485A Expired - Fee Related FR2957189B1 (fr) 2010-03-02 2010-03-02 Procede de realisation d'une structure multicouche avec detourage post meulage.

Country Status (3)

Country Link
US (1) US8298916B2 (fr)
DE (1) DE102011002546B4 (fr)
FR (1) FR2957189B1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2950734B1 (fr) * 2009-09-28 2011-12-09 Soitec Silicon On Insulator Procede de collage et de transfert d'une couche
DE102010005904B4 (de) * 2010-01-27 2012-11-22 Siltronic Ag Verfahren zur Herstellung einer Halbleiterscheibe
FR2957190B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
US9064770B2 (en) * 2012-07-17 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for minimizing edge peeling in the manufacturing of BSI chips
US10464184B2 (en) * 2014-05-07 2019-11-05 Applied Materials, Inc. Modifying substrate thickness profiles
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
JP2017004989A (ja) * 2015-06-04 2017-01-05 株式会社ディスコ ウエーハの製造方法及びウエーハ製造装置
KR20180090494A (ko) 2017-02-03 2018-08-13 삼성전자주식회사 기판 구조체 제조 방법
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
FR3076073B1 (fr) * 2017-12-22 2020-06-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de detourage de plaque
TWI668739B (zh) * 2018-04-03 2019-08-11 環球晶圓股份有限公司 磊晶基板及其製造方法
US10553474B1 (en) 2018-08-29 2020-02-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor-on-insulator (SOI) substrate
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
US11923205B2 (en) 2021-12-17 2024-03-05 United Microelectronics Corporation Method for manufacturing semiconductor device
CN115579374B (zh) * 2022-12-12 2023-04-07 合肥新晶集成电路有限公司 背照式图像传感器的制备方法及背照式图像传感器

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0389519A (ja) 1989-08-31 1991-04-15 Sony Corp 半導体基板の製法
JPH0719737B2 (ja) 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH0636413B2 (ja) 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH04263425A (ja) * 1991-02-18 1992-09-18 Toshiba Corp 半導体基板の研削装置及び研削方法
JPH0799295A (ja) * 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
JP2662495B2 (ja) 1993-06-28 1997-10-15 住友シチックス株式会社 接着半導体基板の製造方法
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US5937312A (en) * 1995-03-23 1999-08-10 Sibond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator wafers
JPH0917984A (ja) 1995-06-29 1997-01-17 Sumitomo Sitix Corp 貼り合わせｓｏｉ基板の製造方法
JP3620554B2 (ja) * 1996-03-25 2005-02-16 信越半導体株式会社 半導体ウェーハ製造方法
JP3352896B2 (ja) * 1997-01-17 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JP3352902B2 (ja) 1997-02-21 2002-12-03 信越半導体株式会社 貼り合わせ基板の作製方法
JP3132425B2 (ja) 1997-06-20 2001-02-05 日本電気株式会社 衛星イントラネットサービスにおける通信時間短縮方式
ATE268943T1 (de) 1998-02-04 2004-06-15 Canon Kk Soi substrat
JP3635200B2 (ja) * 1998-06-04 2005-04-06 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JPH11354761A (ja) 1998-06-09 1999-12-24 Sumitomo Metal Ind Ltd Ｓｏｉ基板及びその製造方法
US20020187595A1 (en) * 1999-08-04 2002-12-12 Silicon Evolution, Inc. Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality
EP1170801B1 (fr) 1999-10-14 2006-07-26 Shin-Etsu Handotai Company Limited Procede de production de tranches collees
JP3632531B2 (ja) 1999-11-17 2005-03-23 株式会社デンソー 半導体基板の製造方法
WO2001073831A1 (fr) 2000-03-29 2001-10-04 Shin-Etsu Handotai Co., Ltd. Procede d'obtention de tranches de silicium ou de soi et tranches ainsi obtenues
JP3991300B2 (ja) * 2000-04-28 2007-10-17 株式会社Ｓｕｍｃｏ 張り合わせ誘電体分離ウェーハの製造方法
DE10058305A1 (de) * 2000-11-24 2002-06-06 Wacker Siltronic Halbleitermat Verfahren zur Oberflächenpolitur von Siliciumscheiben
JP2003163335A (ja) * 2001-11-27 2003-06-06 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
KR100577627B1 (ko) 2002-05-20 2006-05-10 주식회사 사무코 접합기판과 그 제조방법 및 그것에 사용되는 웨이퍼 외주가압용 지그류
US6841848B2 (en) * 2003-06-06 2005-01-11 Analog Devices, Inc. Composite semiconductor wafer and a method for forming the composite semiconductor wafer
FR2860842B1 (fr) * 2003-10-14 2007-11-02 Tracit Technologies Procede de preparation et d'assemblage de substrats
US7442992B2 (en) * 2004-05-19 2008-10-28 Sumco Corporation Bonded SOI substrate, and method for manufacturing the same
KR101151458B1 (ko) 2005-02-28 2012-06-01 신에쯔 한도타이 가부시키가이샤 접합 웨이퍼의 제조방법 및 접합 웨이퍼
JP4918229B2 (ja) 2005-05-31 2012-04-18 信越半導体株式会社 貼り合わせウエーハの製造方法
JP5122731B2 (ja) * 2005-06-01 2013-01-16 信越半導体株式会社 貼り合わせウェーハの製造方法
JP4839818B2 (ja) * 2005-12-16 2011-12-21 信越半導体株式会社 貼り合わせ基板の製造方法
JP5028845B2 (ja) * 2006-04-14 2012-09-19 株式会社Ｓｕｍｃｏ 貼り合わせウェーハ及びその製造方法
JP2007317988A (ja) 2006-05-29 2007-12-06 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法
EP2075830A3 (fr) * 2007-10-11 2011-01-19 Sumco Corporation Procédé de production de plaquette fixée
FR2935535B1 (fr) 2008-09-02 2010-12-10 S O I Tec Silicon On Insulator Tech Procede de detourage mixte.
FR2957190B1 (fr) * 2010-03-02 2012-04-27 Soitec Silicon On Insulator Procede de realisation d'une structure multicouche avec detourage par effets thermomecaniques.
US20120028439A1 (en) * 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor And Solar Wafers And Method For Processing Same

Also Published As

Publication number Publication date
DE102011002546B4 (de) 2017-10-12
US20110230003A1 (en) 2011-09-22
DE102011002546A1 (de) 2011-09-08
FR2957189A1 (fr) 2011-09-09
US8298916B2 (en) 2012-10-30

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