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FR2931293B1 - Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante - Google Patents

Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante

Info

Publication number
FR2931293B1
FR2931293B1 FR0853150A FR0853150A FR2931293B1 FR 2931293 B1 FR2931293 B1 FR 2931293B1 FR 0853150 A FR0853150 A FR 0853150A FR 0853150 A FR0853150 A FR 0853150A FR 2931293 B1 FR2931293 B1 FR 2931293B1
Authority
FR
France
Prior art keywords
heterostructure
epitaxia
manufacturing
support
corresponding heterostructure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0853150A
Other languages
English (en)
Other versions
FR2931293A1 (fr
Inventor
Bruce Faure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0853150A priority Critical patent/FR2931293B1/fr
Priority to US12/463,873 priority patent/US8105916B2/en
Publication of FR2931293A1 publication Critical patent/FR2931293A1/fr
Application granted granted Critical
Publication of FR2931293B1 publication Critical patent/FR2931293B1/fr
Priority to US13/341,489 priority patent/US8564019B2/en
Priority to US13/341,462 priority patent/US8481407B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
FR0853150A 2008-05-15 2008-05-15 Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante Active FR2931293B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0853150A FR2931293B1 (fr) 2008-05-15 2008-05-15 Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante
US12/463,873 US8105916B2 (en) 2008-05-15 2009-05-11 Relaxation and transfer of strained layers
US13/341,489 US8564019B2 (en) 2008-05-15 2011-12-30 Heterostructures comprising crystalline strain relaxation layers
US13/341,462 US8481407B2 (en) 2008-05-15 2011-12-30 Processes for fabricating heterostructures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0853150A FR2931293B1 (fr) 2008-05-15 2008-05-15 Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante

Publications (2)

Publication Number Publication Date
FR2931293A1 FR2931293A1 (fr) 2009-11-20
FR2931293B1 true FR2931293B1 (fr) 2010-09-03

Family

ID=40111101

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0853150A Active FR2931293B1 (fr) 2008-05-15 2008-05-15 Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante

Country Status (2)

Country Link
US (3) US8105916B2 (fr)
FR (1) FR2931293B1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2931293B1 (fr) * 2008-05-15 2010-09-03 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante
US9455146B2 (en) * 2009-12-17 2016-09-27 California Institute Of Technology Virtual substrates for epitaxial growth and methods of making the same
WO2011126528A1 (fr) * 2010-04-08 2011-10-13 California Institute Of Technology Substrats virtuels pour croissance épitaxiale et leurs procédés de fabrication
US8536022B2 (en) * 2010-05-19 2013-09-17 Koninklijke Philips N.V. Method of growing composite substrate using a relaxed strained layer
FR2972567B1 (fr) 2011-03-09 2013-03-22 Soitec Silicon On Insulator Méthode de formation d'une structure de ge sur iii/v sur isolant
US8471243B1 (en) 2012-01-31 2013-06-25 Soitec Photoactive devices with improved distribution of charge carriers, and methods of forming same
KR20140119714A (ko) * 2012-01-31 2014-10-10 소이텍 향상된 전하 캐리어들의 분포를 갖는 광활성 장치들 및 그 형성 방법들
US9257339B2 (en) * 2012-05-04 2016-02-09 Silicon Genesis Corporation Techniques for forming optoelectronic devices
WO2014066740A1 (fr) * 2012-10-26 2014-05-01 Element Six Technologies Us Corporation Dispositif à semi-conducteurs à fiabilité et durée de vie améliorées et leurs procédés de fabrication
US20150048301A1 (en) * 2013-08-19 2015-02-19 Micron Technology, Inc. Engineered substrates having mechanically weak structures and associated systems and methods
EP3132613A1 (fr) * 2014-04-15 2017-02-22 Telefonaktiebolaget LM Ericsson (publ) Télévision sociale synchronisée
US11714231B2 (en) * 2020-05-14 2023-08-01 The Boeing Company Silicon carbide and nitride structures on a substrate
CN113868850B (zh) * 2021-09-17 2024-05-28 北京航空航天大学 一种基于对称性和标准定向的高通量弹性性质计算方法

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US4994867A (en) * 1988-07-22 1991-02-19 Xerox Corporation Intermediate buffer films with low plastic deformation threshold for lattice mismatched heteroepitaxy
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
DE69737086T2 (de) 1996-08-27 2007-05-16 Seiko Epson Corp. Trennverfahren, verfahren zur übertragung eines dünnfilmbauelements, und unter verwendung des übertragungsverfahrens hergestelltes flüssigkristall-anzeigebauelement
FR2775121B1 (fr) * 1998-02-13 2000-05-05 Picogiga Sa Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US20030064535A1 (en) * 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
FR2844634B1 (fr) * 2002-09-18 2005-05-27 Soitec Silicon On Insulator Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US7348260B2 (en) * 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7812340B2 (en) * 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
FR2860248B1 (fr) * 2003-09-26 2006-02-17 Centre Nat Rech Scient Procede de realisation de substrats autosupportes de nitrures d'elements iii par hetero-epitaxie sur une couche sacrificielle
FR2860249B1 (fr) 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
US6972247B2 (en) * 2003-12-05 2005-12-06 International Business Machines Corporation Method of fabricating strained Si SOI wafers
JP4720125B2 (ja) * 2004-08-10 2011-07-13 日立電線株式会社 Ｉｉｉ−ｖ族窒化物系半導体基板及びその製造方法並びにｉｉｉ−ｖ族窒化物系半導体
US7585792B2 (en) * 2005-02-09 2009-09-08 S.O.I.Tec Silicon On Insulator Technologies Relaxation of a strained layer using a molten layer
WO2006093817A2 (fr) * 2005-02-28 2006-09-08 Silicon Genesis Corporation Procede pour rigidite de substrat et dispositif resultant pour traitements a transfert de couche
US7273798B2 (en) * 2005-08-01 2007-09-25 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Gallium nitride device substrate containing a lattice parameter altering element
US7399686B2 (en) * 2005-09-01 2008-07-15 International Business Machines Corporation Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate
US8334155B2 (en) * 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
US20070069225A1 (en) * 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc III-V light emitting device
FR2895420B1 (fr) 2005-12-27 2008-02-22 Tracit Technologies Sa Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.
US7494902B2 (en) * 2006-06-23 2009-02-24 Interuniversitair Microelektronica Centrum Vzw (Imec) Method of fabricating a strained multi-gate transistor
JP5003033B2 (ja) * 2006-06-30 2012-08-15 住友電気工業株式会社 ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法
EP1901345A1 (fr) * 2006-08-30 2008-03-19 Siltronic AG Galette semiconductrice multicouches et procédé de fabrication correspondant.
WO2008060349A2 (fr) * 2006-11-15 2008-05-22 The Regents Of The University Of California Procédé pour une croissance hétéroépitaxiale de gan, inn, et ain à face n de haute qualité et pour leurs alliages par un dépôt chimique en phase vapeur organique de métal
FR2931293B1 (fr) * 2008-05-15 2010-09-03 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure support d'epitaxie et heterostructure correspondante

Also Published As

Publication number Publication date
US8481407B2 (en) 2013-07-09
US8105916B2 (en) 2012-01-31
US20120098033A1 (en) 2012-04-26
US8564019B2 (en) 2013-10-22
US20120100691A1 (en) 2012-04-26
FR2931293A1 (fr) 2009-11-20
US20100025728A1 (en) 2010-02-04

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