[go: up one dir, main page]

FR2926674B1 - Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable - Google Patents

Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable

Info

Publication number
FR2926674B1
FR2926674B1 FR0850359A FR0850359A FR2926674B1 FR 2926674 B1 FR2926674 B1 FR 2926674B1 FR 0850359 A FR0850359 A FR 0850359A FR 0850359 A FR0850359 A FR 0850359A FR 2926674 B1 FR2926674 B1 FR 2926674B1
Authority
FR
France
Prior art keywords
bonding layer
thin film
composite structure
thickness
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0850359A
Other languages
English (en)
Other versions
FR2926674A1 (fr
Inventor
Bruce Faure
Alexandra Marcovecchio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0850359A priority Critical patent/FR2926674B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to EP08871508A priority patent/EP2232545B1/fr
Priority to KR1020107015993A priority patent/KR101534364B1/ko
Priority to JP2010543408A priority patent/JP5420569B2/ja
Priority to PCT/EP2008/068311 priority patent/WO2009092506A2/fr
Priority to CN200880125235.6A priority patent/CN101925994B/zh
Priority to US12/663,693 priority patent/US20100190000A1/en
Priority to AT08871508T priority patent/ATE556433T1/de
Publication of FR2926674A1 publication Critical patent/FR2926674A1/fr
Application granted granted Critical
Publication of FR2926674B1 publication Critical patent/FR2926674B1/fr
Priority to US14/031,498 priority patent/US9242444B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02469—Group 12/16 materials
    • H01L21/02472—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264—Up to 3 mils
    • Y10T428/265—1 mil or less

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Recrystallisation Techniques (AREA)
  • Measuring Fluid Pressure (AREA)
  • Laminated Bodies (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Ceramic Products (AREA)
FR0850359A 2008-01-21 2008-01-21 Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable Expired - Fee Related FR2926674B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR0850359A FR2926674B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
KR1020107015993A KR101534364B1 (ko) 2008-01-21 2008-12-29 안정한 산화물 접착층을 가지는 합성구조를 제작하는 방법
JP2010543408A JP5420569B2 (ja) 2008-01-21 2008-12-29 安定した酸化物結合層を有する複合構造の製造方法
PCT/EP2008/068311 WO2009092506A2 (fr) 2008-01-21 2008-12-29 Procédé de fabrication d'une structure composite avec une couche de liage stable d'oxyde
EP08871508A EP2232545B1 (fr) 2008-01-21 2008-12-29 Procédé de fabrication d'une structure composite avec une couche d'oxyde de collage stable
CN200880125235.6A CN101925994B (zh) 2008-01-21 2008-12-29 具有稳定的氧化物结合层的复合结构的制造方法
US12/663,693 US20100190000A1 (en) 2008-01-21 2008-12-29 Method of fabricating a composite structure with a stable bonding layer of oxide
AT08871508T ATE556433T1 (de) 2008-01-21 2008-12-29 Herstellungsverfahren einer verbundstruktur mit einer stabilen oxidbindungsschicht
US14/031,498 US9242444B2 (en) 2008-01-21 2013-09-19 Method of fabricating a composite structure with a stable bonding layer of oxide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0850359A FR2926674B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable

Publications (2)

Publication Number Publication Date
FR2926674A1 FR2926674A1 (fr) 2009-07-24
FR2926674B1 true FR2926674B1 (fr) 2010-03-26

Family

ID=39767085

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0850359A Expired - Fee Related FR2926674B1 (fr) 2008-01-21 2008-01-21 Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable

Country Status (8)

Country Link
US (2) US20100190000A1 (fr)
EP (1) EP2232545B1 (fr)
JP (1) JP5420569B2 (fr)
KR (1) KR101534364B1 (fr)
CN (1) CN101925994B (fr)
AT (1) ATE556433T1 (fr)
FR (1) FR2926674B1 (fr)
WO (1) WO2009092506A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
US20130264587A1 (en) * 2012-04-04 2013-10-10 Phostek, Inc. Stacked led device using oxide bonding
FR3007892B1 (fr) * 2013-06-27 2015-07-31 Commissariat Energie Atomique Procede de transfert d'une couche mince avec apport d'energie thermique a une zone fragilisee via une couche inductive
FR3032555B1 (fr) * 2015-02-10 2018-01-19 Soitec Procede de report d'une couche utile
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
FR3068508B1 (fr) * 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
FR3077923B1 (fr) * 2018-02-12 2021-07-16 Soitec Silicon On Insulator Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche
FR3078822B1 (fr) * 2018-03-12 2020-02-28 Soitec Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin
FR3079346B1 (fr) 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
US11315789B2 (en) * 2019-04-24 2022-04-26 Tokyo Electron Limited Method and structure for low density silicon oxide for fusion bonding and debonding
JP7204625B2 (ja) * 2019-07-25 2023-01-16 信越化学工業株式会社 Ｉｉｉ族化合物基板の製造方法及びその製造方法により製造した基板
JP2023018972A (ja) * 2021-07-28 2023-02-09 信越化学工業株式会社 スピン波励起検出構造体の製造方法
CN113903834B (zh) * 2021-08-23 2023-10-13 华灿光电（浙江）有限公司 覆晶红光二极管芯片及其制备方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US76559A (en) * 1868-04-07 Alexander g
US255341A (en) * 1882-03-21 Tug-buckle
US241958A (en) * 1881-05-24 galland
US5882532A (en) * 1996-05-31 1999-03-16 Hewlett-Packard Company Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US5985742A (en) * 1997-05-12 1999-11-16 Silicon Genesis Corporation Controlled cleavage process and device for patterned films
FR2767604B1 (fr) 1997-08-19 2000-12-01 Commissariat Energie Atomique Procede de traitement pour le collage moleculaire et le decollage de deux structures
JP2000349264A (ja) * 1998-12-04 2000-12-15 Canon Inc 半導体ウエハの製造方法、使用方法および利用方法
FR2789518B1 (fr) * 1999-02-10 2003-06-20 Commissariat Energie Atomique Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure
US6335263B1 (en) * 2000-03-22 2002-01-01 The Regents Of The University Of California Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
FR2817394B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US7407869B2 (en) * 2000-11-27 2008-08-05 S.O.I.Tec Silicon On Insulator Technologies Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
DE10325150A1 (de) * 2003-05-31 2004-12-30 Hahn-Meitner-Institut Berlin Gmbh Parametrierte Halbleiterverbundstruktur mit integrierten Dotierungskanälen, Verfahren zur Herstellung und Anwendung davon
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
FR2857983B1 (fr) 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2857982B1 (fr) * 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2860249B1 (fr) * 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
FR2864970B1 (fr) * 2004-01-09 2006-03-03 Soitec Silicon On Insulator Substrat a support a coefficient de dilatation thermique determine
WO2006029651A1 (fr) * 2004-09-16 2006-03-23 S.O.I.Tec Silicon On Insulator Technologies Procede de fabrication d'une couche de dioxyde de silicium
WO2006034120A2 (fr) * 2004-09-17 2006-03-30 Massachusetts Institute Of Technology Dispositifs hyperfrequence reglables a bst integre faisant appel a un procede de transfert de couche tampon
FR2877491B1 (fr) * 2004-10-29 2007-01-19 Soitec Silicon On Insulator Structure composite a forte dissipation thermique
JP5364368B2 (ja) * 2005-04-21 2013-12-11 エイオーネックス・テクノロジーズ・インコーポレイテッド 基板の製造方法
FR2888663B1 (fr) * 2005-07-13 2008-04-18 Soitec Silicon On Insulator Procede de diminution de la rugosite d'une couche epaisse d'isolant
FR2890489B1 (fr) 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
JP5003033B2 (ja) * 2006-06-30 2012-08-15 住友電気工業株式会社 ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
CN101573786B (zh) * 2007-02-08 2011-09-28 硅绝缘体技术有限公司 高散热性基片的制造方法
US7767542B2 (en) * 2007-04-20 2010-08-03 Semiconductor Energy Laboratory Co., Ltd Manufacturing method of SOI substrate
JP5280015B2 (ja) * 2007-05-07 2013-09-04 信越半導体株式会社 Ｓｏｉ基板の製造方法
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
KR100976422B1 (ko) * 2007-12-28 2010-08-18 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성 방법
FR2926672B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable

Also Published As

Publication number Publication date
JP2011510503A (ja) 2011-03-31
FR2926674A1 (fr) 2009-07-24
KR20100103617A (ko) 2010-09-27
WO2009092506A3 (fr) 2009-11-19
KR101534364B1 (ko) 2015-07-06
US20140014029A1 (en) 2014-01-16
EP2232545B1 (fr) 2012-05-02
US9242444B2 (en) 2016-01-26
JP5420569B2 (ja) 2014-02-19
ATE556433T1 (de) 2012-05-15
EP2232545A2 (fr) 2010-09-29
US20100190000A1 (en) 2010-07-29
CN101925994B (zh) 2017-05-17
CN101925994A (zh) 2010-12-22
WO2009092506A2 (fr) 2009-07-30

Similar Documents

Publication Publication Date Title
FR2926674B1 (fr) Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
FR2926672B1 (fr) Procede de fabrication de couches de materiau epitaxie
Rolston et al. Engineering stress in perovskite solar cells to improve stability
TWI384583B (zh) 擴散阻障層及製造擴散阻障層之方法
DE602007011470D1 (de) Verfahren zur herstellung kristalliner silizium-so
MX2010009367A (es) Célula solar que tiene homounión p-n de silicio cristalino y heterouniones de silio amorfo para pasivación de superficie.
DE502008003135D1 (de) Verbund aus mindestens zwei halbleitersubstraten sowie herstellungsverfahren
JP2009111373A5 (fr)
JP2010133897A5 (fr)
WO2008120469A1 (fr) Procédé permettant de fabriquer un élément semi-conducteur de carbure de silicium
WO2009061353A3 (fr) Fabrication de couches autonomes à semi-conducteurs par traitement thermique de substrats par un polymère
NO20093092L (no) Flerskiktspolymer mellomskikt som har en preget overflate
FR2963982B1 (fr) Procede de collage a basse temperature
WO2016086616A1 (fr) Substrat d'affichage et son procédé de fabrication, et dispositif d'affiche
WO2020056867A1 (fr) Panneau d'affichage souple et son procédé de préparation
DE602004014533D1 (de) Substrat mit bestimmtem wärmeausdehnungskoeffizienten
WO2008102258A3 (fr) Préparation de substrat pour fabrication de film mince optimisé à partir de nanoparticules semi-conductrices de groupe iv
US10077188B2 (en) Manufacturing method of MEMS chip
WO2008139684A1 (fr) Procédé de fabrication de substrat de silicium sur isolant et substrat de silicium sur isolant
FR2921750B1 (fr) Formation selective d'un compose comprenant un materiau semi-conducteur et un materiau metallique dans un substrat, a travers une couche d'oxyde de germanium
JP6614551B2 (ja) 電子素子の中間材の製造方法、電子素子の製造方法および電子素子の中間材
JP2008097829A5 (fr)
WO2011160814A3 (fr) Procédé de création d'une région dopée au bore passivé, en particulier lors de la fabrication d'une cellule solaire, et cellule solaire présentant une région de diffusion de bore passivé
WO2018176769A1 (fr) Structure stratifiée et son procédé de préparation
US9969152B2 (en) Method for producing glass substrate

Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120907

ST Notification of lapse

Effective date: 20140930