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FR2910702B1 - Procede de fabrication d'un substrat mixte - Google Patents

Procede de fabrication d'un substrat mixte

Info

Publication number
FR2910702B1
FR2910702B1 FR0655950A FR0655950A FR2910702B1 FR 2910702 B1 FR2910702 B1 FR 2910702B1 FR 0655950 A FR0655950 A FR 0655950A FR 0655950 A FR0655950 A FR 0655950A FR 2910702 B1 FR2910702 B1 FR 2910702B1
Authority
FR
France
Prior art keywords
manufacturing
mixed substrate
mixed
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0655950A
Other languages
English (en)
Other versions
FR2910702A1 (fr
Inventor
Marek Kostrzewa
Fabrice Letertre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0655950A priority Critical patent/FR2910702B1/fr
Priority to US11/766,463 priority patent/US7422958B2/en
Priority to PCT/EP2007/063829 priority patent/WO2008077796A1/fr
Priority to JP2009543435A priority patent/JP2010515248A/ja
Priority to EP07857491A priority patent/EP2102903A1/fr
Publication of FR2910702A1 publication Critical patent/FR2910702A1/fr
Application granted granted Critical
Publication of FR2910702B1 publication Critical patent/FR2910702B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
FR0655950A 2006-12-26 2006-12-26 Procede de fabrication d'un substrat mixte Expired - Fee Related FR2910702B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0655950A FR2910702B1 (fr) 2006-12-26 2006-12-26 Procede de fabrication d'un substrat mixte
US11/766,463 US7422958B2 (en) 2006-12-26 2007-06-21 Method of fabricating a mixed substrate
PCT/EP2007/063829 WO2008077796A1 (fr) 2006-12-26 2007-12-12 Procédé de fabrication d'un substrat mélangé
JP2009543435A JP2010515248A (ja) 2006-12-26 2007-12-12 混合基材の製造方法
EP07857491A EP2102903A1 (fr) 2006-12-26 2007-12-12 Procede de fabrication d'un substrat melange

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0655950A FR2910702B1 (fr) 2006-12-26 2006-12-26 Procede de fabrication d'un substrat mixte

Publications (2)

Publication Number Publication Date
FR2910702A1 FR2910702A1 (fr) 2008-06-27
FR2910702B1 true FR2910702B1 (fr) 2009-04-03

Family

ID=38134174

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0655950A Expired - Fee Related FR2910702B1 (fr) 2006-12-26 2006-12-26 Procede de fabrication d'un substrat mixte

Country Status (5)

Country Link
US (1) US7422958B2 (fr)
EP (1) EP2102903A1 (fr)
JP (1) JP2010515248A (fr)
FR (1) FR2910702B1 (fr)
WO (1) WO2008077796A1 (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919006B2 (en) * 2007-10-31 2011-04-05 Freescale Semiconductor, Inc. Method of anti-stiction dimple formation under MEMS
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
FR2936356B1 (fr) * 2008-09-23 2010-10-22 Soitec Silicon On Insulator Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant
FR2937794A1 (fr) * 2008-10-28 2010-04-30 Soitec Silicon On Insulator Procede de traitement d'une structure de type semi-conducteur sur isolant par dissolution selective de sa couche d'oxyde
KR101105918B1 (ko) * 2009-11-30 2012-01-17 주식회사 엘지실트론 질화물 반도체 소자의 제조방법
US8330245B2 (en) * 2010-02-25 2012-12-11 Memc Electronic Materials, Inc. Semiconductor wafers with reduced roll-off and bonded and unbonded SOI structures produced from same
WO2012015022A1 (fr) * 2010-07-30 2012-02-02 京セラ株式会社 Substrat composite, composant électronique, procédé de production d'un substrat composite, et procédé de fabrication du composant électronique
US20120107992A1 (en) * 2010-10-28 2012-05-03 Freescale Semiconductor, Inc. Method of producing layered wafer structure having anti-stiction bumps
JP5454485B2 (ja) * 2011-02-09 2014-03-26 信越半導体株式会社 貼り合わせ基板の製造方法
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
KR102007258B1 (ko) * 2012-11-21 2019-08-05 삼성전자주식회사 광전 집적회로 기판의 제조방법
US9290380B2 (en) 2012-12-18 2016-03-22 Freescale Semiconductor, Inc. Reducing MEMS stiction by deposition of nanoclusters
WO2016149113A1 (fr) * 2015-03-17 2016-09-22 Sunedison Semiconductor Limited Couche de piégeage de charge thermiquement stable destinée à être utilisée dans la fabrication de structures semi-conducteur sur isolant
WO2016196011A1 (fr) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited Procédé de fabrication de silicium-germanium sur isolant
WO2016196060A1 (fr) 2015-06-01 2016-12-08 Sunedison Semiconductor Limited Procédé de fabrication d'un semiconducteur sur isolateur
JP6719600B2 (ja) * 2016-06-24 2020-07-08 クロミス，インコーポレイテッド 多結晶セラミック基板およびその製造方法
JP6831911B2 (ja) 2016-10-26 2021-02-17 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 向上した電荷捕獲効率を有する高抵抗率シリコンオンインシュレータ基板
FR3068508B1 (fr) * 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
FR3079659B1 (fr) * 2018-03-29 2020-03-13 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree
US11705395B2 (en) * 2018-06-25 2023-07-18 Intel Corporation Core fill to reduce dishing and metal pillar fill to increase metal density of interconnects
FR3086096B1 (fr) * 2018-09-14 2021-08-27 Soitec Silicon On Insulator Procede de realisation d'un substrat avance pour une integration hybride
CN111244273A (zh) * 2020-03-10 2020-06-05 上海华力微电子有限公司 改善rram阻变结构下电极凹陷的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238865A (en) * 1990-09-21 1993-08-24 Nippon Steel Corporation Process for producing laminated semiconductor substrate
EP0701286B1 (fr) * 1994-06-16 1999-11-24 Nec Corporation Substrat à silicium sur isolateur et procédé de sa fabrication
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US6613643B1 (en) * 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
JP2002198525A (ja) * 2000-12-27 2002-07-12 Toshiba Corp 半導体装置及びその製造方法
US6846727B2 (en) * 2001-05-21 2005-01-25 International Business Machines Corporation Patterned SOI by oxygen implantation and annealing
FR2847077B1 (fr) * 2002-11-12 2006-02-17 Soitec Silicon On Insulator Composants semi-conducteurs, et notamment de type soi mixtes, et procede de realisation
FR2850487B1 (fr) 2002-12-24 2005-12-09 Commissariat Energie Atomique Procede de realisation de substrats mixtes et structure ainsi obtenue
KR100529667B1 (ko) * 2003-01-09 2005-11-17 동부아남반도체 주식회사 반도체 소자의 트렌치 형성 방법
JP4407127B2 (ja) * 2003-01-10 2010-02-03 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US6989314B2 (en) * 2003-02-12 2006-01-24 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and method of making same
FR2851079B1 (fr) * 2003-02-12 2005-08-26 Soitec Silicon On Insulator Structure semi-conductrice sur substrat a forte rugosite
JP4631347B2 (ja) * 2004-08-06 2011-02-16 株式会社Ｓｕｍｃｏ 部分ｓｏｉ基板およびその製造方法
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.

Also Published As

Publication number Publication date
WO2008077796A1 (fr) 2008-07-03
JP2010515248A (ja) 2010-05-06
EP2102903A1 (fr) 2009-09-23
US7422958B2 (en) 2008-09-09
FR2910702A1 (fr) 2008-06-27
US20080153251A1 (en) 2008-06-26

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: COMMISSARIAT A L ENERGIE ATOMIQUE, FR

Effective date: 20120423

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20140829