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FR2773417B1 - Procede de formation d'un contact auto-aligne dans un dipositif a semiconducteur - Google Patents

Procede de formation d'un contact auto-aligne dans un dipositif a semiconducteur

Info

Publication number
FR2773417B1
FR2773417B1 FR9900017A FR9900017A FR2773417B1 FR 2773417 B1 FR2773417 B1 FR 2773417B1 FR 9900017 A FR9900017 A FR 9900017A FR 9900017 A FR9900017 A FR 9900017A FR 2773417 B1 FR2773417 B1 FR 2773417B1
Authority
FR
France
Prior art keywords
dipositive
semiconductor
self
forming
aligned contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9900017A
Other languages
English (en)
Other versions
FR2773417A1 (fr
Inventor
Hyun Cho Chang
Sik Jeong Hong
Goo Lee Jae
Jin Kang Chang
Sup Jeong Sang
Jung Chul
Ouk Jung Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2773417A1 publication Critical patent/FR2773417A1/fr
Application granted granted Critical
Publication of FR2773417B1 publication Critical patent/FR2773417B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
FR9900017A 1998-01-08 1999-01-05 Procede de formation d'un contact auto-aligne dans un dipositif a semiconducteur Expired - Fee Related FR2773417B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR19980000308 1998-01-08
KR19980000309 1998-01-08
KR1019980031537A KR100276387B1 (ko) 1998-01-08 1998-08-03 반도체 장치의 자기정렬 콘택 형성 방법

Publications (2)

Publication Number Publication Date
FR2773417A1 FR2773417A1 (fr) 1999-07-09
FR2773417B1 true FR2773417B1 (fr) 2004-12-31

Family

ID=34978890

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9900017A Expired - Fee Related FR2773417B1 (fr) 1998-01-08 1999-01-05 Procede de formation d'un contact auto-aligne dans un dipositif a semiconducteur

Country Status (9)

Country Link
US (1) US6177320B1 (fr)
JP (1) JP4040781B2 (fr)
KR (1) KR100276387B1 (fr)
CN (1) CN1157763C (fr)
DE (1) DE19860769C2 (fr)
FR (1) FR2773417B1 (fr)
GB (1) GB2333179B (fr)
NL (2) NL1010986C2 (fr)
TW (1) TW392304B (fr)

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KR100284535B1 (ko) 1998-06-17 2001-04-02 윤종용 반도체장치의자기정렬콘택형성방법
KR100308619B1 (ko) * 1999-08-24 2001-11-01 윤종용 반도체 장치용 자기 정렬 콘택 패드 형성 방법
KR100527577B1 (ko) * 1999-12-24 2005-11-09 주식회사 하이닉스반도체 반도체소자의 제조방법
KR100352909B1 (ko) * 2000-03-17 2002-09-16 삼성전자 주식회사 반도체소자의 자기정렬 콘택 구조체 형성방법 및 그에의해 형성된 자기정렬 콘택 구조체
KR100355236B1 (ko) 2000-09-21 2002-10-11 삼성전자 주식회사 자기 정렬된 컨택 형성 방법 및 이를 이용한 반도체소자의 제조 방법
FR2816110B1 (fr) * 2000-10-27 2003-03-21 St Microelectronics Sa Lignes de bit en memoire dram
KR100343148B1 (ko) * 2000-11-10 2002-07-06 윤종용 반도체 소자의 콘택패드 형성방법
US6410955B1 (en) * 2001-04-19 2002-06-25 Micron Technology, Inc. Comb-shaped capacitor for use in integrated circuits
US6723655B2 (en) 2001-06-29 2004-04-20 Hynix Semiconductor Inc. Methods for fabricating a semiconductor device
US6888217B2 (en) * 2001-08-30 2005-05-03 Micron Technology, Inc. Capacitor for use in an integrated circuit
KR20030058584A (ko) * 2001-12-31 2003-07-07 주식회사 하이닉스반도체 반도체소자의 콘택 형성방법
KR100431816B1 (ko) * 2002-06-29 2004-05-17 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR20040011016A (ko) * 2002-07-26 2004-02-05 동부전자 주식회사 알에프 반도체소자 제조방법
DE10250872B4 (de) 2002-10-31 2005-04-21 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit mehreren Gate-Stapeln
KR100465632B1 (ko) * 2002-12-21 2005-01-13 주식회사 하이닉스반도체 반도체 소자의 비트라인 형성방법
KR100632036B1 (ko) * 2002-12-30 2006-10-04 동부일렉트로닉스 주식회사 반도체 메모리 소자의 제조 방법
KR100607647B1 (ko) * 2003-03-14 2006-08-23 주식회사 하이닉스반도체 반도체소자의 제조 방법
KR20050002315A (ko) * 2003-06-30 2005-01-07 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100499175B1 (ko) * 2003-09-01 2005-07-01 삼성전자주식회사 반도체 장치 및 이의 제조 방법
JP4671614B2 (ja) * 2004-03-03 2011-04-20 パナソニック株式会社 半導体装置
KR100672780B1 (ko) * 2004-06-18 2007-01-22 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
KR100991381B1 (ko) * 2004-10-30 2010-11-02 주식회사 하이닉스반도체 리프레시 특성을 향상시킬 수 있는 반도체 소자
US7301185B2 (en) * 2004-11-29 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. High-voltage transistor device having an interlayer dielectric etch stop layer for preventing leakage and improving breakdown voltage
KR100673125B1 (ko) * 2005-04-15 2007-01-22 주식회사 하이닉스반도체 포토 마스크
JP4205734B2 (ja) * 2006-05-25 2009-01-07 エルピーダメモリ株式会社 半導体装置の製造方法
KR101186043B1 (ko) 2009-06-22 2012-09-25 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
KR102057067B1 (ko) * 2013-01-29 2019-12-18 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
US9123575B1 (en) * 2014-07-21 2015-09-01 Avalanche Technology, Inc. Semiconductor memory device having increased separation between memory elements
US9397049B1 (en) 2015-08-10 2016-07-19 International Business Machines Corporation Gate tie-down enablement with inner spacer
US9548448B1 (en) 2015-11-12 2017-01-17 Avalanche Technology, Inc. Memory device with increased separation between memory elements
US10818498B1 (en) 2019-05-09 2020-10-27 Globalfoundries Inc. Shaped gate caps in spacer-lined openings

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US4196443A (en) * 1978-08-25 1980-04-01 Rca Corporation Buried contact configuration for CMOS/SOS integrated circuits
US4999318A (en) * 1986-11-12 1991-03-12 Hitachi, Ltd. Method for forming metal layer interconnects using stepped via walls
DE3727142C2 (de) * 1987-08-14 1994-02-24 Kernforschungsz Karlsruhe Verfahren zur Herstellung von Mikrosensoren mit integrierter Signalverarbeitung
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US5258096A (en) * 1992-08-20 1993-11-02 Micron Semiconductor, Inc. Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths
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Also Published As

Publication number Publication date
FR2773417A1 (fr) 1999-07-09
GB2333179A (en) 1999-07-14
NL1025870A1 (nl) 2004-07-07
GB9825187D0 (en) 1999-01-13
GB2333179B (en) 2000-05-17
DE19860769C2 (de) 2002-11-14
NL1010986C2 (nl) 2004-04-08
JP4040781B2 (ja) 2008-01-30
KR19990066733A (ko) 1999-08-16
NL1010986A1 (nl) 1999-07-12
JPH11251557A (ja) 1999-09-17
DE19860769A1 (de) 1999-07-15
CN1222753A (zh) 1999-07-14
US6177320B1 (en) 2001-01-23
TW392304B (en) 2000-06-01
NL1025870C2 (nl) 2006-02-14
KR100276387B1 (ko) 2000-12-15
CN1157763C (zh) 2004-07-14

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20140930