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FR2763743B1 - Procede de fabrication d'un siliciure auto-aligne - Google Patents

Procede de fabrication d'un siliciure auto-aligne

Info

Publication number
FR2763743B1
FR2763743B1 FR9711068A FR9711068A FR2763743B1 FR 2763743 B1 FR2763743 B1 FR 2763743B1 FR 9711068 A FR9711068 A FR 9711068A FR 9711068 A FR9711068 A FR 9711068A FR 2763743 B1 FR2763743 B1 FR 2763743B1
Authority
FR
France
Prior art keywords
self
manufacturing
aligned silicide
silicide
aligned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9711068A
Other languages
English (en)
Other versions
FR2763743A1 (fr
Inventor
Tony Lin
Water Lur
Shih Wei Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW086107014A external-priority patent/TW345694B/zh
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of FR2763743A1 publication Critical patent/FR2763743A1/fr
Application granted granted Critical
Publication of FR2763743B1 publication Critical patent/FR2763743B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
FR9711068A 1997-05-24 1997-09-05 Procede de fabrication d'un siliciure auto-aligne Expired - Fee Related FR2763743B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW086107014A TW345694B (en) 1997-05-24 1997-05-24 Method of making a self-aligned silicide component
GB9716395A GB2328078B (en) 1997-05-24 1997-08-01 Method of making a self-aligned silicide
NL1006872A NL1006872C2 (nl) 1997-05-24 1997-08-28 Methode voor het maken van een zelfrichtende silicidelaag.

Publications (2)

Publication Number Publication Date
FR2763743A1 FR2763743A1 (fr) 1998-11-27
FR2763743B1 true FR2763743B1 (fr) 1999-07-23

Family

ID=27268962

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9711068A Expired - Fee Related FR2763743B1 (fr) 1997-05-24 1997-09-05 Procede de fabrication d'un siliciure auto-aligne

Country Status (6)

Country Link
US (1) US5913124A (fr)
JP (1) JP3041369B2 (fr)
DE (1) DE19734837B4 (fr)
FR (1) FR2763743B1 (fr)
GB (1) GB2328078B (fr)
NL (1) NL1006872C2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6187643B1 (en) * 1999-06-29 2001-02-13 Varian Semiconductor Equipment Associates, Inc. Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
US6509264B1 (en) 2000-03-30 2003-01-21 Chartered Semiconductor Manufacturing Ltd. Method to form self-aligned silicide with reduced sheet resistance
CN1868046B (zh) * 2003-10-17 2011-12-28 Nxp股份有限公司 半导体器件及制造此类半导体器件的方法
JP2005183458A (ja) * 2003-12-16 2005-07-07 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及びその製造装置
DE102004055083B4 (de) * 2004-11-15 2008-01-17 Trw Automotive Electronics & Components Gmbh & Co. Kg Schweißteil für das Verschweißen mittels einer Kehlnaht und elektrische Baueinheit
US7442619B2 (en) * 2006-05-18 2008-10-28 International Business Machines Corporation Method of forming substantially L-shaped silicide contact for a semiconductor device
US8338265B2 (en) * 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
US8664050B2 (en) * 2012-03-20 2014-03-04 International Business Machines Corporation Structure and method to improve ETSOI MOSFETS with back gate

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4512073A (en) * 1984-02-23 1985-04-23 Rca Corporation Method of forming self-aligned contact openings
US5612914A (en) * 1991-06-25 1997-03-18 Texas Instruments Incorporated Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
JPH05166798A (ja) * 1991-12-18 1993-07-02 Sony Corp 半導体装置の素子分離領域の形成方法
US5463237A (en) * 1993-11-04 1995-10-31 Victor Company Of Japan, Ltd. MOSFET device having depletion layer
EP0669656A3 (fr) * 1994-02-25 1996-02-28 Matsushita Electric Ind Co Ltd Source/drain de MISFET dans un dispositif semi-conducteur et méthode de fabrication.
US5576227A (en) * 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
US5759901A (en) * 1995-04-06 1998-06-02 Vlsi Technology, Inc. Fabrication method for sub-half micron CMOS transistor
US5508212A (en) * 1995-04-27 1996-04-16 Taiwan Semiconductor Manufacturing Co. Salicide process for a MOS semiconductor device using nitrogen implant of titanium
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry
US6281562B1 (en) * 1995-07-27 2001-08-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device which reduces the minimum distance requirements between active areas
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US5686324A (en) * 1996-03-28 1997-11-11 Mosel Vitelic, Inc. Process for forming LDD CMOS using large-tilt-angle ion implantation
KR100205320B1 (ko) * 1996-10-25 1999-07-01 구본준 모스펫 및 그 제조방법
US5793090A (en) * 1997-01-10 1998-08-11 Advanced Micro Devices, Inc. Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

Also Published As

Publication number Publication date
NL1006872C2 (nl) 1999-03-02
US5913124A (en) 1999-06-15
GB2328078B (en) 1999-07-14
GB9716395D0 (en) 1997-10-08
JP3041369B2 (ja) 2000-05-15
DE19734837A1 (de) 1998-11-26
DE19734837B4 (de) 2004-04-15
FR2763743A1 (fr) 1998-11-27
JPH10335662A (ja) 1998-12-18
GB2328078A (en) 1999-02-10

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20100531