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FR2718560B1 - Procédé et circuit pour réparer un défaut dans un dispositif de mémoire à semi-conducteur. - Google Patents

Procédé et circuit pour réparer un défaut dans un dispositif de mémoire à semi-conducteur.

Info

Publication number
FR2718560B1
FR2718560B1 FR9504239A FR9504239A FR2718560B1 FR 2718560 B1 FR2718560 B1 FR 2718560B1 FR 9504239 A FR9504239 A FR 9504239A FR 9504239 A FR9504239 A FR 9504239A FR 2718560 B1 FR2718560 B1 FR 2718560B1
Authority
FR
France
Prior art keywords
repairing
fault
circuit
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9504239A
Other languages
English (en)
Other versions
FR2718560A1 (fr
Inventor
Sung-Soo Lee
Jin-Ki Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2718560A1 publication Critical patent/FR2718560A1/fr
Application granted granted Critical
Publication of FR2718560B1 publication Critical patent/FR2718560B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
FR9504239A 1994-04-11 1995-04-10 Procédé et circuit pour réparer un défaut dans un dispositif de mémoire à semi-conducteur. Expired - Lifetime FR2718560B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940007549A KR0119888B1 (ko) 1994-04-11 1994-04-11 반도체 메모리장치의 결함구제방법 및 그 회로

Publications (2)

Publication Number Publication Date
FR2718560A1 FR2718560A1 (fr) 1995-10-13
FR2718560B1 true FR2718560B1 (fr) 1997-06-20

Family

ID=19380789

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9504239A Expired - Lifetime FR2718560B1 (fr) 1994-04-11 1995-04-10 Procédé et circuit pour réparer un défaut dans un dispositif de mémoire à semi-conducteur.

Country Status (7)

Country Link
US (1) US5548555A (fr)
JP (1) JP2777083B2 (fr)
KR (1) KR0119888B1 (fr)
CN (1) CN1037721C (fr)
DE (1) DE19513789C2 (fr)
FR (1) FR2718560B1 (fr)
IT (1) IT1273529B (fr)

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KR0157339B1 (ko) * 1995-06-28 1998-12-01 김광호 반도체 메모리의 불량셀 구제회로
US5748031A (en) * 1996-02-01 1998-05-05 Cypress Semiconductor, Corporation Electrical laser fuse hybrid cell
US5828624A (en) * 1996-12-23 1998-10-27 Cypress Semiconductor Corporation Decoder circuit and method for disabling a number of columns or rows in a memory
US5889679A (en) * 1997-07-15 1999-03-30 Integrated Device Technology, Inc. Fuse array control for smart function enable
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US5970013A (en) * 1998-02-26 1999-10-19 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus with broadcast write
US6011733A (en) * 1998-02-26 2000-01-04 Lucent Technologies Inc. Adaptive addressable circuit redundancy method and apparatus
JPH11339493A (ja) * 1998-05-27 1999-12-10 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4260247B2 (ja) * 1998-09-02 2009-04-30 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
JP3301398B2 (ja) * 1998-11-26 2002-07-15 日本電気株式会社 半導体記憶装置
US6407944B1 (en) 1998-12-29 2002-06-18 Samsung Electronics Co., Ltd. Method for protecting an over-erasure of redundant memory cells during test for high-density nonvolatile memory semiconductor devices
JP4950816B2 (ja) * 1999-06-03 2012-06-13 株式会社東芝 半導体メモリ
US6438672B1 (en) 1999-06-03 2002-08-20 Agere Systems Guardian Corp. Memory aliasing method and apparatus
US6288436B1 (en) * 1999-07-27 2001-09-11 International Business Machines Corporation Mixed fuse technologies
JP2001210092A (ja) * 2000-01-24 2001-08-03 Nec Corp 半導体記憶装置
KR100328447B1 (ko) * 2000-02-21 2002-03-16 박종섭 안티퓨즈 리페어 회로
KR100385950B1 (ko) * 2001-01-15 2003-06-02 삼성전자주식회사 자동 퓨징 회로
US7085971B2 (en) * 2001-10-25 2006-08-01 International Business Machines Corporation ECC based system and method for repairing failed memory elements
KR100462877B1 (ko) * 2002-02-04 2004-12-17 삼성전자주식회사 반도체 메모리 장치, 및 이 장치의 불량 셀 어드레스프로그램 회로 및 방법
US7055069B2 (en) * 2002-08-23 2006-05-30 Infineon Technologies Ag Spare input/output buffer
JP4175852B2 (ja) * 2002-09-13 2008-11-05 スパンション エルエルシー 冗長セルアレイへの置き換えを正常に行う半導体メモリ
US6819160B2 (en) * 2002-11-13 2004-11-16 International Business Machines Corporation Self-timed and self-tested fuse blow
US7405989B2 (en) * 2005-03-07 2008-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical fuses with redundancy
KR100739927B1 (ko) * 2005-06-29 2007-07-16 주식회사 하이닉스반도체 반도체 메모리 장치의 리페어 입출력 퓨즈 회로
JP4946260B2 (ja) 2006-08-16 2012-06-06 富士通セミコンダクター株式会社 アンチヒューズ書込電圧発生回路を内蔵する半導体メモリ装置
KR101373183B1 (ko) * 2008-01-15 2014-03-14 삼성전자주식회사 3차원 어레이 구조를 갖는 메모리 장치 및 그것의 리페어방법
KR101204665B1 (ko) * 2010-03-31 2012-11-26 에스케이하이닉스 주식회사 퓨즈회로
KR101750460B1 (ko) 2010-09-01 2017-06-23 삼성전자주식회사 리던던시 제어 회로 및 이를 포함하는 메모리 장치
JP5664204B2 (ja) * 2010-12-15 2015-02-04 富士通株式会社 半導体メモリ
US9202532B2 (en) 2012-09-13 2015-12-01 Winbond Electronics Corp. Burst sequence control and multi-valued fuse scheme in memory device
KR20150019442A (ko) * 2013-08-14 2015-02-25 삼성전자주식회사 퓨즈 셀들의 프로그래밍 방법 및 메모리 복구 방법
US9117534B2 (en) * 2014-01-23 2015-08-25 Freescale Semiconductor, Inc. Fuse circuit with test mode
KR101803721B1 (ko) 2016-09-05 2017-12-01 주식회사 에스앤에스티 개선된 전기적 퓨즈 구조
KR102416942B1 (ko) * 2017-11-13 2022-07-07 에스케이하이닉스 주식회사 적층 반도체 장치 및 반도체 시스템
KR20200101651A (ko) * 2019-02-20 2020-08-28 에스케이하이닉스 주식회사 메모리 및 메모리의 동작 방법
US11309057B2 (en) * 2020-04-28 2022-04-19 Micron Technology, Inc. Apparatuses and methods for post-package repair protection

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
WO1980002889A1 (fr) * 1979-06-15 1980-12-24 Fujitsu Ltd Dispositif de memoire a semiconducteur
US4358833A (en) * 1980-09-30 1982-11-09 Intel Corporation Memory redundancy apparatus for single chip memories
JPS59113595A (ja) * 1982-12-20 1984-06-30 Mitsubishi Electric Corp 冗長回路におけるプログラム回路装置
JPS59121699A (ja) * 1982-12-28 1984-07-13 Toshiba Corp 冗長性回路変更装置
US4577294A (en) * 1983-04-18 1986-03-18 Advanced Micro Devices, Inc. Redundant memory circuit and method of programming and verifying the circuit
KR910005601B1 (ko) * 1989-05-24 1991-07-31 삼성전자주식회사 리던던트 블럭을 가지는 반도체 메모리장치
JP2778234B2 (ja) * 1990-09-13 1998-07-23 日本電気株式会社 冗長デコーダ回路
KR970000501B1 (en) * 1991-04-12 1997-01-13 Hyundai Electronics Ind Semiconductor memory device with redundancy confirmative circuit
JPH05242693A (ja) * 1992-02-28 1993-09-21 Mitsubishi Electric Corp 半導体記憶装置
KR950000275B1 (ko) * 1992-05-06 1995-01-12 삼성전자 주식회사 반도체 메모리 장치의 컬럼 리던던시
JP3020077B2 (ja) * 1993-03-03 2000-03-15 株式会社日立製作所 半導体メモリ
US5422850A (en) * 1993-07-12 1995-06-06 Texas Instruments Incorporated Semiconductor memory device and defective memory cell repair circuit

Also Published As

Publication number Publication date
IT1273529B (it) 1997-07-08
CN1117193A (zh) 1996-02-21
KR0119888B1 (ko) 1997-10-30
DE19513789A1 (de) 1995-10-12
KR950030164A (ko) 1995-11-24
JPH07287992A (ja) 1995-10-31
CN1037721C (zh) 1998-03-11
FR2718560A1 (fr) 1995-10-13
JP2777083B2 (ja) 1998-07-16
US5548555A (en) 1996-08-20
ITMI950731A0 (it) 1995-04-07
DE19513789C2 (de) 2000-11-16
ITMI950731A1 (it) 1996-10-07

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