[go: up one dir, main page]

ES8702011A1 - Sistema de control de traslacion de direcciones - Google Patents

Sistema de control de traslacion de direcciones

Info

Publication number
ES8702011A1
ES8702011A1 ES539203A ES539203A ES8702011A1 ES 8702011 A1 ES8702011 A1 ES 8702011A1 ES 539203 A ES539203 A ES 539203A ES 539203 A ES539203 A ES 539203A ES 8702011 A1 ES8702011 A1 ES 8702011A1
Authority
ES
Spain
Prior art keywords
memory
purge
control system
record
address translation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES539203A
Other languages
English (en)
Other versions
ES539203A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES539203A0 publication Critical patent/ES539203A0/es
Publication of ES8702011A1 publication Critical patent/ES8702011A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Computer And Data Communications (AREA)

Abstract

SISTEMA DE CONTROL DE TRASLACION DE DIRECCIONES PARA UN PROCESO DE DATOS. COMPRENDE UNA MEMORIA INTERMEDIA PARA LA TRASLACION DE DIRECCIONES CON VARIAS ENTRADAS Y CON, AL MENOS, UN SEÑALIZADOR VALIDO, EL CAMPO DE DIRECCIONES, UN REGISTRO DE PURGA PARA LA MEMORIA INTERMEDIA, UN DISPOSITIVO COMPARADOR, QUE COMPARA EL CONTENIDO DEL REGISTRO DE PURGA CON EL DE LA MEMORIA INTERMEDIA DE TRASLACION DE DIRECCIONES. UN SEGUNDO COMPARADOR CONTRASTA EL REGISTRO DE PURGA CON EL CONTENIDO DE LA FORMACION DE LA MEMORIA. LA PURGA PARCIAL SE REALIZA INVALIDANDO LOS SEÑALIZADORES VALIDOS DE LAS ENTRADAS CORRESPONDIENTES DE LA MEMORIA INTERMEDIA DE TRASLACION DE DIRECCIONES Y LA FORMACION DE LA MEMORIA.
ES539203A 1983-12-29 1984-12-28 Sistema de control de traslacion de direcciones Expired ES8702011A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58246112A JPS60142451A (ja) 1983-12-29 1983-12-29 アドレス変換制御方式

Publications (2)

Publication Number Publication Date
ES539203A0 ES539203A0 (es) 1986-12-01
ES8702011A1 true ES8702011A1 (es) 1986-12-01

Family

ID=17143658

Family Applications (1)

Application Number Title Priority Date Filing Date
ES539203A Expired ES8702011A1 (es) 1983-12-29 1984-12-28 Sistema de control de traslacion de direcciones

Country Status (9)

Country Link
US (1) US4733350A (es)
EP (1) EP0149389B1 (es)
JP (1) JPS60142451A (es)
KR (1) KR890004994B1 (es)
AU (1) AU552060B2 (es)
BR (1) BR8406791A (es)
CA (1) CA1226372A (es)
DE (1) DE3480235D1 (es)
ES (1) ES8702011A1 (es)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6184753A (ja) * 1984-10-01 1986-04-30 Hitachi Ltd バツフアメモリ
JPS61190638A (ja) * 1985-02-20 1986-08-25 Hitachi Ltd 仮想計算機のフアイル制御方式
JPH0685156B2 (ja) * 1985-05-24 1994-10-26 株式会社日立製作所 アドレス変換装置
US5045996A (en) * 1986-11-12 1991-09-03 Xerox Corporation Multiprocessor cache memory housekeeping
US5123101A (en) * 1986-11-12 1992-06-16 Xerox Corporation Multiple address space mapping technique for shared memory wherein a processor operates a fault handling routine upon a translator miss
JPH077364B2 (ja) * 1987-07-24 1995-01-30 株式会社日立製作所 アドレス変換バッファ制御方式
JPH035851A (ja) * 1989-06-01 1991-01-11 Fujitsu Ltd バッファ記憶装置
JP2825550B2 (ja) * 1989-09-21 1998-11-18 株式会社日立製作所 多重仮想空間アドレス制御方法および計算機システム
JPH0512126A (ja) * 1991-07-05 1993-01-22 Hitachi Ltd 仮想計算機のアドレス変換装置及びアドレス変換方法
EP0600112A1 (de) * 1992-11-30 1994-06-08 Siemens Nixdorf Informationssysteme Aktiengesellschaft Datenverarbeitungsanlage mit virtueller Speicheradressierung und schlüsselgesteuertem Speicherzugriff
JP2842313B2 (ja) * 1995-07-13 1999-01-06 日本電気株式会社 情報処理装置
US6493343B1 (en) 1998-01-07 2002-12-10 Compaq Information Technologies Group System and method for implementing multi-pathing data transfers in a system area network
US6163834A (en) * 1998-01-07 2000-12-19 Tandem Computers Incorporated Two level address translation and memory registration system and method
US6545981B1 (en) 1998-01-07 2003-04-08 Compaq Computer Corporation System and method for implementing error detection and recovery in a system area network
US6647423B2 (en) * 1998-06-16 2003-11-11 Intel Corporation Direct message transfer between distributed processes
US6615337B1 (en) * 2001-08-09 2003-09-02 Advanced Micro Devices, Inc. Method and apparatus for maintaining coherency in a translation lookaside buffer
US7069413B1 (en) 2003-01-29 2006-06-27 Vmware, Inc. Method and system for performing virtual to physical address translations in a virtual machine monitor
US7617378B2 (en) * 2003-04-28 2009-11-10 International Business Machines Corporation Multiprocessor system with retry-less TLBI protocol
US8112174B2 (en) * 2008-02-25 2012-02-07 International Business Machines Corporation Processor, method and computer program product for fast selective invalidation of translation lookaside buffer
US10248573B2 (en) 2016-07-18 2019-04-02 International Business Machines Corporation Managing memory used to back address translation structures
US10168902B2 (en) 2016-07-18 2019-01-01 International Business Machines Corporation Reducing purging of structures associated with address translation
US10241924B2 (en) * 2016-07-18 2019-03-26 International Business Machines Corporation Reducing over-purging of structures associated with address translation using an array of tags
US10176006B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Delaying purging of structures associated with address translation
US10282305B2 (en) 2016-07-18 2019-05-07 International Business Machines Corporation Selective purging of entries of structures associated with address translation in a virtualized environment
US10802986B2 (en) 2016-07-18 2020-10-13 International Business Machines Corporation Marking to indicate memory used to back address translation structures
US10223281B2 (en) 2016-07-18 2019-03-05 International Business Machines Corporation Increasing the scope of local purges of structures associated with address translation
US10176110B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Marking storage keys to indicate memory used to back address translation structures
US10176111B2 (en) 2016-07-18 2019-01-08 International Business Machines Corporation Host page management using active guest page table indicators
US10180909B2 (en) 2016-07-18 2019-01-15 International Business Machines Corporation Host-based resetting of active use of guest page table indicators

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51115737A (en) * 1975-03-24 1976-10-12 Hitachi Ltd Adress conversion versus control system
FR2348544A1 (fr) * 1976-04-15 1977-11-10 Honeywell Bull Soc Ind Ensemble double de memoire associative
US4053948A (en) * 1976-06-21 1977-10-11 Ibm Corporation Look aside array invalidation mechanism
US4373179A (en) * 1978-06-26 1983-02-08 Fujitsu Limited Dynamic address translation system
US4376927A (en) * 1978-12-18 1983-03-15 Mcgalliard James D Printed circuit fuse assembly
JPS601658B2 (ja) * 1980-07-04 1985-01-16 富士通株式会社 アドレス変換制御方式
JPS5953634B2 (ja) * 1980-07-15 1984-12-26 富士通株式会社 計算機システム
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4456954A (en) * 1981-06-15 1984-06-26 International Business Machines Corporation Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations

Also Published As

Publication number Publication date
JPS6341100B2 (es) 1988-08-15
JPS60142451A (ja) 1985-07-27
KR890004994B1 (ko) 1989-12-04
ES539203A0 (es) 1986-12-01
AU3691984A (en) 1985-07-04
DE3480235D1 (en) 1989-11-23
EP0149389B1 (en) 1989-10-18
CA1226372A (en) 1987-09-01
EP0149389A2 (en) 1985-07-24
AU552060B2 (en) 1986-05-22
BR8406791A (pt) 1985-10-29
US4733350A (en) 1988-03-22
EP0149389A3 (en) 1987-05-20
KR850004677A (ko) 1985-07-25

Similar Documents

Publication Publication Date Title
ES8702011A1 (es) Sistema de control de traslacion de direcciones
DE3689357D1 (de) Digitaler Lese-/Schreibspeicher.
SE8102507L (sv) Databehandlingsanleggning
ATE205946T1 (de) Speicherverwaltung
BE852985A (fr) Systeme de traitement des donnees avec adressage des mots, des multiplets et des bits
FR2381356B1 (fr) Capacite de detection et de correction d'erreurs perfectionnee pour systeme de memoire
ES8305963A1 (es) "una disposicion de subsistema de almacenamiento de datos".
BR9705770A (pt) Sistema de exibição de imagens de diagnóstico ultra-sÈnico com capacidade de comunicações e acesso de dados.
IT8120743A0 (it) Circuito per la rivelazione di errori di scrittura in memoria.
KR960015237A (ko) 데이타 캐쉬 어레이 및 그를 이용한 데이타 캐슁 방법 및 데이타 처리 시스템
KR920016956A (ko) 직렬 버스를 기초로한 데이타 통신 시스템과 그 시스템과 함께 사용되는 모니터 시스템
DE3688400D1 (de) Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks.
KR910017286A (ko) 캐쉬 및 프리페치 버퍼를 갖는 데이타 처리 시스템 및 방법
DE3486054D1 (de) Fehlertolerante speicheranordnung.
IT8024912A0 (it) Sistema di sintonizzazione, del tipo a ricerca, dotato di un apparato per la selezione deicanali, ad indirizzo diretto.
NL7317545A (nl) Geheugensysteem met hoofd- en buffergeheugen.
GB1386227A (en) Memory arrangement for a computer
SE8106239L (sv) Vermevexlarvals
SE7904063L (sv) Databehandlingsanleggnig
KR840000642A (ko) 다환식 에테르계 항생물질의 제조방법
ES2056926T3 (es) Sistema de memoria cache.
JPS5211829A (en) Memory control unit
DE3382805D1 (de) Rechner mit dynamischem Aufbau eines Befehlzusatzfeldes zur Speicherung der folgenden Befehlsadresse.
GR3017394T3 (en) Procedure for testing of a smallest addressable unit of a RAM for bit errors exceeding a fixed number.
JPS5235947A (en) Information processing unit for imaginary memory system