DE3688400D1 - Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks. - Google Patents

Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks.

Info

Publication number: DE3688400D1
Authority: DE; Germany
Prior art keywords: transfer; processing; data block; cache memory; memory circuit
Prior art date: 1985-02-01
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE8686101357T

Other languages

English (en)

Other versions

DE3688400T2 (de

Inventor

Masatoshi Kofuji

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1985-02-01

Filing date

1986-02-03

Publication date

1993-06-17

1985-02-01 Priority claimed from JP60016401A external-priority patent/JPH0752410B2/ja

1985-04-01 Priority claimed from JP60066619A external-priority patent/JPH0644246B2/ja

1986-02-03 Application filed by NEC Corp filed Critical NEC Corp

1993-06-17 Application granted granted Critical

1993-06-17 Publication of DE3688400D1 publication Critical patent/DE3688400D1/de

1993-08-26 Publication of DE3688400T2 publication Critical patent/DE3688400T2/de

2006-02-04 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Memory System Of A Hierarchy Structure (AREA)

DE8686101357T 1985-02-01 1986-02-03 Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks. Expired - Lifetime DE3688400T2 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP60016401A JPH0752410B2 (ja)	1985-02-01	1985-02-01	キャッシュメモリ制御方式
JP60066619A JPH0644246B2 (ja)	1985-04-01	1985-04-01	キヤツシユメモリ制御方式

Publications (2)

Publication Number	Publication Date
DE3688400D1 true DE3688400D1 (de)	1993-06-17
DE3688400T2 DE3688400T2 (de)	1993-08-26

Family

ID=26352744

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8686101357T Expired - Lifetime DE3688400T2 (de)	1985-02-01	1986-02-03	Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks.

Country Status (3)

Country	Link
US (1)	US4835678A (de)
EP (1)	EP0189944B1 (de)
DE (1)	DE3688400T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CA1300759C (en) *	1987-02-07	1992-05-12	Kouji Kinoshita	Buffer memory circuit arrangement capable of receiving a requestwithout qualification during block transfer
US5276853A (en) *	1987-05-18	1994-01-04	Fujitsu Limited	Cache system
US5179678A (en) *	1987-09-08	1993-01-12	Nec Corporation	Address/control signal input circuit for a cache controller which clamps the address/control signals to predetermined logic level clamp signal is received
US5175826A (en) *	1988-05-26	1992-12-29	Ibm Corporation	Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385
US5202969A (en) *	1988-11-01	1993-04-13	Hitachi, Ltd.	Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
JPH0666056B2 (ja) *	1989-10-12	1994-08-24	甲府日本電気株式会社	情報処理システム
US5073851A (en) *	1990-02-21	1991-12-17	Apple Computer, Inc.	Apparatus and method for improved caching in a computer system
US5491811A (en) *	1992-04-20	1996-02-13	International Business Machines Corporation	Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory
US5539914A (en) *	1993-06-14	1996-07-23	International Business Machines Corporation	Method and system for preprocessing data block headers during access of data in a data storage system
US5627994A (en) *	1994-07-29	1997-05-06	International Business Machines Corporation	Method for the assignment of request streams to cache memories
JPH08314794A (ja) *	1995-02-28	1996-11-29	Matsushita Electric Ind Co Ltd	安定記憶装置へのアクセス待ち時間を短縮するための方法およびシステム
JP3641872B2 (ja)	1996-04-08	2005-04-27	株式会社日立製作所	記憶装置システム
KR0174711B1 (ko) *	1996-04-24	1999-04-15	김광호	하드디스크 캐시의 제어방법
US6092149A (en) *	1997-05-28	2000-07-18	Western Digital Corporation	Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses
US7159068B2 (en) *	2003-12-22	2007-01-02	Phison Electronics Corp.	Method of optimizing performance of a flash memory
JP2012533112A (ja) *	2009-07-07	2012-12-20	エルエスアイコーポレーション	階層不揮発性ストレージのためのシステムおよび方法
CN103631534B (zh) *	2013-11-12	2017-01-11	北京兆芯电子科技有限公司	数据存储系统以及其管理方法
JP6287571B2 (ja) *	2014-05-20	2018-03-07	富士通株式会社	演算処理装置、情報処理装置、及び、演算処理装置の制御方法
US10915447B1 (en) *	2018-01-30	2021-02-09	Johnny Yau	Systems, devices, and methods for reduced critical path latency and increased work parallelization in memory writes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3896419A (en) *	1974-01-17	1975-07-22	Honeywell Inf Systems	Cache memory store in a processor of a data processing system
US4169284A (en) *	1978-03-07	1979-09-25	International Business Machines Corporation	Cache control for concurrent access
US4381541A (en) *	1980-08-28	1983-04-26	Sperry Corporation	Buffer memory referencing system for two data words
JPS57105879A (en) *	1980-12-23	1982-07-01	Hitachi Ltd	Control system for storage device
US4439829A (en) *	1981-01-07	1984-03-27	Wang Laboratories, Inc.	Data processing machine with improved cache memory management
US4511960A (en) *	1982-01-15	1985-04-16	Honeywell Information Systems Inc.	Data processing system auto address development logic for multiword fetch

1986
- 1986-02-03 US US06/824,837 patent/US4835678A/en not_active Expired - Lifetime
- 1986-02-03 DE DE8686101357T patent/DE3688400T2/de not_active Expired - Lifetime
- 1986-02-03 EP EP86101357A patent/EP0189944B1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
DE3688400T2 (de)	1993-08-26
US4835678A (en)	1989-05-30
EP0189944B1 (de)	1993-05-12
EP0189944A2 (de)	1986-08-06
EP0189944A3 (en)	1989-09-06

Publication	Publication Date	Title
DE3688400D1 (de)	1993-06-17	Cachespeicherschaltung geeignet zur verarbeitung einer leseanforderung waehrend der uebertragung eines datenblocks.
DE3850901D1 (de)	1994-09-08	Datenverarbeitungsanordnung mit Mitteln zur angrenzenden Adressierung eines Speichers.
DE3484170D1 (de)	1991-04-04	System zum austausch von informationen mit elektronischen etiketten.
DE3689519D1 (de)	1994-02-17	Hierarchisches datenverarbeitungssystem.
DE3862594D1 (de)	1991-06-06	Sichere datenaustauschsysteme.
DE3689574D1 (de)	1994-03-10	System zum Feststellen der Echtheit von Software in einer Informationsverarbeitungsanlage.
DE3580778D1 (de)	1991-01-17	Datenverarbeitungsvorrichtung.
DE58908975D1 (de)	1995-03-16	Zweiwege-Datenübergabe-Einrichtung.
DE3484328D1 (de)	1991-05-02	Datenverarbeitungssystem mit zwei prozessoren.
KR850006738A (ko)	1985-10-16	데이타 처리 시스템
DE3484400D1 (de)	1991-05-16	Datenuebertragungssysteme.
DE3587375D1 (de)	1993-07-08	Schaltung zur zwischenspeicherung von bilddaten.
DE3889550D1 (de)	1994-06-23	Datenübertragungspufferschaltungen für Datenaustausch.
DE3484679D1 (de)	1991-07-11	Datenverarbeitungsgeraet fuer die verarbeitung von operandenspeicherungskonflikten.
FR2617621B1 (fr)	1989-12-01	Memoire de transposition pour circuit de traitement de donnees
ATA320282A (de)	1989-07-15	Datenuebertragungseinrichtung
DK155061C (da)	1989-07-03	Elektrofotografisk informationsskriver
NO167831C (no)	1991-12-11	Hierarkistyring for databehandlingssystem.
DK73683D0 (da)	1983-02-21	Dataoverfoeringsanlaeg
SE8203553L (sv)	1982-12-10	Informationsminnesanordning
DE69022402D1 (de)	1995-10-19	System zur integrität der speicherdaten.
DE3280423D1 (de)	1993-02-04	Datenuebertragungssystem.
DE3482997D1 (de)	1990-09-20	Vorrichtung zur computerspeicherzugriffssteuerung.
FR2610134B1 (fr)	1989-03-31	Circuit de lecture pour memoire
DE3854181D1 (de)	1995-08-24	System zur datenübertragung.