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ES483975A1 - Un proceso para fabricar tarjetas de circuito impreso multi-capas - Google Patents

Un proceso para fabricar tarjetas de circuito impreso multi-capas

Info

Publication number
ES483975A1
ES483975A1 ES483975A ES483975A ES483975A1 ES 483975 A1 ES483975 A1 ES 483975A1 ES 483975 A ES483975 A ES 483975A ES 483975 A ES483975 A ES 483975A ES 483975 A1 ES483975 A1 ES 483975A1
Authority
ES
Spain
Prior art keywords
printed circuit
multilayer printed
processed
circuit board
known manner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES483975A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES483975A1 publication Critical patent/ES483975A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Un proceso para fabricar tarjetas de circuito impreso multicapas que comprenden dos o más planos de interconexión e interconexiones entre las conexiones de diferentes planos de interconexión en dónde, en primer lugar, las interconexiones del primero o de los dos primeros planos se realizan sobre la superficie de un material base, después de lo cual el o los planos así equipados son interconexiones, se cubren con una capa de material aislante, produciéndose los conductores impresos a la distribución de interconexión deseada de los planos siguientes, produciéndose simultáneamente tanto los conductores impresos como las interconexiones entre los conductores impresos, caracterizado porque las interconexiones de los dos primeros (internas) planos de interconexión en sandwich se realizan atacando al aguafuerte un material base recubierto de cobre, después de lo cual estos planos de interconexión se recubren en todas sus superficies con una capa de material aislante, y se realizan los taladros, produciéndose entonces las interconexiones de los otros planos de interconexión utilizando el denominado método semi-aditivo.
ES483975A 1978-09-07 1979-09-07 Un proceso para fabricar tarjetas de circuito impreso multi-capas Expired ES483975A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782838982 DE2838982B2 (de) 1978-09-07 1978-09-07 Verfahren zum Herstellen von Mehrebenen-Leiterplatten

Publications (1)

Publication Number Publication Date
ES483975A1 true ES483975A1 (es) 1980-04-01

Family

ID=6048893

Family Applications (1)

Application Number Title Priority Date Filing Date
ES483975A Expired ES483975A1 (es) 1978-09-07 1979-09-07 Un proceso para fabricar tarjetas de circuito impreso multi-capas

Country Status (7)

Country Link
BE (1) BE878645A (es)
DE (1) DE2838982B2 (es)
ES (1) ES483975A1 (es)
FR (1) FR2447131A1 (es)
GB (1) GB2030781B (es)
NL (1) NL7906603A (es)
SE (1) SE7907298L (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816070A (en) * 1985-08-29 1989-03-28 Techo Instruments Investments Ltd. Use of immersion tin and alloys as a bonding medium for multilayer circuits
US4715894A (en) * 1985-08-29 1987-12-29 Techno Instruments Investments 1983 Ltd. Use of immersion tin and tin alloys as a bonding medium for multilayer circuits
JPS6276600A (ja) * 1985-09-29 1987-04-08 株式会社　アサヒ化学研究所 基板に導電回路を形成する方法
SE455148B (sv) * 1985-11-15 1988-06-20 Leeb Karl Erik Anordning innefattande ett substrat och derpa applicerat ledningsmonster vid framstellning av monsterkort samt forfarande for framstellning av anordningen
GB8630392D0 (en) * 1986-12-19 1987-01-28 Prestwick Circuits Ltd Producing printed circuit boards
US4804575A (en) * 1987-01-14 1989-02-14 Kollmorgen Corporation Multilayer printed wiring boards
JPH03196691A (ja) * 1989-12-26 1991-08-28 Cmk Corp プリント配線板の絶縁層の形成方法
DE4237611A1 (de) * 1992-11-09 1994-05-11 Lueberg Elektronik Gmbh & Co R Verfahren zur Herstellung von Leiterplatten

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB892451A (en) * 1957-12-03 1962-03-28 Radio And Allied Ind Ltd Improvements in and relating to the manufacture of printed circuits
US3349162A (en) * 1965-08-23 1967-10-24 Automatic Elect Lab Intra-connection techniques for multilayer printed wiring boards
DE1924775B2 (de) * 1969-05-14 1971-06-09 Verfahren zur herstellung einer leiterplatte
GB1310880A (en) * 1969-06-13 1973-03-21 Microponent Dev Ltd Multi-layer printed circuit board assemblies

Also Published As

Publication number Publication date
NL7906603A (nl) 1980-03-11
GB2030781B (en) 1982-10-13
SE7907298L (sv) 1980-03-08
FR2447131A1 (fr) 1980-08-14
DE2838982A1 (de) 1980-03-20
DE2838982B2 (de) 1980-09-18
BE878645A (nl) 1980-03-07
GB2030781A (en) 1980-04-10

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