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ES402719A1 - Perfeccionamientos introducidos en los transistores desti- nados a montarse por el metodo de inversion de la pastilla sobre zonas terminales incluidas en un sustrato de un cir- cuito microelectronico hibrido. - Google Patents

Perfeccionamientos introducidos en los transistores desti- nados a montarse por el metodo de inversion de la pastilla sobre zonas terminales incluidas en un sustrato de un cir- cuito microelectronico hibrido.

Info

Publication number
ES402719A1
ES402719A1 ES402719A ES402719A ES402719A1 ES 402719 A1 ES402719 A1 ES 402719A1 ES 402719 A ES402719 A ES 402719A ES 402719 A ES402719 A ES 402719A ES 402719 A1 ES402719 A1 ES 402719A1
Authority
ES
Spain
Prior art keywords
metallic
layer
openings
insulating material
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES402719A
Other languages
English (en)
Spanish (es)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of ES402719A1 publication Critical patent/ES402719A1/es
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
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    • H01L2224/05001Internal layers
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    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
ES402719A 1971-05-20 1972-05-13 Perfeccionamientos introducidos en los transistores desti- nados a montarse por el metodo de inversion de la pastilla sobre zonas terminales incluidas en un sustrato de un cir- cuito microelectronico hibrido. Expired ES402719A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14540671A 1971-05-20 1971-05-20

Publications (1)

Publication Number Publication Date
ES402719A1 true ES402719A1 (es) 1975-12-01

Family

ID=22512964

Family Applications (1)

Application Number Title Priority Date Filing Date
ES402719A Expired ES402719A1 (es) 1971-05-20 1972-05-13 Perfeccionamientos introducidos en los transistores desti- nados a montarse por el metodo de inversion de la pastilla sobre zonas terminales incluidas en un sustrato de un cir- cuito microelectronico hibrido.

Country Status (8)

Country Link
AU (1) AU4236672A (fr)
BE (1) BE783729A (fr)
DE (1) DE2224334A1 (fr)
ES (1) ES402719A1 (fr)
FR (1) FR2138731A1 (fr)
GB (1) GB1374867A (fr)
IT (1) IT955650B (fr)
NL (1) NL7206816A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114256215A (zh) * 2021-12-29 2022-03-29 广东晶科电子股份有限公司 一种照明器件及其制备方法

Also Published As

Publication number Publication date
BE783729A (fr) 1972-09-18
NL7206816A (fr) 1972-11-22
GB1374867A (en) 1974-11-20
DE2224334A1 (de) 1972-11-30
AU4236672A (en) 1973-11-22
FR2138731A1 (fr) 1973-01-05
IT955650B (it) 1973-09-29

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