[go: up one dir, main page]

EP3079142A1 - Bildanzeigeverfahren auf matrix-bildschirm - Google Patents

Bildanzeigeverfahren auf matrix-bildschirm Download PDF

Info

Publication number
EP3079142A1
EP3079142A1 EP16164462.0A EP16164462A EP3079142A1 EP 3079142 A1 EP3079142 A1 EP 3079142A1 EP 16164462 A EP16164462 A EP 16164462A EP 3079142 A1 EP3079142 A1 EP 3079142A1
Authority
EP
European Patent Office
Prior art keywords
lines
bit
memory
period
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP16164462.0A
Other languages
English (en)
French (fr)
Other versions
EP3079142B1 (de
Inventor
Josep Segura Puchades
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP3079142A1 publication Critical patent/EP3079142A1/de
Application granted granted Critical
Publication of EP3079142B1 publication Critical patent/EP3079142B1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the invention relates to a method for displaying images on an active matrix screen.
  • This type of screen has largely developed in recent years especially for liquid crystal type screens known by their abbreviation Anglo-Saxon: LCD. More recently other types of screens using light emitting diodes have been developed, including using organic diodes or micro diodes, known by their abbreviation Anglo-Saxon: OLED, respectively ⁇ LED.
  • Each of the pixels of an active matrix screen contains at least one transistor which acts as a switch connected to a storage component which makes it possible to store a useful signal during the duration of a frame. In the case of a liquid crystal display, these two elements are sufficient to excite the crystal. In the case of a diode screen, each pixel contains a second transistor which makes it possible to drive the supply of the light-emitting diode according to the useful signal stored in the storage component.
  • each pixel receives, via its transistor, a voltage representative of the brightness that the pixel must display.
  • This voltage is stored in the storage component, for example a capacitor.
  • the voltage is directly applied to the electrodes surrounding the liquid crystal.
  • the voltage is applied to the second transistor configured as a follower to supply the diode proportionally to the stored voltage.
  • Voltage leakage at the capacitor may occur during the frame time. This results in a phenomenon of flicker (known in the English literature as “flickering") which is amplified under the influence of temperature during the duration of the frame.
  • the voltages pass through conductors of the matrix, generally column conductors.
  • the voltage variations occurring on the column conductors can disturb the pixels of the other unaddressed lines, by capacitive coupling between the column conductors and the unaddressed storage capacitors. This results in artifacts in the displayed image.
  • the light-emitting diodes may require a high bias voltage.
  • the entire pixel must be compatible with this voltage.
  • the voltage stored in the capacitor must then be equal to the bias voltage of the diode to which the gate-source voltage of the second transistor is added.
  • Current CMOS technologies being limited to about 5V, the voltage applied to the light emitting diode is then capped at less than 4V, which can represent a limitation of the achievable performances in the brightness of the screen.
  • the diode power follower transistors may have non-uniform characteristics which causes a spatial noise phenomenon in the display, because for the same control voltage for distinct pixels, the polarization of the diode can then vary from one pixel to another.
  • the follower transistor operates in saturated mode and must absorb a voltage difference inversely proportional to the illumination of the light emitting diode.
  • the power dissipated in this transistor causes significant heating, which can cause problems of heat dissipation, especially when the transistor is implanted in an inner layer of the screen.
  • the control of the diodes of each of the pixels is ensured, for the digital control, in all or nothing that is to say, the diode is either connected to its maximum tension, thus lit, or disconnected, so off.
  • the control of the brightness of the diode is achieved by modulating the width of the pulse applied between its terminals.
  • the visual perception, because of the inertia of the eye, is the average of the sum of all the lighting times of the diode.
  • the command is binary. It applies two possible levels of voltage to the gate of the second transistor, which operates in switch mode. The amplitude between these two levels must be sufficient to block or not the second transistor, which can be achieved with relatively low voltage values.
  • the main disadvantage of digital control is the high frequency of operation of the matrix. Indeed, to modulate the pulse width on the light emitting diode of each pixel, it is necessary to address each pixel and therefore each line several times per frame.
  • the brightness of a pixel is encoded as a binary word.
  • Each bit of the binary word drives the diode for a duration proportional to the weight of the bit.
  • the electroluminescent diode is driven for a time proportional to the weight of the bit of the value to be displayed.
  • the most significant bit drives the diode half the duration of the frame (for example 10ms for a frequency of 50 frames / second).
  • the next bit represents one quarter of this duration, and so on until the least significant bit (LSB).
  • the diode is lit when the value of a bit is 1 and is off when the value of a bit is 0.
  • the opposite convention is of course possible.
  • the frequency F pix to be written in each of the pixels of a line is the frequency F line multiplied by the number of pixels per line which corresponds to the number of columns N col of the matrix:
  • F pix F line * NOT collar
  • the frequency F pix is then greater than 15GHz and for a format of 1920 columns by 1200 lines, Format known as WUXGA, always for coding on 10 bits, the frequency F pix then 118GHz.
  • the invention aims to overcome all or part of the problems mentioned above by providing a digital control method for reducing the pixel addressing frequency.
  • i represents a line pointer that increments each write and the complete sequence of writes is performed after 2 P -1 writing periods.
  • the writes made on lines i + 2 j occupy a period T i .
  • the 2 P -1 periods T i have equal durations.
  • the duration of a period T i is equal to the duration of an image frame divided by 2 P -1.
  • each of the pixels further comprises a switch for controlling the display component according to a state of the bit written in the memory.
  • the switch is actuated to control the display component according to the bit written in the memory for a duration extending between two successive writes.
  • the method may further consist, for each of the pixels, in activating the display component after writing in the corresponding memory.
  • the writes on the lines i + 2 j made from the current line i are made during a period.
  • the display component is activated for a period of time extending from the end of the period during which the brightness has been written until the end of the next period during which a new writing is performed in the pixel concerned.
  • each pixel is called the first memory.
  • Each pixel advantageously comprises a second binary memory for passing the bit written in the first memory to the display component to activate it.
  • the addressing means controls the first memory by means of a first signal for writing and controls the second memory by means of a second signal distinct from the first signal and enabling the activation of the display component.
  • the matrix is divided into separately piloted zones, each of the zones having a number of lines less than or equal to 2 S -1.
  • the binary word contains only value bits corresponding to an extinction of the display component.
  • the figure 1 represents a matrix screen 10 comprising a display zone 11 formed of pixels 12 organized in rows and columns, a line addressing circuit 13 and a horizontal register 14. Each pixel 12 illuminates according to a brightness datum expressed in the form of a binary word.
  • the line addressing circuit 13 selects the rows of the matrix one by one and for each pixel 12 of a selected line, the binary word stored in the horizontal register 14 and representing the brightness is transferred bit by bit to the pixel 12 corresponding.
  • the Figures 2a, 2b and 2c represent three examples of pixel schemes 12 that can be implemented in the screen of the figure 1 . These three examples of pixels can be implemented in a monochrome or color screen. For a color screen, we sometimes use the term "color pixel" which is actually formed by juxtaposition of several pixels each associated with a color filter. Each group of pixels receives separate brightness controls for each of the colors.
  • the method of the invention is illustrated from pixels implemented in a monochrome screen and can be transposed to the control of a color screen by replicating the control of each of the elementary pixels forming the color pixel.
  • the figure 2a schematically represents the main components of a liquid crystal pixel 12a.
  • the pixel 12a comprises a switch 20, a storage capacitor 21 and a liquid crystal cell 22.
  • the pixel 12a is connected to a column conductor 23 conveying the brightness data coming from the horizontal register 14.
  • the switch 20, for example formed by a transistor, makes it possible to transfer the brightness data of the column conductor 23 to the capacitor 21.
  • the pixel 12a is also connected to a line conductor 24 connected to the line addressing circuit 13.
  • the switch 20 is controlled by the line conductor 24.
  • the data stored in the capacitor 21 forms a voltage directly applied to one of the electrodes of the cell 22.
  • the data stored in the capacitor 21 is binary. One of the binary states makes the cell 22 transparent and the other state makes the cell 22 opaque. In the case of a backlit screen, the cell 22 thus lets the light pass according to the binary state of the data stored in the capacitor 21.
  • the cell operates in all or nothing according to the binary state of the cell. the data stored
  • the figure 2b schematically represents the main components of a light emitting diode pixel 12b.
  • the switch 20 In the pixel 12b there is the switch 20 and the storage capacitor 21, both of which are connected to the conductors 23 and 24.
  • the pixel 12b In place of the cell 22, the pixel 12b comprises a light-emitting diode 25 and a second switch 26 making it possible to supplying the diode 25 by means of a supply voltage V DD .
  • the switch 26 can also be a transistor. The switch 26 is driven by the data stored in the capacitor 21.
  • the Figure 2c represents a pixel 12c forming a variant of the pixel 12b.
  • the capacitor 21 is replaced by a binary memory 27.
  • This memory makes it possible to store binary information.
  • the binary memory can be formed by a flip-flop connected to its input to the column conductor 23 and to its output to the control terminal of the switch 26.
  • the memory 27 is controlled by the line conductor 24. The modification of FIG. information stored in the memory 27 occurs during an order conveyed on the line conductor 24.
  • Such a memory can also be implemented for a liquid crystal pixel instead of the capacitor 21 of the pixel 12a.
  • the implementation of a memory may be advantageous for a matrix comprising pixels made using a CMOS technology.
  • the switches 20 and 26 as well as the memory 27 then all use the same technology.
  • the term memory will be used for a capacitor as well as any other component or block component for storing a binary information.
  • the capacitor 21 is assimilated to a memory.
  • the invention can be implemented for any type of pixel for emitting light, such as those comprising a light emitting diode, to control the light passing through it such as those comprising a liquid crystal cell or to control the reflection of light. as those implemented in a screen or projector based on micro-mirrors. Subsequently the component of the pixel for emitting or controlling the light will be called the display component.
  • the brightness control of a pixel is done by means of a binary word representing a fraction of the maximum brightness of the pixel.
  • each pixel is assigned a brightness value encoded as a binary word.
  • the different bits of the binary word are written in the pixel memory and used by the display component operating in all or nothing for a fraction of the duration of the image. This fraction of duration is a function of the weight of the bit in the binary word.
  • the most significant bit is used by the display component for substantially half the duration of an image, the next bit for one quarter of the image duration, and so on, dividing the fraction by two until 'to the least significant bit.
  • the screen 10 allows for example to display 50 images per second.
  • the retinal persistence of a user makes it possible to average these fractions of duration to reconstitute the average brightness of the pixel.
  • the method of the invention consists in writing line by line the different bits of the binary words in the different memories of the corresponding pixels so as to reduce the writing frequency necessary to scan the entire matrix.
  • the invention is concerned with the sequence of writing periods in the different pixels of the matrix.
  • each current line i the writes made on lines i + 2 j occupy a period T i .
  • each repetition occupies a period T i .
  • 2 P -1 periods T i follow one another.
  • the different periods have the same duration. This makes it possible to respect the agreement on a frame between the value of the binary word and the sum of the activation durations of the display component.
  • the different periods occupy the entire frame.
  • the duration of a period T i is equal to the duration (T frame ) of an image frame divided by 2 P -1.
  • the figure 3 represents visually on a frame the usable durations for each of the bits of the binary word coding the brightness of each of the pixels.
  • Each row of the matrix being scanned during a frame the durations between each rewrite can be expressed in number of lines representing fractions of the total duration of the frame.
  • On the figure 3 half of the rows of the matrix contain MSB bits, one quarter of the lines contain MSB-1 bits, the eighth of the lines contains MSB-2 bits, and so on up to one line, the lowest line on the figure 3 , containing low-order bits.
  • the frequency is lowered in a ratio close to: N line / P.
  • the Figures 4a to 4p represent an example of a sequence of writing periods in the memories of the different pixels of the matrix. More precisely, in the example illustrated with the Figures 4a to 4p , the brightness is coded on 4 bits. It is understood that the brightness can be encoded on a larger (or smaller) number of bits. In order for a user to see practically no difference in brightness between two successive levels of coding the brightness of a pixel, an 8 to 10-bit coding may be appropriate.
  • the binary words coding the brightness comprise bits identified D0, D1, D2 and D3, ordered from the low-order bit D0 also called LSB for its abbreviation: "Low Significant Bit” to the most significant bit D3 also called MSB for its abbreviation Anglo-Saxon: "Most Significant Bit”.
  • the most significant bit D3 is written on the first line of the matrix
  • the bit of Low D0 is written on the second line
  • the D1 bit is written on the fourth line of the matrix
  • the D2 bit is written on the eighth row of the matrix.
  • a single bit can be written simultaneously.
  • Periods 3 to 15 are then sequenced in the same way by shifting the current line to each period of a line.
  • bit D2 is written on the eighth line.
  • the offsets made for the ninth period are rotational, that is, the offsets are incremented by one unit modulo the row number of the matrix. In other words, it is considered that the fifteenth row of the matrix is followed by the first line and in the ninth period the D2 bit is written on the first line of the matrix.
  • the current line is line 14.
  • all lines of the matrix were written with all the bits of the binary words representing the brightness of the different pixels of the matrix.
  • the figure 4p represents a period 16 for a new image or frame. This period 16 is similar to period 1 with new values of the binary words corresponding to the new image.
  • the figure 5 represents an example of a shift register that can be used in line addressing circuit 13 for generating the selection signals of lines Li, signals carried on line conductors 24.
  • the signal Li is formed using P flip-flops D: Di-1 to Di-P connected in series.
  • the output of the flip-flop Di-P forms the signal Li of the line i and is connected to the input of the flip-flop Di + 1-1.
  • a clock signal CLK is common to all flip-flops D. J chips are introduced at the input of the flip-flop D1-1 with a time difference of 2 j times the duration of a period.
  • This embodiment of the line addressing circuit 13 has a disadvantage due to the large number of latches that must switch simultaneously. This implies significant and significant consumption peaks. The size of the surface of this type of register is also penalizing.
  • the figure 6 represents an alternative for realizing the line addressing circuit 13. This alternative is more compact and less energy consuming.
  • the counter 34 receives a clock CLK operating at the frequency of each period.
  • the shift register 33 receives a clock P times faster than the clock of the counter 34 and a startup token Start at the beginning of each period.
  • the shift register 33 shifts the start signal at the rate of its clock, which makes it possible to transmit to the adder 32 a binary number equal to 2 P.
  • the adder 32 also receives the output of the counter 34.
  • the adder 32 performs the addition of the binary number and the output of the counter 34.
  • the result of the addition is transmitted to the decoder P to N, here a decoder 4 to 16 of which only 15 outputs are connected, each to a line conductor 24 of the matrix 11.
  • the lines of rank 2 j + k are successively addressed, k represents an integer incremented by one unit by the counter 34 to each new period.
  • the figure 7 represents an exemplary embodiment of the horizontal register 14 which comprises two shift registers 41 and 42 having as many bits as rows in the matrix.
  • the register 41 is used as a buffer for recording the brightness data.
  • the register 42 is used for the sequential writing of the lines addressed by the line addressing circuit 13.
  • the figures 8a and 8b represent in chronogram form the writing periods described above. These timing diagrams can be easily implemented using the line addressing circuits described on the figures 5 and 6 .
  • the figures 8a and 8b allow to illustrate a first embodiment of succession of different writings within periods.
  • a regular CLK clock allows to clock the various writings of the different periods.
  • the clock CLK are represented, line by line, the writes of the different bits of the words representing the brightness of the different pixels.
  • bit D3 of the first line is written.
  • bit D0 of the second line is written.
  • bit D1 of the fourth line is written and at the fourth top t 4 , the bit D2 of the eighth line is written.
  • This first embodiment has the advantage of a regular clock and a write in the order of the weight of the bits. Nevertheless, the duration for each bit is not exactly a multiple of the duration of a period because of the division of the period into four phases.
  • the low order bit D0 may be used by the display component for a duration of 3 ⁇ 4 of period and the bit D1 for 1 + 3 ⁇ 4 of period.
  • This quantization error is due to the choice of the sequence of the different bits. This error may be acceptable for encoding binary words over a larger number of bits.
  • the figure 9 represents a timing diagram of a second embodiment of the sequence of writes for reducing the previously described error.
  • the first periods are represented on this figure.
  • the bit D0 of the second line is written.
  • the bit D3 of the first line is written.
  • the bit D2 of the sixth line is written and at the fourth top t 4 , the bit D1 of the eighth line is written.
  • the low-order bit D0 may be used by the display component for a duration of 1 + 1 ⁇ 4 period, the D1 bit for 1 + 3 ⁇ 4 period, the D2 bit for 3 + 1 ⁇ 2 period , bit D3 during 8 + 1 ⁇ 4 period.
  • the error on the duration remains this time less than half the expected duration for the low-order bit D0.
  • This error is typically of the same order of magnitude as that of a digital-to-analog converter often used in a horizontal register implemented in an analog control. It is possible to empirically test different timing of the brightness bits in order to minimize the quantization error.
  • the figure 10 represents a timing diagram of a third embodiment of the sequence of writes also making it possible to reduce the error on the duration of use of the different bits.
  • the four phases of a period are generated this time for a period less than that of the period whose duration is equal to the duration of an image frame divided by the number of written lines 2 P -1.
  • the four phases are for example generated during half of the period. This is achieved by doubling the clock frequency.
  • the error is then divided by two.
  • the figure 11 a represents a pixel 12d making it possible to implement this activation duration offset with respect to the writing.
  • the switch 20 the storage capacitor 21, both connected to the conductors 23 and 24, the light emitting diode 25 and the switch 26 for supplying the diode 25 by means of of the supply voltage V DD.
  • the capacitor 21 does not directly control the switch 26.
  • a new switch 41 is interposed between the capacitor 21 and the control gate of the switch 26.
  • the switch 41 is controlled by a specific signal carried on an additional line conductor 42 separate from the conductor 24.
  • a parasitic capacitance 43 has at the common point switches 26 and 41 serves as a second memory driven by the specific signal. If necessary, it is of course possible to add a capacitor in addition to the parasitic capacitance.
  • the specific signal makes it possible to pass the charges stored in the capacitor 21 to the parasitic capacitance 43 at the desired moment.
  • the figure 11b represents a pixel 12e forming an alternative to the pixel 12d also making it possible to implement the shift of the activation time with respect to the writing.
  • the bit memory 27 receiving information to be stored by the column conductor 23 and driven by the line driver 24.
  • the bit memory 27 does not directly control the switch 26.
  • a second bit memory 45 is interposed between the bit memory 27 and the gate of the control of the switch 26. The memory 45 is driven by the signal specific on the additional line conductor 42.
  • the figure 12 represents in chronogram form the signals conveyed on line conductors 24 and 42. As previously on the figures 8 , 9 and 10 the time axis carries the different writing periods of the matrix. To simplify understanding, a 4-bit brightness resolution has been retained. The chronogram of the figure 12 resumes the natural scheduling of the writing of the different bits of brightness, scheduling presented on the figures 8a and 8b . For each of the 15 lines of the matrix, two signals S1 and S2 are represented, the signal S1 conveyed by the conductor 24 and the signal S2 by the conductor 42. The signals S1 conveyed by the different conductors 24 are identical to those described in FIG. help from figure 8a .
  • the bit D3 of the first line is written.
  • This bit is conveyed by the column conductor 23 and the top t 1 forms the signal S1 conveyed by the driver 24 of the first line.
  • the signal S2 conveyed by the conductor 42 a rising edge allows the contents of the memory 27, or the voltage present in the capacitor 21, to control the switch 26.
  • the on or off state of the switch 26 is maintained as long as a new rising edge does not appear on the conductor 42.
  • a falling edge appears on the signal S2 at the beginning of the first period shortly before the appearance of the bit D3 at the top t 1 .
  • the bit D0 is written at the top t 2 of the first period and the bit D3 is written at the top t 1 of the second period.
  • a first rising edge occurs at the end of the first period allowing the activation of the diode 25 by the value of the bit D0.
  • a second rising edge occurs at the end of the second period allowing the activation of the diode 25 by the value of the bit D3.
  • the diode has been activated by the D0 bit for exactly one period.
  • the signals S1 and S2 of the third line are temporally offset by one period with respect to the signals of the second line.
  • the D1 bit is written in the top t 3 of the first period and the bit D0 is written at the top t 2 of the third period.
  • a first rising edge intervenes at the end of the first period allowing the activation of the diode 25 by the value of the bit D1.
  • a second rising edge occurs at the end of the third period allowing the activation of the diode 25 by the value of the bit D3.
  • the diode 25 has been activated by the bit D1 during exactly two periods separating the two rising edges intervening at the end of the first period and at the end of the third period. And so on for the different bits D0 which activate the diode 25 during a period, the bits D1 during two periods, the bits D2 during four periods and the bits D3 during eight periods. More generally, the weight bits j activate the display component for 2 j periods.
  • the pixels 11d and 11e as well as the associated chronogram and represented on the figure 12 refer to a diode 25. It is understood that these variants can be implemented for any other type of display component, such as a liquid crystal cell or a micro mirror.
  • N 2 P - 1.
  • an eight-bit resolution imposes a matrix of 255 lines and a 10-bit resolution imposes a matrix of 1023 lines.
  • a first solution consists in artificially increasing by one unit the number of bits by systematically assigning a 0 to the new LSB LSB. This solution can also be implemented if it is desired to multiply the number of lines by any power of two. For example to quadruple the number of lines, two additional bits can be added.
  • the figure 13 offers an alternative to adding a low-order bit. More specifically, the line addressing circuit is duplicated and each circuit operates separately. On the figure 13 two line addressing circuits 13a and 13b are shown, each addressing one half of the matrix 11. More generally, the matrix 11 is divided into zones, 11a and 11b in the example shown, each of the zones having a line number less than or equal to 2 P -1. Here again, it is possible to multiply the number of line addressing circuits by any integer number.
  • the figure 14 describes the implementation of such virtual lines.
  • Several periods are represented in a way similar to the representation of figures 3 or 4 .
  • the total number of addressed lines 2 P - 1 is represented along an ordinate axis.
  • the number of real lines U of the matrix is equal to (2 P - 1) - V, V representing the number of virtual lines remaining addressed and whose brightness value is advantageously zero.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP16164462.0A 2015-04-10 2016-04-08 Bildanzeigeverfahren auf matrix-bildschirm Active EP3079142B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1553140A FR3034902B1 (fr) 2015-04-10 2015-04-10 Procede d’affichage d’images sur un ecran matriciel

Publications (2)

Publication Number Publication Date
EP3079142A1 true EP3079142A1 (de) 2016-10-12
EP3079142B1 EP3079142B1 (de) 2020-06-24

Family

ID=53274699

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16164462.0A Active EP3079142B1 (de) 2015-04-10 2016-04-08 Bildanzeigeverfahren auf matrix-bildschirm

Country Status (3)

Country Link
US (1) US10223961B2 (de)
EP (1) EP3079142B1 (de)
FR (1) FR3034902B1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023285449A1 (fr) 2021-07-16 2023-01-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif d'affichage interactif
EP4138128A1 (de) 2021-08-19 2023-02-22 Commissariat à l'énergie atomique et aux énergies alternatives Bilderfassungsvorrichtung

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10418405B2 (en) 2017-09-05 2019-09-17 Sony Semiconductor Solutions Corporation Sensor chip and electronic apparatus
KR102395792B1 (ko) 2017-10-18 2022-05-11 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
FR3079957B1 (fr) * 2018-04-05 2021-09-24 Commissariat Energie Atomique Dispositif et procede d'affichage d'images avec une memorisation de donnees realisee dans les pixels
GB201914186D0 (en) * 2019-10-01 2019-11-13 Barco Nv Driver for LED or OLED display

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011314A1 (en) * 2001-05-15 2003-01-16 Takaji Numao Display apparatus and display method
US20090058769A1 (en) * 2007-08-29 2009-03-05 Kazuyoshi Kawabe Active matrix display device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030011314A1 (en) * 2001-05-15 2003-01-16 Takaji Numao Display apparatus and display method
US20090058769A1 (en) * 2007-08-29 2009-03-05 Kazuyoshi Kawabe Active matrix display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023285449A1 (fr) 2021-07-16 2023-01-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif d'affichage interactif
FR3125358A1 (fr) 2021-07-16 2023-01-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif d'affichage interactif et procédé de fabrication d'un tel dispositif
EP4138128A1 (de) 2021-08-19 2023-02-22 Commissariat à l'énergie atomique et aux énergies alternatives Bilderfassungsvorrichtung
FR3126261A1 (fr) 2021-08-19 2023-02-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif de capture d'images et procédé de fabrication d'un tel dispositif

Also Published As

Publication number Publication date
FR3034902B1 (fr) 2017-05-19
US10223961B2 (en) 2019-03-05
FR3034902A1 (fr) 2016-10-14
EP3079142B1 (de) 2020-06-24
US20160300525A1 (en) 2016-10-13

Similar Documents

Publication Publication Date Title
EP3079142B1 (de) Bildanzeigeverfahren auf matrix-bildschirm
EP2013863B1 (de) Organisches elektrolumineszenzdisplay
EP0635819B1 (de) Verfahren und Einrichtung zur Steuerung einer Mikrospitzenanzeigevorrichtung
JP5733154B2 (ja) 液晶表示装置
EP2186081B1 (de) Schieberegister für einen aktivmatrixflachbildschirm
EP1964093B1 (de) Antriebsverfahren für eine plasmaanzeigetafel mit depolarisierung
EP1958182B1 (de) Videosystem mit einer durch ein verbessertes adressierungsverfahren gesteuerten flussigkristallmatrixanzeige
EP3550550A1 (de) Bildanzeigevorrichtung und -verfahren mit einer datenspeicherung in den pixeln
FR2784489A1 (fr) Procede d'affichage de donnees sur un afficheur matriciel
WO2007071680A1 (fr) Procede de pilotage d'un panneau d'affichage par couplage capacitif
EP1964095A1 (de) Anzeigeschirm und steuerverfarhen mit transienter kapazitiver kopplung
EP1864275B1 (de) Bildanzeigeeinrichtung und verfahren zu ihrer steuerung
EP1481387B1 (de) Teilfeldverfahren zur anzeige eines videobildes mit helligkeitsabstufung auf einem digitalen anzeigegerät mit artefaktreduktion
JP2015161836A (ja) 液晶表示装置
EP1958183A1 (de) Farbsequentielle flüssigkristallmatrixanzeige
FR2889763A1 (fr) Afficheur matriciel a affichage sequentiel des couleurs et procede d'adressage
EP2531998A1 (de) Verfahren zur schreibung in einem bild in einer flüssigkristallanzeige
EP2104092B1 (de) Anzeigevorrichtung, die in einem Sondermodus zur Anzeige mit geringem Energieverbrauch betrieben werden kann
WO2021115860A1 (fr) Dispositif comprenant un ecran d'affichage a mode de fonctionnement a basse consommation
EP0793212B1 (de) Steuerverfahren für eine Bildanzeigetafel mit Halbtönen und Anzeigeeinrichtung zur Durchführung dieses Verfahrens
FR2837607A1 (fr) Dispositif d'affichage numerique d'une image video
CA2536216A1 (fr) Micro-ecran de visualisation a cristaux liquides et son procede de commande
FR2826767A1 (fr) Procede d'affichage d'une image video sur un dispositif d'affichage numerique
FR3024796A1 (fr) Afficheur lcd avec adressage de lignes par echantillonnage et conversion, et procede d'affichage
JP2014132355A (ja) 液晶表示装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20170412

RBV Designated contracting states (corrected)

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20180206

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20200309

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SEGURA PUCHADES, JOSEP

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

GRAR Information related to intention to grant a patent recorded

Free format text: ORIGINAL CODE: EPIDOSNIGR71

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

INTC Intention to grant announced (deleted)
INTG Intention to grant announced

Effective date: 20200514

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602016038569

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1284673

Country of ref document: AT

Kind code of ref document: T

Effective date: 20200715

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: FRENCH

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200925

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200924

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200924

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20200624

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1284673

Country of ref document: AT

Kind code of ref document: T

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201026

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201024

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602016038569

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20210325

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20210408

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210408

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20210430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210408

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210430

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210408

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201024

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210430

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20160408

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240418

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240422

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20200624