EP2109247A1 - Detection of data received by a master device in a single-wire communication protocol - Google Patents

Abstract

The method involves determining a binary state of data transmitted by a slave device over a single-wire connection according to a slope of a rising edge of two-state signals i.e. voltage (V-MD), transmitted by a master device. The slope is determined based on a charge level of a capacitor on occurrence of the edge. The signals are used as clock signals by the slave device, where the two-state signals comprise a duty cycle modulated according to data to be transmitted from the master device to the slave device. An independent claim is also included for a transmission-reception device for transmitting a two-state signal to a device over a single-wire connection for modifying a charge that exhibits on the connection according to a binary data state.

Description

Field of the invention

The present invention generally relates to electronic circuits and, more particularly, to data transmissions between two devices on a single-wire link. The invention applies more particularly to systems implementing protocols known as the single-wire protocol (SWP).

Presentation of the prior art

The single-wire communication protocols are defined between a master device and a slave device sharing a single-wire link for transmitting data in a bidirectional simultaneous (full duplex) manner. Most often, the signal transmitted by the master device to the slave device is further a clock signal for synchronizing exchanges. In the direction master device to slave device, the duty cycle of a periodic signal is modulated according to the binary state to be transmitted. In the slave device to master device direction, the slave device modulates the load that it presents on the link according to the binary states of the data that it transmits. The detection by the slave device is carried out by measuring the ratio cyclic. The detection by the master device is performed by comparing a threshold level of the current drawn by the slave device on the link. The charge modulation by the slave device is generally carried out at the rhythm of the periodic signal, by positioning the load during the low states, so that the load to be detected by the master device is present over the entire high state of the signal. .

The document US-A-5,903,607 describes an example of coding and data transmission between a master circuit and a slave circuit.

The communication rate in a single-wire protocol is related, among other things, to the delay required for the master device detection. It must indeed be expected that, following the rising edges of the signal, the levels are established to perform the comparison.

In addition, a detection by level is sensitive to the noise of the line which imposes a relatively large margin of safety to differentiate the levels.

summary

It would be desirable to have a single-wire communication protocol that overcomes all or part of the disadvantages of the usual systems.

In particular, it would be desirable to have an increased communication rate.

It would also be desirable to have a detection mechanism, on the master device side, which is less sensitive to the noise of the line.

To achieve all or part of these objects as well as others, there is provided a method of determining, by a first device adapted to emit a two-state signal on a single-wire link to a second device, the state binary data transmitted by the second device on said link, said state being determined from the slope of a rising edge of said two-state signal.

According to one embodiment, the slope is determined from the level of charge of a capacitive element to the appearance of a rising edge.

According to one embodiment, the charge level is compared with a threshold to determine the received state.

According to one embodiment, the slope of the rising edge has a break for a first binary state and is regular for a second state.

According to one embodiment, the second device modulates the load that it presents on the link according to the binary state that it emits.

According to one embodiment, said signal serves as a clock signal to the second device.

According to one embodiment, said signal is modulated in cyclic ratio as a function of data to be transmitted from the first device to the second.

• un élément de mesure d'une information représentative de la pente des fronts montants dudit signal ; et
• un élément de comparaison de ladite information par rapport à un seuil.

There is also provided a transmission-reception device on a single-wire link, capable of transmitting a two-state signal to another device capable of modifying the load it has on the link according to the binary state of data. it emits back, comprising:

• an element for measuring information representative of the slope of the rising edges of said signal; and
• an element for comparing said information with respect to a threshold.

According to one embodiment, the device further comprises a switching element of the power of a transmission amplifier of said signal, activated after detecting a state corresponding to a load of the second device.

There is also provided a bidirectional transmission system simultaneously on a single-wire link between a master device and a slave device.

Brief description of the drawings

• la figure 1 est un schéma bloc d'un système de communication radiofréquence dont au moins un des éléments met en oeuvre, en interne, un protocole de communication unifilaire entre des dispositifs qu'il comporte ;
• la figure 2 est un schéma bloc d'un système de communication unifilaire entre un circuit maître et un circuit esclave ;
• la figure 3 illustre un exemple d'allure d'un signal de données à émettre par le dispositif maître ;
• les figures 4A, 4B et 4C illustrent un exemple de niveaux de tension et de courant dans une application de type routeur de communication à faible distance ;
• la figure 5 est un schéma bloc fonctionnel et partiel d'un mode de réalisation d'un dispositif maître ;
• la figure 6 représente schématiquement un mode de réalisation du circuit de détection de la figure 5 ; et
• les figures 7A à 7E sont des chronogrammes illustrant le fonctionnement du circuit de la figure 6.

These and other objects, features, and benefits will be discussed in detail in the following description particular embodiments made in a non-limiting manner in relation to the attached figures among which:

• the figure 1 is a block diagram of a radio frequency communication system in which at least one of the elements implements, internally, a single-wire communication protocol between the devices that it comprises;
• the figure 2 is a block diagram of a single-wire communication system between a master circuit and a slave circuit;
• the figure 3 illustrates an example of a pace of a data signal to be transmitted by the master device;
• the Figures 4A, 4B and 4C illustrate an example of voltage and current levels in a short-range communication router application;
• the figure 5 is a functional and partial block diagram of an embodiment of a master device;
• the figure 6 schematically represents an embodiment of the detection circuit of the figure 5 ; and
• the Figures 7A to 7E are chronograms illustrating the operation of the circuit of the figure 6 .

detailed description

The same elements have been designated by the same references to the various figures whose chronograms have been drawn without respect of scale. For the sake of clarity, only the steps and elements useful for understanding the invention have been shown and will be described. In particular, the mechanisms for generating and using the data to be transmitted and the data received have not been detailed, the invention being compatible with the usual mechanisms. In addition, the various systems and hardware devices capable of implementing the described embodiments have also not been detailed, the implementation of the invention being compatible with any system or device capable of implementing a protocol unifilar, better known as Single Wire Protocol (SWP).

The figure 1 is a block diagram of a radiofrequency communication system between a first element 1 and another element 2, each provided with a transmission-reception circuit for communicating by means of an antenna 11 or 21. for example, a radiofrequency communication system by inductive coupling. For example, the element 2 is a card-type radiofrequency object or contactless reader and the element 1 is a similar object including a contact-type processing part (secure identification module (SIM), a processing circuit). a mobile phone, etc.).

At least one of the elements (in the example, element 1) includes a router 13 called NFC (Near Field Communication) capable of managing communications between a radio frequency portion 12 (RF PART) and a processing part 14 (PROC) GO). The purpose of the router 13 is, among other things, to serve as an interface between the radiofrequency part with which it communicates bi-directionally and the processing part 14 with which it communicates on a single wire 3.

In this kind of application, the full duplex protocol used for the communication between the router 13 and the processing part 14 is an SWP protocol. The router behaves as a master device and sends data to the circuit 14 which behaves like a slave device.

The figure 2 represents a block diagram of a communication system uniliaison between a master device 13 (MD) and a slave device 14 (SD) via a single-wire link 3. This figure illustrates, more generally, that the modes embodiments that will be described may apply regardless of the type of system, provided that it operates a single-line communication protocol.

The figure 3 is a timing diagram illustrating an exemplary appearance of a periodic signal S1 provided on the line 3 by the master device 13 and whose duty cycle is a function of a digital data stream to be transmitted. In the example of the figure 3 , the transmission of a state 1 is effected by a high level H on about three quarters of the clock period T (low level L on a quarter of the period T) while the transmission of a state 0 is performed by a high level H only on the order of a quarter of this clock period (low level L of the remaining three quarters). The signal S1 is emitted by the master device by means of an output amplifier in the form of a voltage V _MD .

The Figures 4A, 4B and 4C illustrate an example of the voltage and current levels used by a single-wire protocol to distinguish transmitted binary states. These levels do not take into account signal establishment times.

The Figure 4A illustrates the voltage levels, respectively high H and low L, that can take the V _MD signal. The protocol defines in a standardized way a range of voltages for the low and high levels of the periodic signal (between a level V _OLmin and a level V _OLmax for the low level L and between a level V _OHmin and a level V _OHmax for the high level H). In a particular example (standard SWP for a supply voltage Vdd between 1.62 and 1.98 volts (class C)), the levels V _OHmax and V _OHmin are respectively Vdd (for example 1.98 volts) and 0.85 * Vdd (for example 1.377 volts) and the level V _OLmax is 0.15 * Vdd (for example, 0.297 volts), the level V _OLmin being the mass (0 volts).

The Figure 4B illustrates the voltage ranges of a signal V _SD corresponding to the input voltage of the slave device 14, therefore to the image of the signal V _MD slave device side. These ranges define the voltages within which this device 14 considers that the signal received is at a high level H or a low level L. These ranges are defined by levels V _ILmin and V _ILmax to consider a signal at the high level H and levels V _IHmin and V _IHmax to consider a signal at the low level L. The ranges V _OLmin -V _OLmax and V _OHmin -V _OHmax are of course respectively within the ranges V _ILmin -V _ILmax and V _IHmin - V _IHmax . The detection of the signal level V _SD by the slave device serves to reconstruct the signal S1. The slave device 14 uses this signal both as a synchronization signal of its exchanges with the master device and, by the durations of the low levels, to detect the data conveyed by this signal.

FIG. 3C illustrates the charge modulation operated by a slave device 14 on the single-wire link 3 for transmitting data to the master device 13. This figure illustrates ranges I _Lmin- I _Lmax and I _Hmin -I _Hmax of the current I _W on the line 3 which define binary states 0 and 1 of the data transmitted by the slave device. Taking again the example of system acquisition program above, the thresholds I _Lmin and I _Lmax are respectively 0 and about 20 microamperes and the thresholds I _Hmin and I _Hmax are respectively about 600 microamperes and d about 1 milliampere.

From a temporal point of view, the slave device 14 uses the durations during which the signal V _SD is low to position the load (thus define the current I _W ) that it applies to the line. Thus, when the master device 13 switches the state of the signal V _MD to the high state, it can evaluate the current on the line.

In the usual devices, it is clearly seen that, in order to detect this current level, the signal V _MD must be set high. This setup time (which depends on the load applied by the slave device) therefore conditions the minimum duration of the high level of the signal V _MD , thus the minimum duration of the high level for a bit 0 transmitted, therefore the system throughput.

The figure 5 is a partial block diagram of a master device illustrating an embodiment of circuits 4 for sending the periodic stream S1 and for determining the binary state S2 of data received in return. The signal to be transmitted (for example the pace of figure 3 ) is provided as a digital train S1 to an output amplifier 41 (Output buffer-OB). This output amplifier supplies the voltage V _MD on a single pad 42 for connection to the line 3. The signal present on the pad 42 is also used by the device master himself to assess the slope of rising fronts. In the example of the figure 5 the signal V _MD serves to close a load switch K of a capacitive element 431 of a slope detection circuit 43. The switch K and the capacitive element 431 are in series with a current source 432 between two terminals for applying a supply voltage Vdd. The charge level of the element 431 is evaluated by a measurement circuit 44 (MES) which provides a binary signal S2 corresponding to the received data.

The figure 5 illustrates a preferred embodiment of the output amplifier 41 according to which it modifies its transmission power in the case of a large load applied by the slave device. The objective is, once the signal S2 has been detected, to make up the relatively steep slope of the rising edge so as not to delay the establishment of a stable level of the voltage V _MD which is moreover used on the slave device for measure the transmitted data in the master-slave direction.

Such a functionality is for example obtained by switching, in the output amplifier 41, high leveling circuits (generally P-channel MOS transistors) and / or low leveling circuits (generally MOS transistors to N channel) to vary the output power. In the example shown, it is assumed the presence of a single low leveling circuit 411, sized for maximum power and two high leveling circuits 412 and 413 respectively sized for a relatively low power (SP) and for a relatively high power (BP). For example, different sizes are provided for the P-channel MOS transistors constituting the circuits 412 and 413, the N-channel transistor constituting the circuit 411 being of the same size as the sum of the sizes of the P-channel transistors. The inverse is of course possible.

The master device first transmits with the amplifier 41 configured with the circuit 413 of low power of so that the slope of establishment of the signal is conditioned by the load present on the line, thus applied by the slave device. Once the detection is carried out, if the measuring device 44 indicates to the amplifier 41 the presence of a state 1, the amplifier 41 switches to the high power circuit 411. It is then able to provide a larger current output. Thus, even with a greater load, the slope of the rising edge becomes sufficient.

The fact of accelerating the rising edge on strong load makes it possible to increase the transmission rate.

The switching of the output amplifier 41, however, remains optional, in particular for the case where this increase in flow rate is not desired. A determination of the state by an interpretation of the slope of the rising edges nevertheless makes the system less sensitive to noise.

On the slave device side, intervention on the rising edge slope is not detrimental. Conversely, it is possible to size the circuits of the output amplifier 41 so that the establishment time of the signal V _MD is identical in the two load cases by causing a greater slope at the end of the rising edge on high load. to reach the high level at approximately the same time as in the case of low load. This leaves more flexibility in the realization of the slave device because it is then possible to detect indifferently the duration of the high or low steps to reconstruct the periodic signal and decode the received signal.

The figure 7 illustrates an embodiment of the circuits 43 and 44 in which the switch K (for example a MOS or bipolar type transistor) is controlled at the opening by a comparator 435 of the voltage present on the terminal 42 with respect to a threshold Ref. An inverter 436 of the signal on the pad 42 controls another switch K 'placed in parallel on the capacitor 431 to short-circuit it. Thus, when the signal V _MD is in the low state, the switch K 'is closed. At the appearance of a rising edge of the signal V _MD , (neglecting the signal establishment times in the elements 435 and 436), the switch K is closed and the switch K 'is open. Capacitor 431 therefore charges. Its charge is interrupted when the signal level V _MD reaches the threshold Ref. The circuit 44 comprises a comparator 441 of the voltage level across the capacitor 431 with respect to a threshold TH. The comparator 441 provides the signal S2.

The Figures 7A to 7E are chronograms illustrating the operation of the circuit of the figure 6 . These timing diagrams respectively represent examples of the steps of the signal S1 of the master device for transmitting a stream 1010, the charge level R2 presented by the slave device on the line for transmitting a stream 0011, the voltage V _MD , the voltage V ₄₃₁ at the terminals of the capacitive element 431 and the signal S2 detected by the master device. To simplify the description that follows, we neglect the propagation time in the circuits.

At each period T of the signal S1, the latter switches to the high level at a time t1, then to the low level at a time t2 ₀ for the transmission of a 0 or t2 ₁ posterior for the transmission of a 1. To a instant t0 which precedes each instant t1, that is to say during the low state part L of the period T which precedes, the slave device positions its charge between a maximum or relatively high load, for example to transmit a 1, or minimum or relatively low (relative to the relatively high load) to then transmit a 0. This is illustrated by two levels S (low load) and B (high) of a signal R2 ( Figure 7B ). In the example, it is assumed that the signal R2 passes from one level to the other if necessary at each instant t0. Generally in an SWP protocol, there is a communication waiting state in which the signals S1 and S2 are respectively 1 and 0. The slave device causes the output of this state by switching its load.

At each instant t1, the signal V _MD begins to grow which causes the opening of the switch K '(in practice as soon as the voltage level is sufficient to switch the inverter 436) and the closing of the switch K. The charge of the capacitor 431 therefore begins approximately at time t1. The slope of the voltage V ₄₃₁ is set by the current source 432, preferably at a constant current. On the other hand, the slope of the voltage V _MD depends on the level B or S of the load imposed by the slave device. This difference in slope is taken advantage of to detect the level 0 or 1 transmitted.

With a low load S (transmission of a state 0), the slope is greater than with a high load B (transmission of a state 1). Consequently, the voltage V _MD reaches the threshold Ref at a time t3 ₀ earlier than it would reach it (time t3 ₁ ) in the case of a load B.

The threshold TH of the comparator 441 is chosen to be greater than the voltage level reached at the terminals of the capacitor 431 at the opening of the switch K in the event of a steep slope of the current (therefore of the voltage V _MD ). Therefore, the signal S2 remains at the low level L indicating a received binary state 0.

With a higher load B imposed by the slave device, the slope of the signal V _MD is lower.

The threshold Ref of the comparator 435 is chosen so that, in the event of a small slope of the signal V _MD , the voltage V ₄₃₁ across the capacitor 431 reaches the threshold TH before the voltage V _MD has reached the threshold Ref. Therefore, the comparator 441 switches at a time t4 ₁ , which causes the high state of the signal S2 indicating a binary state 1.

In a simplified embodiment, the amplifier 41 does not modify its output power and the voltage V _MD reaches the Ref level at time t3 ₁ . The switch K opens and the charge of the capacitor 431 stops.

In the preferred embodiment shown, the switching of the signal S2 at the instant t4 ₁ causes the switching of the output amplifier 41 (FIG. figure 5 ) to a higher power. Consequently, there is a change of slope of the rising edge of the signal V _MD (or I _W ) which then reaches the high level faster. This results in an earlier stop of the charge of the capacitor 431.

At each falling edge (times t2 ₀ , t2 ₁ ) of the signal S1, the capacitor 431 is reset (discharged) by the closing of the switch K '.

An advantage of an interruption of the charge of the capacitor 431 is that it reduces the consumption of the detection circuit.

The synchronization of the different circuits does not pose a problem insofar as the master device side, it manages the synchronization not only of its own circuits but also of the slave device.

Various embodiments have been described, various variations and modifications are within the reach of those skilled in the art. In particular, the choice of timing instants and voltage levels and thresholds is within the abilities of those skilled in the art from the functional indications given above and the application. In addition, the practical implementation of the invention from the functional indications given above is also within its reach and in particular the realization of output stages of the different gain amplifier. In addition, the binary states 0 and 1 illustrated are conventions and may be reversed.

Claims (10)

Method of determining, by a first device (13) adapted to transmit a two-state signal (V _MD ) on a single-wire link (3) to a second device (14), of the binary state of a data item transmitted by the second device over said link, characterized in that said state is determined from the slope of a rising edge of said two-state signal. The method of claim 1, wherein the slope is determined from the charge level of a capacitive element (431) to the appearance of a rising edge. The method of claim 2, wherein the level of charge is compared to a threshold (TH) to determine the received state. A method according to any one of claims 1 to 3, wherein the slope of the rising edge has a break for a first binary state (1) and regular for a second state (0). Method according to any one of claims 1 to 4, wherein the second device (14) modulates the load it has on the link (3) according to the binary state that it emits. A method as claimed in any one of claims 1 to 5, wherein said signal (V _MD ) serves as a clock signal to the second device (14). A method according to any one of claims 1 to 6, wherein said signal (V _MD ) is cyclically modulated based on data (S1) to be transmitted from the first device (13) to the second (14). Transmitting-receiving device (13) on a single-wire link (3), adapted to transmit a two-state signal (V _MD ) to another device (14) capable of modifying the load on the device link according to the binary state of data that it sends back, characterized in that it comprises: an element (43) for measuring information representative of the slope of the rising edges of said signal; and an element (44) for comparing said information with respect to a threshold, for determining said binary state. An apparatus according to claim 8, further comprising a switching element of the power of a transmit amplifier (41) of said signal, activated after detecting a state corresponding to a load of the second device. Simultaneous bidirectional transmission system on a single-wire link (3) between a master device (13) and a slave device (14), in which the first device is adapted to carry out the method according to any one of claims 1 to 7.

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