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CN115033508B - Single-wire bidirectional direct communication circuit and method between PADs in chip - Google Patents

Single-wire bidirectional direct communication circuit and method between PADs in chip Download PDF

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CN115033508B
CN115033508B CN202210704870.1A CN202210704870A CN115033508B CN 115033508 B CN115033508 B CN 115033508B CN 202210704870 A CN202210704870 A CN 202210704870A CN 115033508 B CN115033508 B CN 115033508B
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gate
level signal
pad
unidirectional
module
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CN115033508A (en
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赵红涛
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Zhuhai Shengsheng Microelectronic Co ltd
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Zhuhai Shengsheng Microelectronic Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

A single-wire bidirectional direct communication circuit and method between PADs in a chip are disclosed, wherein the circuit comprises a processor unit, a communication unit, a register unit, a first PAD end, a second PAD end, a first unidirectional direct module and a second unidirectional direct module; the first unidirectional direct connection module is used for transmitting a first level signal from the first PAD end to the second PAD end in a unidirectional mode; the second unidirectional direct-connection module is used for transmitting a second level signal from the second PAD end to the first PAD end in a unidirectional mode; the first unidirectional through module is connected with the second unidirectional through module through an internal node; in the chip, the processor unit sends a starting instruction of a bidirectional direct communication mode to the communication unit and the register unit according to a communication protocol; the communication unit receives a starting instruction of the bidirectional direct communication mode and sets the first unidirectional direct communication module and the second unidirectional direct communication module to be in the bidirectional direct communication mode, namely data transmission and data reception of the first PAD end and the second PAD end follow a communication protocol of the processor unit.

Description

Single-wire bidirectional direct communication circuit and method between PADs in chip
Technical Field
The invention relates to the field of chip internal communication, in particular to a single-wire bidirectional direct communication circuit and a method between PADs in a chip.
Background
In the existing embedded electronic product, once the PCB is mounted on the housing, it is difficult to debug and upgrade other chips besides the main control chip on the PCB. At this time, the closed shell is often required to be opened, and the closed shell is connected to a debugger through flying wires on corresponding pads on the PCB, so that debugging or firmware upgrading can be carried out;
if the product comprises a main control chip and a debugging chip, an external communication main body needs to be connected with the debugging chip of the product, and the debugging chip and an external interface of the product have no physical connection line, in the prior art, the external communication main body and the debugging chip are connected by building an electronic circuit on the main control chip, so that the connection of the external communication main body and the debugging chip is realized; the switching of the transmission direction needs the participation of software of a main control chip, once a channel is established, an external communication main body is directly communicated with a debugging chip, the software running on the main control chip does not have a chance to participate in the switching process of the communication direction, a hardware circuit cannot adapt, so that the single-wire two-way communication in the true sense cannot be realized, only the single-wire one-way communication can be realized at best, and the application scene is limited greatly.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a single-wire bidirectional direct communication circuit and a method between PADs in a chip, which are used for solving the communication problem between an external communication main body and a chip in a product.
In order to solve the problems, the technical scheme adopted by the invention is as follows:
the circuit for bidirectional direct communication between the PAD points in the chip A is built, the first PAD end is connected with the external communication main body, the second PAD end is connected with the other chip B which is communicated with the external communication main body, and when the external communication main body and the internal chip B do not need to be communicated, the two PAD points are used for normal signal transmission communication in the chip A; when the external communication body needs to communicate with the internal chip B, the two PAD points form a bidirectional through communication circuit in the chip A for signal transmission communication between the external communication body and the internal chip B.
A single-wire bidirectional direct communication circuit among PADs in a chip comprises a processor unit, a communication unit, a register unit, a first PAD end and a second PAD end,
the device comprises a first unidirectional through module and a second unidirectional through module; the first unidirectional through module is used for the unidirectional transmission of a first level signal from the first PAD end to the second PAD end; the second unidirectional through module is used for the second PAD end to transmit a second level signal to the first PAD end in a unidirectional way; the first unidirectional through module is connected with the second unidirectional through module through an internal node; the first unidirectional through module comprises a first input end, a first output end and a first control end; the second unidirectional through module comprises a second input end, a second output end and a second control end; the first input end is connected with the first PAD end and the second output end, the second input end is connected with the second PAD end and the first output end, and the first control end and the second control end are connected with the register unit.
The processor unit is respectively connected with the communication unit and the register unit; the processor unit is used for controlling the switches of the communication unit and the register unit during bidirectional communication, is connected with the first unidirectional through module and the second unidirectional through module through the communication unit, and is connected with the first control end and the second control end through the register unit; and the first end of the register unit is connected with the first control end, and the second end of the register unit is connected with the second control end.
Further, the first unidirectional through module comprises a first and gate, a first resistor, a first or gate, a first not gate, a second not gate and a first tri-state gate; a first input end of the first AND gate is connected with the first PAD end and the second output end, and a second input end of the first AND gate is connected with a first end of the register unit; the first end of the first resistor is connected with the first PAD end, and the second end of the first resistor is connected with a direct-current power supply; the first input end of the first OR gate is connected with the output end of the first AND gate; the input end of the first NOT gate is connected with the second unidirectional through module through the internal node, and the output end of the first NOT gate is connected with the second input end of the first OR gate; the input end of the second NOT gate is connected with the output end of the first OR gate and the input end of the first tri-state gate; and the output end of the first tri-state gate is connected with the output end of the second NOT gate and the second PAD end.
The second unidirectional through module comprises a second AND gate, a second resistor, a second OR gate, a third NOT gate, a fourth NOT gate and a second tri-state gate; a first input end of the second AND gate is connected with the first PAD end and the second output end, and a second input end of the second AND gate is connected with a first end of the register unit; the first end of the second resistor is connected with the second PAD end, and the second end of the second resistor is connected with a direct current power supply; the first input end of the second OR gate is connected with the output end of the second AND gate; the input end of the third NOT gate is connected with the first unidirectional through module through the internal node, and the output end of the third NOT gate is connected with the second input end of the second OR gate; the input end of the fourth NOT gate is connected with the output end of the second OR gate and the input end of the second tri-state gate; and the output end of the second tri-state gate is connected with the output end of the fourth NOT gate and the first PAD end.
Further, the connection relationship of the internal nodes of the first unidirectional through module and the second unidirectional through module is as follows: the output end of the first OR gate is connected with the input end of the third NOT gate, and the output end of the second OR gate is connected with the input end of the first NOT gate.
A single-wire bidirectional direct communication method between PADs in a chip comprises the following steps,
in the chip, the processor unit sends a starting instruction of a bidirectional direct communication mode to the communication unit and the register unit according to a communication protocol; the communication unit receives a starting instruction of a bidirectional direct communication mode and sets the first unidirectional direct communication module and the second unidirectional direct communication module to be in the bidirectional direct communication mode, namely, data transmission and data reception of the first PAD end and the second PAD end follow a communication protocol of a processor unit; the register unit receives a starting instruction of a bidirectional straight-through communication mode, a first output end of the register unit sends a first control signal to the first control end, and the first control signal is used for controlling the first unidirectional straight-through module to be switched on and switched off; and a second output end of the register unit sends a second control signal to the second control end, and the second control signal is used for controlling the second unidirectional through module to be switched on and off.
When two-way direct communication is needed between two PAD terminals, the communication steps are as follows:
according to a communication protocol, the first unidirectional direct connection module and the second unidirectional direct connection module allocate the first PAD end and the second PAD end to be in a sending or receiving state according to a signal transmission direction;
when the first PAD end is in a sending state and the second PAD end is in a receiving state: a first input end of the first unidirectional through module receives a first level signal sent by the first PAD end, and a second input end of the first unidirectional through module receives a first control signal sent by the first control end; a second input end of the second unidirectional through module receives a second control signal sent by the second control end; the first PAD end sends a first level signal to the second PAD end through the first unidirectional through module; meanwhile, a first level signal keeps a sending state of a first unidirectional through module through the connection relation of the internal nodes, and the signal output of a first output end of a second unidirectional through module is interrupted;
when the second PAD end is in a sending state and the first PAD end is in a receiving state: a first input end of the second unidirectional through module receives a second level signal sent by the second PAD end, and a second input end of the second unidirectional through module receives a second control signal sent by the second control end; a second input end of the first unidirectional through module receives a first control signal sent by the first control end; the second PAD end sends a second level signal to the second PAD end through the second unidirectional through module; meanwhile, a second level signal keeps a sending state of a second unidirectional through module through the connection relation of the internal nodes, and the signal output of the first output end of the first unidirectional through module is interrupted.
Further, when the first PAD is in a sending state and the second PAD is in a receiving state:
the first input end of the first AND gate receives a first level signal sent by the first PAD end, the second input end of the first AND gate receives a first control signal, and the first level signal and the first control signal are subjected to AND processing and the first level signal is output to the first OR gate; the first control signal and the first control signal are high level signals; a first input end of the first OR gate receives a first level signal, a second PAD end defaults to be a high level and ensures an output end of the first NOT gate to be a low level signal through the connection relation of the internal nodes, and further ensures that the output end of the first OR gate outputs the first level signal; the input end of the second not gate and the input end of the first tri-state gate receive the first level signal sent by the output end of the first or gate, the second not gate inverts the first level signal, and the output end of the second not gate outputs the inverted signal of the first level signal to the control end of the first tri-state gate; when the first level signal is a high level signal, the control end of the first tri-state gate is a low level signal, the first tri-state gate is not conducted, the output end of the first tri-state gate does not output a high level signal, and the second PAD end pulls up a set high level signal through the second resistor; when the first level signal is a low level signal, the control end of the first tri-state gate is a high level signal, the first tri-state gate is turned on, the output end of the first tri-state gate is a low level signal, and the second PAD end sets the low level signal.
When the second PAD end is in a sending state and the first PAD end is in a receiving state:
the first input end of the second AND gate receives a second level signal sent by the second PAD end, the second input end of the second AND gate receives a second control signal, and the second level signal and the second control signal are subjected to phase-AND processing and output to a second OR gate; the second control signal and the second control signal are high level signals; a first input end of the second OR gate receives a second level signal, a first PAD end defaults to be a high level, and the output end of the second NOT gate is ensured to be a low level signal through the connection relation of the internal nodes, so that the output end of the second OR gate is ensured to output the first level signal; the input end of the fourth not gate and the input end of the second tri-state gate receive a second level signal sent by the output end of the second or gate, the fourth not gate inverts the second level signal, and the output end of the fourth not gate outputs an inverted signal of the first level signal to the control end of the second tri-state gate; when the second level signal is a high level signal, the control end of the second tri-state gate is a low level signal, the second tri-state gate is not conducted, the output end of the second tri-state gate does not output a high level signal, and the first PAD end pulls up the set high level signal through the second resistor; when the second level signal is a low level signal, the control end of the second tri-state gate is a high level signal, the second tri-state gate is turned on, the output end of the second tri-state gate is a low level signal, and the position of the first PAD end is a low level signal.
Further, when the first PAD terminal starts to transmit the first level signal to the second PAD terminal: the first input end and the second input end of the second AND gate are high level and output high level signals; the second OR gate outputs a high level signal, and the output end of the third NOT gate is at a low level; when the first PAD terminal sends a first level signal to the second PAD terminal: the third not gate outputs an inverted signal of the first level signal, the first input end of the second and gate receives the first level signal, the second or gate outputs a high level signal, the output end of the first not gate and the output end of the fourth not gate keep low level, the first or gate keeps outputting the first level signal, and the output end of the second tri-state gate does not output a signal.
Further, when the second PAD terminal starts to transmit the second level signal to the first PAD terminal: the first input end and the second input end of the first AND gate are high level and output high level signals; the first OR gate outputs a high level signal, and the output end of the first NOT gate is at a low level; when the second PAD terminal sends a first level signal to the first PAD terminal: the first not gate outputs an inverted signal of a first level signal, the first input end of the first and gate receives the first level signal, the first or gate outputs a high level signal, the output end of the third not gate and the output end of the second not gate keep low level, the second or gate keeps outputting the first level signal, and the output end of the first tri-state gate does not output a signal.
Compared with the prior art, the invention has the beneficial effects that: by building a bidirectional direct communication circuit between two PAD ends in a chip, when an external communication main body and another chip do not need to communicate, a first PAD end and a second PAD end can be used as common endpoints to carry out signal transmission; when the external communication body needs to communicate with another chip, the first PAD end is connected with the external communication body, and the second PAD end is connected with the other chip; the processor unit in the chip controls the on and off of the single-wire bidirectional direct communication circuit through the register unit, the receiving or sending states of the first PAD end and the second PAD end are kept through the structure of the single-wire bidirectional direct communication circuit, and the signal transmission and switching of the first PAD end and the second PAD end are carried out according to a communication protocol; the circuit hardware self-adaptation and the software coordinated transmission are achieved, and the real single-wire bidirectional direct communication is realized.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram according to an embodiment of the present invention.
The reference numbers illustrate: a first resistance: r1, second resistance: r2, a first AND gate: and gate 1, second and gate: and gate 2, first or gate: or gate 1, second or gate: or gate 2, first not gate: not gate 1, second not gate: not gate 2, third not gate: not gate 3, fourth not gate: not gate 4, first tri-state gate: three-state gate 1, second three-state gate: a tri-state gate 2;
Detailed Description
The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes in detail may be made without departing from the spirit of the disclosure, from various aspects and applications of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
A single-wire bidirectional direct communication circuit among PADs in a chip comprises a processor unit, a communication unit, a register unit, a first PAD end and a second PAD end;
the circuit also comprises a first unidirectional through module 1 and a second unidirectional through module 2; the first unidirectional through module 1 comprises a first input end, a first output end and a first control end; the second unidirectional through module 2 includes a second input terminal, a second output terminal, and a second control terminal.
The first unidirectional direct connection module is used for transmitting a first level signal from the first PAD end to the second PAD end in a unidirectional mode; the second unidirectional direct-connection module is used for transmitting a second level signal from the second PAD end to the first PAD end in a unidirectional mode; the first unidirectional through module is connected with the second unidirectional through module through an internal node; the first input end is connected with the first PAD end and the second output end, the second input end is connected with the second PAD end and the first output end, and the first control end and the second control end are connected with the register unit.
The processor unit is connected with the register unit and the communication unit; the processor unit is used for controlling the switch of the register unit and the communication unit during bidirectional communication; the communication unit is connected with the first unidirectional through module 1 and the second unidirectional through module 2; the first end of the register unit is connected with the first control end, and the second end of the register unit is connected with the second control end; the first unidirectional through module 1 is used for transmitting a first level signal inside a chip, the second unidirectional through module 2 is used for transmitting a second level signal inside the chip, and the first unidirectional through module 1 is connected with the second unidirectional through module 2 through an internal node;
the first PAD end is connected with a first input end of the first unidirectional through module 1 and a first output end of the second unidirectional through module 2 and used for sending a signal of the first unidirectional through module 1 and receiving a sending signal of the second unidirectional through module 2 during bidirectional communication; the second PAD end is connected to the second input end of the second unidirectional through module 2 and the first output end of the first unidirectional through module 1, and is used for sending a signal of the second unidirectional through module 2 and receiving a sending signal of the first unidirectional through module 1 during bidirectional communication.
Specifically, as shown in fig. 1, the first unidirectional pass-through module 1 includes a first and gate, a first resistor R1, a first or gate, a first not gate, a second not gate, and a first tri-state gate; the second unidirectional through module 2 comprises a second AND gate, a second resistor R2, a second OR gate, a third NOT gate, a fourth NOT gate and a second tri-state gate; the first input end of the first AND gate is connected with a first PAD end and a second output end, the second input end of the first AND gate is connected with the first end of the register unit, the first end of a first resistor R1 is connected with the first PAD end, the second end of the first resistor R1 is connected with a direct current power supply, the first input end of the first OR gate is connected with the output end of the first AND gate, the input end of the first NOT gate is connected with the second unidirectional through module through an internal node, the output end of the first NOT gate is connected with the second input end of the first OR gate, the input end of the second NOT gate is connected with the output end of the first OR gate and the input end of the first tristate gate, the output end of the first tristate gate is connected with the output end of the second not gate and the second PAD end, the first input end of the second AND gate is connected with the first PAD end and the second output end, the second input end of the second AND gate is connected with the first end of the register unit, the first end of the second resistor is connected with the second PAD end, the second end of the second resistor is connected with the direct-current power supply, the first input end of the second OR gate is connected with the output end of the second AND gate, the input end of the third not gate is connected with the first one-way through module through an internal node, the output end of the third not gate is connected with the second input end of the second OR gate, and the input end of the fourth not gate is connected with the output end of the second OR gate and the input end of the second tristate gate; the output end of the second tri-state gate is connected with the output end of the fourth NOT gate and the first PAD end.
Specifically, the connection relationship between the internal nodes of the first unidirectional through module and the second unidirectional through module is as follows: the output end of the first OR gate is connected with the input end of the third NOT gate, and the output end of the second OR gate is connected with the input end of the first NOT gate.
A single-wire bidirectional direct communication method between PADs in a chip comprises the following steps:
when the external communication main body does not need to carry out bidirectional communication with another chip, the first PAD end and the second PAD end are normal PAD ends and are used for data transmission inside the chip, and the data transmission comprises input and output of signals such as UART, I2C, GPIO and the like; the first PAD end of the pull-up setting is set to be high level by the first resistor R1 in a default mode, the second PAD end of the pull-up setting is set to be high level by the second resistor R2 in a default mode, and signal transmission is not carried out between the first unidirectional through module 1 and the second unidirectional through module 2.
When the external communication main body needs to carry out bidirectional communication with another chip, the external communication main body is connected by a first PAD end, another chip is connected to a second PAD end, a bidirectional direct communication circuit is formed by a first unidirectional direct communication module 1 and a second unidirectional direct communication module 2, and the bidirectional communication steps of the first PAD end and the second PAD end are as follows:
the processor unit sends a starting instruction of a bidirectional direct communication mode to the communication unit and the register unit according to a communication protocol; the communication unit receives a starting instruction of a bidirectional direct communication mode and sets the first unidirectional direct module and the second unidirectional direct module to be in the bidirectional direct communication mode, namely data transmission and data reception of the first PAD end and the second PAD end follow a communication protocol of the processor unit; the register unit receives a starting instruction of a bidirectional direct communication mode, a first output end of the register unit sends a first control signal to a first control end, and the first control signal is used for controlling the conduction and the closing of a first unidirectional direct module; and a second output end of the register unit sends a second control signal to a second control end, and the second control signal is used for controlling the conduction and the closing of the second unidirectional through module.
According to the communication protocol, the first unidirectional through module 1 and the second unidirectional through module 2 allocate the first PAD end and the second PAD end to be in a sending or receiving state according to the signal transmission direction.
When the first PAD end starts to send a first level signal to the second PAD end: the first input end and the second input end of the second AND gate are high level and output high level signals; the second OR gate outputs a high level signal, and the output end of the third NOT gate is at a low level.
When the second PAD end starts to send a second level signal to the first PAD end: the first input end and the second input end of the first AND gate are high level and output high level signals; the first OR gate outputs a high level signal, and the output end of the first NOT gate is at a low level.
When the first PAD terminal sends a first level signal to the second PAD terminal: a first unidirectional through module, a first input end of which receives a first level signal sent by a first PAD end, and a second input end of which receives a first control signal sent by a first control end; a second input end of the second unidirectional through module receives a second control signal sent by a second control end; the first PAD end sends a first level signal to the second PAD end through the first one-way direct connection module; meanwhile, the first level signal keeps the sending state of the first unidirectional through module through the connection relation of the internal nodes, and interrupts the signal output of the first output end of the second unidirectional through module; the third NOT gate outputs an inverted signal of the first level signal, the first input end of the second AND gate receives the first level signal, the second OR gate outputs a high level signal, the output end of the first NOT gate and the output end of the fourth NOT gate keep low level, the first OR gate keeps outputting the first level signal, and the output end of the second tri-state gate does not output a signal.
Specifically, a first input end of the first and gate receives a first level signal sent by the first PAD end, a second input end of the first and gate receives a first control signal, and the first level signal and the first control signal are subjected to phase and processing, and the first level signal is output to the first or gate; the first control signal and the first control signal are high level signals; a first input end of the first OR gate receives a first level signal, a second PAD end defaults to be a high level and ensures that an output end of the first NOT gate is a low level signal through the connection relation of internal nodes, and further ensures that the output end of the first OR gate outputs the first level signal; the input end of the second NOT gate and the input end of the first tri-state gate receive a first level signal sent by the output end of the first OR gate, the second NOT gate inverts the first level signal, and the output end of the second NOT gate outputs an inverted signal of the first level signal to the control end of the first tri-state gate; when the first level signal is a high level signal, the control end of the first tri-state gate is a low level signal, the first tri-state gate is not conducted, the output end of the first tri-state gate does not output a high level signal, and the second PAD end pulls up the set high level signal through the second resistor; when the first level signal is a low level signal, the control end of the first tri-state gate is a high level signal, the first tri-state gate is conducted, the output end of the first tri-state gate is a low level signal, and the second PAD end sets the low level signal.
When the second PAD terminal sends a first level signal to the first PAD terminal: a first input end of the second unidirectional through module receives a second level signal sent by a second PAD end, and a second input end of the second unidirectional through module receives a second control signal sent by a second control end; a second input end of the first unidirectional through module receives a first control signal sent by a first control end; the second PAD end sends a second level signal to the second PAD end through the second unidirectional direct connection module; meanwhile, the second level signal keeps the sending state of the second unidirectional through module through the connection relation of the internal nodes, and interrupts the signal output of the first output end of the first unidirectional through module; the first NOT gate outputs an inverted signal of the first level signal, the first input end of the first AND gate receives the first level signal, the first OR gate outputs a high level signal, the output end of the third NOT gate and the output end of the second NOT gate keep low level, the second OR gate keeps outputting the first level signal, and the output end of the first tri-state gate does not output a signal.
Specifically, a first input end of the second and gate receives a second level signal sent by the second PAD end, a second input end of the second and gate receives a second control signal, and the second level signal and the second control signal are subjected to phase-and processing, and the second level signal is output to the second or gate; the second control signal and the second control signal are high level signals; a first input end of the second OR gate receives a second level signal, a first PAD end is defaulted to be a high level, and the output end of the second NOT gate is ensured to be a low level signal through the connection relation of internal nodes, so that the output end of the second OR gate is ensured to output the first level signal; the input end of the fourth not gate and the input end of the second tri-state gate receive a second level signal sent by the output end of the second or gate, the fourth not gate inverts the second level signal, and the output end of the fourth not gate outputs an inverted signal of the first level signal to the control end of the second tri-state gate; when the second level signal is a high level signal, the control end of the second tri-state gate is a low level signal, the second tri-state gate is not conducted, the output end of the second tri-state gate does not output a high level signal, and the first PAD end pulls up the set high level signal through the second resistor; when the second level signal is a low level signal, the control end of the second tri-state gate is a high level signal, the second tri-state gate is conducted, the output end of the second tri-state gate is a low level signal, and the position of the first PAD end is a low level signal.
In this embodiment:
the first PAD end sends a first level signal to the second PAD end, and the first level signal is set as a high-level digital signal 1: the first control end and the second control end set a high-level digital signal 1, a first AND gate output signal 1, a first OR gate output signal 1 and a second NOT gate output signal 0, the first tri-state gate is closed, the second PAD end keeps a pull-up potential by a second resistor R2, and the second PAD end sets the signal 1, and the transmission is completed; meanwhile, the third not gate outputs a signal 0, the second and gate outputs a signal 1, the second or gate keeps outputting the signal 1, and the first not gate keeps outputting the signal 0; the fourth NOT gate keeps the output signal 0, the second tri-state gate keeps closed, the first PAD is kept transmitting data, and the second PAD is kept receiving data.
The first PAD end sends a first level signal to the second PAD end, and the first level signal is set as a low-level digital signal 0: the first control end and the second control end set a high-level digital signal 1, a first AND gate output signal 0, a first OR gate output signal 0, a second NOT gate output signal 1, a first tri-state gate is conducted, the first tri-state gate outputs a signal 0, and a second PAD end receives a signal 0; meanwhile, the third NOT gate outputs data 1, the second AND gate outputs a signal 0, the second OR gate keeps outputting the signal 1, and the first NOT gate keeps outputting the signal 0; the fourth NOT gate keeps the output signal 0, the second tri-state gate keeps closed, the first PAD is kept transmitting data, and the second PAD is kept receiving data.
The second PAD terminal sends the second level signal to the first PAD terminal according to a single-wire bidirectional direct communication method, which is similar to the process of sending the first level signal to the second PAD terminal by the first PAD terminal, and the first level signal includes a high-level digital signal 1 and a low-level digital signal 0.
In the invention, inside a chip, a first unidirectional through module 1 and a second unidirectional through module 2 are connected through an internal node to form a single-wire bidirectional through communication circuit, signal transmission of the first unidirectional through module 1 and the second unidirectional through module 2 is carried out according to a communication protocol of a processor unit, and the first unidirectional through module 1 and the second unidirectional through module 2 control the bidirectional through communication circuit to be switched on and off through a register unit; in the bidirectional direct communication process, the first PAD end and the second PAD end carry out signal transmission according to a communication protocol and keep the signal sending and receiving conversion states of the first PAD end and the second PAD end; the first PAD end is further connected with the external communication main body, the second PAD end is connected with another chip, and when the external main body is required to be connected with the other chip, bidirectional direct communication can be achieved; when communication is not needed, the first PAD end and the second PAD end are used as common endpoints to transmit signals.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.

Claims (11)

1. The utility model provides a two-way direct communication circuit of single line between PAD inside chip, the chip is inside to include processor unit, communication unit, register unit, first PAD end and second PAD end, its characterized in that: the device comprises a first unidirectional through module and a second unidirectional through module;
the first unidirectional through module is used for the unidirectional transmission of a first level signal from the first PAD end to the second PAD end; the second unidirectional through module is used for the second PAD end to transmit a second level signal to the first PAD end in a unidirectional mode; the first unidirectional through module is connected with the second unidirectional through module through an internal node;
the first unidirectional through module comprises a first input end, a first output end and a first control end; the second unidirectional through module comprises a second input end, a second output end and a second control end;
the first input end is connected with the first PAD end and the second output end, the second input end is connected with the second PAD end and the first output end, and the first control end and the second control end are connected with the register unit.
2. The single-wire bidirectional direct communication circuit between PADs inside a chip as claimed in claim 1, wherein: the processor unit is respectively connected with the communication unit and the register unit;
the processor unit is used for controlling the switches of the communication unit and the register unit during bidirectional communication, is connected with the first unidirectional through module and the second unidirectional through module through the communication unit, and is connected with the first control end and the second control end through the register unit; and the first end of the register unit is connected with the first control end, and the second end of the register unit is connected with the second control end.
3. The single-wire bidirectional direct-communication circuit between PADs inside a chip as claimed in claim 1, wherein: the first unidirectional through module comprises a first AND gate, a first resistor, a first OR gate, a first NOT gate, a second NOT gate and a first tri-state gate;
a first input end of the first AND gate is connected with the first PAD end and the second output end, and a second input end of the first AND gate is connected with a first end of the register unit;
the first end of the first resistor is connected with the first PAD end, and the second end of the first resistor is connected with a direct current power supply;
a first input end of the first OR gate is connected with an output end of the first AND gate;
the input end of the first NOT gate is connected with the second unidirectional through module through the internal node, and the output end of the first NOT gate is connected with the second input end of the first OR gate;
the input end of the second NOT gate is connected with the output end of the first OR gate and the input end of the first tri-state gate;
and the output end of the first tri-state gate is connected with the output end of the second NOT gate and the second PAD end.
4. The single-wire bidirectional direct-current communication circuit between PADs inside a chip as claimed in claim 3, wherein: the second unidirectional through module comprises a second AND gate, a second resistor, a second OR gate, a third NOT gate, a fourth NOT gate and a second tri-state gate;
a first input end of the second AND gate is connected with the first PAD end and the second output end, and a second input end of the second AND gate is connected with a first end of the register unit;
the first end of the second resistor is connected with the second PAD end, and the second end of the second resistor is connected with a direct current power supply;
the first input end of the second OR gate is connected with the output end of the second AND gate;
the input end of the third NOT gate is connected with the first unidirectional through module through the internal node, and the output end of the third NOT gate is connected with the second input end of the second OR gate;
the input end of the fourth NOT gate is connected with the output end of the second OR gate and the input end of the second tri-state gate;
and the output end of the second tri-state gate is connected with the output end of the fourth NOT gate and the first PAD end.
5. The single-wire bidirectional direct-current communication circuit between PADs inside a chip as claimed in claim 4, wherein: the connection relationship of the internal nodes of the first unidirectional through module and the second unidirectional through module is as follows: the output end of the first OR gate is connected with the input end of the third NOT gate, and the output end of the second OR gate is connected with the input end of the first NOT gate.
6. A single-wire bidirectional direct communication method between PADs in a chip is characterized in that: the method is to use the single-wire bidirectional direct communication circuit between PADs in any one of the chips of claim 1 to 5 to perform single-wire bidirectional direct communication, and the method comprises,
in the chip, the processor unit sends a starting instruction of a bidirectional direct communication mode to the communication unit and the register unit according to a communication protocol;
the communication unit receives a starting instruction of a bidirectional direct communication mode and sets the first unidirectional direct communication module and the second unidirectional direct communication module to be in the bidirectional direct communication mode, namely, data transmission and data reception of the first PAD end and the second PAD end follow a communication protocol of a processor unit;
the register unit receives a starting instruction of a bidirectional straight-through communication mode, a first output end of the register unit sends a first control signal to the first control end, and the first control signal is used for controlling the first unidirectional straight-through module to be switched on and switched off; and a second output end of the register unit sends a second control signal to the second control end, and the second control signal is used for controlling the second unidirectional through module to be switched on and off.
7. The method of claim 6, wherein the single-wire bidirectional direct communication between PADs inside the chip is as follows: when two-way direct communication is needed between two PAD terminals, the communication steps are as follows:
according to a communication protocol, the first one-way direct connection module and the second one-way direct connection module allocate the first PAD end and the second PAD end to be in a sending or receiving state according to a signal transmission direction;
when the first PAD end is in a sending state and the second PAD end is in a receiving state: a first input end of the first unidirectional through module receives a first level signal sent by the first PAD end, and a second input end of the first unidirectional through module receives a first control signal sent by the first control end; a second input end of the second unidirectional through module receives a second control signal sent by the second control end; the first PAD end sends a first level signal to the second PAD end through the first unidirectional through module; meanwhile, a first level signal keeps a sending state of a first unidirectional through module through the connection relation of the internal nodes, and the signal output of a first output end of a second unidirectional through module is interrupted;
when the second PAD end is in a sending state and the first PAD end is in a receiving state: a first input end of the second unidirectional through module receives a second level signal sent by the second PAD end, and a second input end of the second unidirectional through module receives a second control signal sent by the second control end; a second input end of the first unidirectional through module receives a first control signal sent by the first control end; the second PAD end sends a second level signal to the second PAD end through the second unidirectional through module; meanwhile, a second level signal keeps a sending state of a second unidirectional through module through the connection relation of the internal nodes, and the signal output of the first output end of the first unidirectional through module is interrupted.
8. The method of claim 7, wherein the single-wire bidirectional direct communication between PADs inside the chip is as follows: when the first PAD end is in a sending state and the second PAD end is in a receiving state:
a first input end of the first AND gate receives a first level signal sent by the first PAD end, a second input end of the first AND gate receives a first control signal, and the first level signal and the first control signal are subjected to AND processing and the first level signal is output to the first OR gate; the first control signal and the first control signal are high level signals;
a first input end of the first OR gate receives a first level signal, a second PAD end defaults to be a high level and ensures an output end of the first NOT gate to be a low level signal through the connection relation of the internal nodes, and further ensures that the output end of the first OR gate outputs the first level signal;
the input end of a second NOT gate and the input end of a first tri-state gate receive a first level signal sent by the output end of the first OR gate, the second NOT gate inverts the first level signal, and the output end of the second NOT gate outputs an inverted signal of the first level signal to the control end of the first tri-state gate;
when the first level signal is a high level signal, the control end of the first tri-state gate is a low level signal, the first tri-state gate is not conducted, the output end of the first tri-state gate does not output a high level signal, and the second PAD end pulls up a set high level signal through a second resistor;
when the first level signal is a low level signal, the control end of the first tri-state gate is a high level signal, the first tri-state gate is turned on, the output end of the first tri-state gate is a low level signal, and the second PAD end sets the low level signal.
9. The method of claim 8, wherein the single-wire bidirectional direct communication between PADs inside the chip is as follows: when the second PAD end is in a sending state and the first PAD end is in a receiving state:
a first input end of the second AND gate receives a second level signal sent by the second PAD end, a second input end of the second AND gate receives a second control signal, and the second level signal and the second control signal are subjected to phase-AND processing and output to a second OR gate; the second control signal and the second control signal are high level signals;
a first input end of the second OR gate receives a second level signal, the first PAD end is defaulted to be a high level, and the output end of the second NOT gate is ensured to be a low level signal through the connection relation of the internal nodes, so that the output end of the second OR gate is ensured to output the first level signal;
an input end of a fourth not gate and an input end of the second tri-state gate receive the second level signal sent by the output end of the second or gate, the fourth not gate inverts the second level signal, and an output end of the fourth not gate outputs an inverted signal of the first level signal to a control end of the second tri-state gate;
when the second level signal is a high level signal, the control end of the second tri-state gate is a low level signal, the second tri-state gate is not conducted, the output end of the second tri-state gate does not output a high level signal, and the first PAD end pulls up a set high level signal through a second resistor;
when the second level signal is a low level signal, the control end of the second tri-state gate is a high level signal, the second tri-state gate is turned on, the output end of the second tri-state gate is a low level signal, and the position of the first PAD end is a low level signal.
10. The method of claim 9, wherein the single-wire bidirectional direct communication between PADs inside the chip is as follows:
when the first PAD end starts to send a first level signal to the second PAD end: the first input end and the second input end of the second AND gate are high level and output high level signals; the second OR gate outputs a high level signal, and the output end of the third NOT gate is at a low level;
when the first PAD terminal sends a first level signal to the second PAD terminal: the third not gate outputs an inverted signal of the first level signal, the first input end of the second and gate receives the first level signal, the second or gate outputs a high level signal, the output end of the first not gate and the output end of the fourth not gate keep low level, the first or gate keeps outputting the first level signal, and the output end of the second tri-state gate does not output a signal.
11. The method of claim 10, wherein the single-wire bidirectional direct communication between PADs inside the chip is as follows:
when the second PAD end starts to send a second level signal to the first PAD end: the first input end and the second input end of the first AND gate are high level and output high level signals; the first OR gate outputs a high level signal, and the output end of the first NOT gate is at a low level;
when the second PAD end sends a first level signal to the first PAD end: the first not gate outputs an inverted signal of a first level signal, the first input end of the first and gate receives the first level signal, the first or gate outputs a high level signal, the output end of the third not gate and the output end of the second not gate keep low level, the second or gate keeps outputting the first level signal, and the output end of the first tri-state gate does not output a signal.
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