CN118838241B

CN118838241B - GPIO pin control system, monitoring method and single-wire communication method

Info

Publication number: CN118838241B
Application number: CN202411319534.0A
Authority: CN
Inventors: 陈越; 仲原立; 周宽裕
Original assignee: Quanzhou Archie Technology Co ltd
Current assignee: Quanzhou Archie Technology Co ltd
Priority date: 2024-09-23
Filing date: 2024-09-23
Publication date: 2024-12-27
Anticipated expiration: 2044-09-23
Also published as: CN118838241A

Abstract

The application relates to the field of communication, in particular to a GPIO pin control system, a monitoring method and a single-wire communication method. The system comprises an input branch, an output branch, an IO pin and a processor, wherein the output branch comprises an output data register, the IO pin is set to be in an open-drain output mode, the processor is used for monitoring data of the IO pin in real time through the input branch when the IO pin is in an idle state, when the IO pin is monitored to be in a specific level, the processor judges that external equipment requests to send the data and sends a fixed value to the output data register so that the IO pin is in a receiving state, and when the processor needs to send the data, the processor directly sends the data to be output to the output data register so that the IO pin is in an output state. The application utilizes the special design inertia of the existing GPIO circuit, does not add any functional circuit, improves the communication efficiency and the utilization rate of pin resources, and is suitable for the design of consumer electronic products sensitive to price and cost.

Description

GPIO pin control system, monitoring method and single-wire communication method

Technical Field

The application relates to the field of embedded system and singlechip communication, in particular to a GPIO pin control system, a monitoring method and a single-wire communication method.

Background

GPIO (General-Purpose input/output) communication is a common communication mode in embedded systems and single-chip computers, and the basic principle is to transmit data by controlling the level of a single GPIO pin. These pins may be dynamically configured by the program as inputs or outputs and their state may be controlled by software. Such communication schemes are widely employed in a variety of applications including, but not limited to, sensor data acquisition, device control, peripheral device communication, and the like. Because of its simple and flexible characteristics, GPIO single-wire communication is an important communication mode in many embedded systems.

For conventional GPIO pins, a single GPIO pin can only be set to either an input or output state. Thus, a single GPIO pin can only be either an input pin or an output pin. The single GPIO pin also provides the function of switching between input and output states, but the CPU is required to output a plurality of instructions for switching, so that the switching efficiency is low. Therefore, in a scenario where two communication parties need to frequently send information to each other, GPIO communication generally needs to set two data lines, namely, a data line (MOSI) from a master device to a slave device and a data line (MISO) from a slave device to a master device. Correspondingly, the single chip microcomputer on the master device and the slave device needs to be occupied with two GPIO pins respectively, set to be in an input state and an output state respectively and are connected with the two data lines respectively.

However, the pin resources of the singlechip are very short, and in order to realize enough functions, the use of each pin needs to be compactly designed. If the data communication occupies too many pins, other control functions are easy to cause idle pins which are not enough to be used, or a singlechip with more pins but higher cost must be purchased.

In addition, the occupation of more pins means that more interconnect wires are required, which significantly increases the circuit board routing space and increases signal interference between wires, and requires more circuit board space and more complex process technology to reduce signal interference, thereby significantly increasing costs. Meanwhile, too many wires between communication devices are also cost, and the possibility of being interfered by the outside and the interference to the outside are increased.

The above problems are particularly pronounced in consumer electronics designs that are price sensitive. Therefore, a new GPIO communication protocol is needed to provide a more flexible and efficient manner of inter-device communication.

Aiming at the related technology, the inventor considers that four wires are needed for the SPI protocol, too many GPIO pins of the equipment are occupied, a common single-wire communication protocol needs a CPU to output a plurality of instructions, the input and output modes of the pins are frequently switched, the efficiency is low, the speed is low, and the functions of the input part circuit are idle, the GPIO output part circuit is not effectively utilized and the resource is wasted when the GPIO output part circuit works.

Disclosure of Invention

In order to reduce the number of GPIO pins required, and the GPIO pins do not need to switch input and output states during receiving and transmitting, so that a collision detection communication protocol is simple and efficient, the application provides a GPIO pin control system, a monitoring method and a single-wire communication method.

In order to solve the above problems, the present application provides a GPIO pin control system, a monitoring method and a single-wire communication method.

In a first aspect, the present application provides a GPIO pin control system.

A GPIO pin control system comprises an input branch circuit, an output branch circuit, an IO pin, a processor and a fixed value, wherein the input branch circuit is used for monitoring and checking a value corresponding to a level on a GPIO pin and is used for receiving input data, the output branch circuit is used for controlling data output, the output branch circuit comprises an output data register which is used for storing data sent by a processor, the IO pin is connected to an output end of the output branch circuit and an input end of the input branch circuit and is used for being connected to external equipment, the IO pin is set into an open-drain output mode, the processor is used for monitoring the data of the IO pin in real time through the input branch circuit when the IO pin is in an idle state, the output branch circuit is used for judging that the external equipment requests to send data when the IO pin is in a specific level, and sending the fixed value to the output data register, and when the processor needs to send the data, the IO pin is directly sent to the output data register, and is in an output state.

Further, when the IO pin is monitored to be at the low level, the external device is judged to request to send data.

Further, the processor is further configured to monitor, in real time, whether data output by the output branch is correct through the input branch when the IO pin is in an output state, and if not, determine that a data collision occurs with the external device.

The input branch circuit further comprises an input driving module, an input data register and an output controller, wherein the input driving module is used for converting the level state received by the IO pin into a numerical value, the input data register is used for storing the numerical value corresponding to the level state processed by the input driving module, the output branch circuit further comprises the output controller which receives and outputs the level state converted by the numerical value stored in the output data register according to the open-drain output mode, and the NMOS transistor is used for receiving and opening and closing according to data output by the output controller.

Further, the step of monitoring whether the data output by the output branch circuit in real time comprises the steps that the processor reads the data in the input data register in real time and compares the data with the data to be output by the output branch circuit, whether the data are consistent or not is judged, if the data are consistent, the data are correct, the data are continuously transmitted, if the data are not consistent, the data are incorrect, and the data are judged to have data conflict with the external equipment.

Further, when the transmitted data to be output sent to the output branch by the processor is inconsistent with the data in the input data register, the processor stops sending the data to the output branch and reads the data in the input data register in real time.

Further, the real-time monitoring of the data of the IO pin through the input branch comprises the steps of storing the current state of the IO pin, reading the data in the input data register, and monitoring the data of the IO pin by the processor according to the data, wherein the monitoring result is combined with the stored current state of the IO pin by the data of the IO pin to make a common decision.

Further, the step of storing the current state of the IO pin comprises the steps of storing the current pin output state of the IO pin, controlling the output branch to output a high-resistance state, reading the actual level of the external equipment on the IO pin and storing the actual level into the input data register, and recovering the state of the IO pin to the stored current state.

In a second aspect, the present application provides a monitoring method based on a GPIO pin control system.

A monitoring method based on a GPIO pin control system comprises the steps of setting an IO pin to be in an open-drain output mode, when the IO pin is in an output state, reading data of an input branch in real time by a processor, comparing the data with data sent to the output branch, judging whether the data are consistent, if so, continuing to send the data, if not, otherwise, judging that the data conflict with external equipment occurs.

In a third aspect, the present application provides another monitoring method based on a GPIO pin control system.

A monitoring method based on a GPIO pin control system comprises the steps of setting an IO pin to be in an open-drain output mode, reading data in an input data register when the IO pin is in an idle state, monitoring the data of the IO pin in real time, judging that an external device requests to send data when the IO pin is in a specific level, sending a fixed value to the output data register to enable the IO pin to be in a receiving state, and directly sending data to be output to the output data register when the processor needs to send the data to enable the IO pin to be in an output state.

In a fourth aspect, the present application provides a GPIO single-wire communication method.

A GPIO single-wire communication method includes that sender and receiver both include GPIO pin control system, and sender and receiver's IO pin is connected through a wire.

The sending method comprises the steps of setting a circulation timer, outputting a specific level by an output branch of a sender for sending a signal entering an output state when data transmission is requested, entering an interrupt program by the sender when the circulation timer is triggered after timing is finished, monitoring the level on an IO pin, switching the IO pin to output a high level if the low level is read, polling the level on the IO pin, and entering a data transmission stage if the high level is read.

The receiving method comprises the steps of setting a circulation timer, enabling a receiving party to enter an interrupt program when the timing of the circulation timer is ended and to monitor the level on an IO pin, indicating that the receiving party enters a transmitting state if the level is read to be low, switching an output branch to output the low level, setting a single timer, outputting a high level when the timing of the single timer is ended and triggering, and entering a data receiving stage.

In summary, the application uses the special design inertia of the existing GPIO circuit, does not add any functional circuit, designs the communication protocol autonomously, is realized by pure software, skillfully solves the problems of low efficiency and waste of pin resources of the traditional GPIO, obviously improves the communication efficiency and saves the GPIO pin resources by using the GPIO single-wire communication method, and is suitable for application scenes with shortage of pin resources. The processor can monitor the data of the IO pins in real time, including the state of external equipment and the correctness of output data, so that the running reliability of the system is ensured. The monitoring method and the single-wire communication method simplify the design and implementation process, and are convenient to integrate and apply in an embedded system. By monitoring and controlling data transmission in real time, communication failure caused by data errors is reduced, and reliability, stability and high efficiency of the system are improved. In addition, because the system has lower requirement on hardware resources, the system is suitable for the design of price-sensitive consumer electronic products, thereby reducing the overall cost. In addition, the application sends a fixed value (such as a mode of setting 1) to the output data register to enable the IO pin to be in a receiving state, or directly sends data to be output to the output data register to enable the IO pin to be in an output state, so that a mode register is not required to be set for switching between the receiving state and the output state, and the method is simple, quick and efficient.

Drawings

FIG. 1 is a block diagram of a GPIO pin control system of the present application;

FIG. 2 is a flow chart for verifying whether an input branch and an output branch of a GPIO pin can operate in parallel;

FIG. 3 is a block diagram of a system architecture for dual devices using GPIO pins for single-wire communication;

FIG. 4 is a flow chart of a GPIO single-wire communication handshake;

FIG. 5 is a main flow chart of GPIO single-wire communication;

FIG. 6 is a flow chart of a timer interrupt function for GPIO single wire communication;

FIG. 7 is a flow chart of the GPIO single wire communication to save the current state of the IO pin;

FIG. 8 is a graph showing the actual level relationship between the output state of the drain of the NMOS transistor and the IO pin in the respective output branches of A, B devices;

FIG. 9 is a flowchart of an alternative timer interrupt function for GPIO single wire communications;

Fig. 10 is a flow chart of a newly built receiving line for GPIO single line communication.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the drawings of the specification, but the embodiments should not be construed as limiting the application.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a GPIO pin control system according to the present application. The GPIO pin control system includes an input branch 101, an output branch 102, an IO pin 103, and a processor 117, and the IO pin 103 is connected to an output terminal of the output branch 102 and an input terminal of the input branch 101, and is used for connection to an external device.

The output branch 102 includes an output data register 104 and an output driver module 106. The output data register 104 and the output driving module 106 are sequentially connected in series between a processor 117 and the IO pin 103 of the device, and the processor 117 of the device may be, for example, a CPU (central processing chip). The output data register 104 is used for storing output data sent by the processor, and the output driving module 106 is used for outputting high and low levels according to the data in the output data register 104.

The output data register 104 receives data to be output from the processor 117 and also receives data from the bit set/clear register. The processor 117 may read the contents of the output data register 104 to obtain the last write data value and the bit set/clear register 116 is used to operate on a certain port (bit) of the output data register 104. The output driving module 106 includes an output controller 108, and a PMOS transistor 109 and an NMOS transistor 110 (MOS: abbreviation of MOSFET, refer to metal-oxide semiconductor field effect transistor) controlled by the output controller 108. One end of the source of the PMOS transistor 109 is connected to the positive power supply VDD, the other end is connected to the IO pin 103, the gate is connected to the output terminal of the output controller 108, and one end of the source of the NMOS transistor 110 is connected to the negative power supply VSS, the other end is connected to the IO pin 103, and the gate is connected to the output terminal of the output controller 108. The output controller 108 determines the output mode according to the mode bit in the configuration register, and controls the gate voltages to be output to the PMOS transistor 109 and the NMOS transistor 110 according to the output data in the output data register 104. The NMOS transistor 110 is turned on at a high level and turned off at a low level to control the conduction with VSS, and the PMOS transistor 109 is turned on at a low level and turned off at a high level to control the conduction with VDD (as described below, the PMOS transistor 109 remains non-conductive in the open drain output mode). The data in the output data register 104 is output through the IO pin 103 through the above steps.

The input branch 101 comprises an input data register 105 and an input drive module 107. The input data register 105 and the input driving module 107 are sequentially connected in series between the processor 117 and the IO pin 103, and the input driving module 107 is configured to input data received by the IO pin 103 into the input data register 105 according to the high-low level of the IO pin 103. The input data register 105 is used to store received input data for reading by the processor 117.

The input drive module 107 includes a schmitt trigger 111, a pull-up resistor R1, and a pull-down resistor R2. The schmitt trigger 111 is used for converting the analog signal received by the IO pin 103 into a digital signal. Pull-up resistor R1 is connected to positive power supply VDD through switch K1 and pull-down resistor R2 is connected to negative power supply VSS through switch K2. With the switch K1 and the switch K2 opened or closed, the pull-up resistor R1 and the pull-down resistor R2 can limit the normal potential of the IO pin 103 to a high level or a low level.

The processor 117 includes a monitoring module 118, configured to monitor, in real time, data of the IO pin through the input branch when the IO pin is in an idle state, where when it is monitored that the IO pin is at a specific level, it is determined that the external device requests to send the data. For example, when the IO pin is monitored to be at a low level, it is determined that the external device requests to send data, and it can be understood that the specific level may be a high level, that is, both the high level and the low level are within the protection scope of the present application.

The processor 117 then sends a fixed value to the output data register (e.g., send data 1 to the output data register, set the output data register directly to 1, or send data 0 to the output data register, output low, pull down directly), pull down is a handshake, and pull down again when a single timer triggers, then the high impedance state is enabled, which can only receive data.

So that the NMOS is in an off state, the IO pin floats to be in a high-resistance state, and the IO pin is in a receiving state. When the processor needs to send data, the data to be output is directly sent to the output data register (without any input/output state instruction), and the data controls the NMOS to switch between on and off states so that the IO pin is in an output state and can switch between a high level and a low level to output data 0 or 1. When the IO pin is in an output state, the processor 117 monitors whether the data output by the output branch is correct or not in real time through the input branch, and if the data output by the output branch is incorrect, the processor determines that the data conflict occurs with the external equipment. This monitoring module 118 may be a set software program or a physical module in a circuit.

When GPIO single-wire communication is adopted, it is quite easy to think that a time division multiplexing method is adopted to realize single-wire communication by switching an input mode and an output mode, but when data is transmitted and received in the method, the input mode or the output mode of a pin needs to be frequently switched, and when the input mode or the output mode is switched each time, a plurality of instructions are consumed by a CPU, so that the efficiency is low and the switching speed is low. The method is combined with the method for monitoring the IO pin data on the basis of the time division multiplexing method, the IO pin can be in a receiving state only by setting the output data register to 1, or the data to be transmitted is directly transmitted to the output data register, the IO pin can be in the output state without any instruction, or the IO pin can be in an idle state when the IO pin data is unchanged for a long time (for example, a fixed value is set) in the receiving state, or the IO pin can be in the idle state after the output is finished in the output state, so that the switching among various states of the IO pin does not need instructions (only the output data register is set to 1 when the switching is in the receiving state), a plurality of instructions can be saved, the response speed is improved, the communication delay is reduced, the redundancy is reduced, and meanwhile the communication efficiency is improved. In addition, in the related art, as the GPIO output branch circuit works, the function of the input branch circuit is idle, the input branch circuit is not effectively utilized, and resources are wasted.

As can be seen from the circuit of fig. 1, the input data register 105 and the output data register 104 are independent, which means that the processor 117 can read data from the input data register 105 at the same time when outputting data to the output data register 104, and the two sets of circuits of the input branch 101 and the output branch 102 are parallel. The input branch 101 and the output branch 102 are converged to the same IO pin 103 on the right side of fig. 1, and the input level and the output level are the same at the IO pin 103, and no switch is used for controlling unidirectional conduction, so that it is judged that the input branch 101 and the output branch 102 can work in parallel on the physical connection.

Fig. 2 is a flowchart for verifying whether the input branch and the output branch of the GPIO pin can operate in parallel.

The GPIO pin has a plurality of working modes, wherein one mode is an open-drain output mode. When the GPIO pin is configured into an open-drain output mode, the PMOS transistor is not conducted, and the NMOS transistor works in a conducting state or a non-conducting state under the control of the output controller, so that the GPIO pin outputs a level of a certain voltage. The specific communication procedure is as follows. The processor stores the data to be output into an output data register, the output data register outputs the data to an output controller, the output controller receives and outputs the level state (low level and high resistance state) converted by the numerical value of the output data register according to the open-drain output mode, namely, the output mode is judged to be the open-drain output mode according to the configuration register, and the on/off of the NMOS transistor is controlled by outputting different voltages so as to control the level of GPIO output. When the value in the output data register is 1, the controller outputs a low level, so that the gate voltage of the NMOS transistor is low, the NMOS transistor is not conductive, the GPIO pin is in a high resistance state, and it is possible to output a high level generated by the pull-up resistor and also possible to output a low level determined by external equipment, and when the value in the output data register is 0, the controller outputs a high level, the NMOS transistor is conductive, and the GPIO pin outputs a low level determined by VSS.

In general purpose GPIO design, an input signal is input through an IO pin, a received analog signal is converted into a digital signal through a Schmitt trigger and is sent to an input data register, the digital signal is sent to an output controller through an output data register, and the output data register controls the conduction of an NMOS transistor to generate an output signal and outputs the output signal to the IO pin. Thus, the input data register and the output data register are connected with the IO pin on the logic circuit, and the data in the input data register is consistent with the data in the output data register under the condition of no external signal.

To see if the processor can read the value of the GPIO output data register through the GPIO input data register in the open drain output mode, the inventors devised the following method for verification. Using the constant CH32V208WBU8 evaluation board, using GDB (GNU Debugger) debug, easy operation was possible in IDE memory windows. The specific operation comprises the following steps:

S100, setting an LED indicator lamp, wherein one pin of the indicator lamp is connected with a positive power supply through a current limiting resistor, the other pin of the indicator lamp is connected with one PAO pin of a constant CH32V208WBU8 chip on an evaluation board, and the voltage output by the PA0 is high or low and is determined by the end value in an input data register 0x4001080 c. The PA0 pin outputs a low level when the end value in the input data register 0x4001080c is 0, and outputs a high level when the end value in the input data register 0x4001080c is 1.

S200, configuring GPIO pins of the chip into an open-drain output mode. In a general understanding, in this mode, the output branch is active, the input branch is inactive or the operating state is unknown.

S300, reading GPIOA INDR the last position of the output data register to be 0, and checking whether the zero bit is 0. At this time, the LED1 is turned on. Wherein GPIOA OUTDR is the value of the output data register and GPIOA INDR is the value of the input data register.

S400, reading GPIOA INDR the last position of the output data register to be 1, and checking whether the zero bit is 1. At this time, the LED1 is turned off.

S500, the last bit of the output data register is set to 0 again, GPIOA INDR is read out, and whether the zero bit is 0 is checked. At this point the LED1 is again on.

As can be seen from the above procedure, the GPIO pin is set to the output mode instead of the input mode, but the pin level can still be correctly read from the input data register. This means that at least in the open drain output mode, the input circuit and the output circuit are operated in parallel, and even though seemingly configured in the output mode, the input circuit is still functioning and can be used normally. This provides the possibility for the same GPIO port to be used as both an input port and an output port. The system described below in which the dual devices communicate using GPIO pins can be designed in this way.

Fig. 3 is a block diagram of a system in which two devices communicate using GPIO pins, and the present application takes the two devices communication as an example, and those skilled in the art can modify the two devices communication into multi-device communication according to needs, and the modification process does not need to take creative effort. As shown in fig. 3, the GPIO pin control system of the present application is used for both device a and device B. Only one GPIO pin is used for data communication between device a and device B, respectively. The GPIO pins of both devices are configured in an open drain output mode. And a pull-up resistor R3 is configured between IO pins of the device A and the device B, and the pull-up resistor R3 can be arranged on the device A or the device B.

The following describes how device a and device B achieve single-wire communication via GPIO pins when using the open drain output mode.

When neither device a nor device B outputs data, the output data registers 311,321 are both set to 1, the output controller 312 outputs a low level to the gate of the NMOS transistor 313, the output controller 322 outputs a low level to the gate of the NMOS transistor 323, at this time, neither NMOS transistor 313,323 is turned on, and the IO pin 301 level is a high level determined by the pull-up resistor R3.

When the device a needs to output data and the device B does not output data, the device a stores the data 1 into the output data register 311, the output controller 312 outputs a high level to the gate of the NMOS transistor 313 according to the data 1 in the output data register 311, the NMOS transistor 313 is not turned on, the IO pin 301 is a high level determined by the pull-up resistor R3, and when the device a outputs the data 0, the device a stores the data 0 into the output data register 311, the output controller 312 outputs a low level to the gate of the NMOS transistor 313 according to the data 0 in the output data register 311, the NMOS transistor 313 is turned on, and the IO pin 301 is a low level determined by VSS.

It can be understood that, at this time, the device a is a sender, the monitoring module 118 monitors whether the output data of the processor through the output branch is correct in real time, in the device a, the input branch receives the level of the IO pin 301 through the input driving module in real time and stores the level into the input data register, the processor reads the data in the input data register in real time and compares the data with the data to be output sent to the output branch (specifically, the processor reads the data in the input data register in real time and compares the data with the data to be output already output by the output branch), whether the data is consistent is judged, if the data is consistent, the data is correct, and if the data is not consistent, the data is incorrect. When the data sent by the processor to the output branch is consistent with the data in the input data register, the communication is normal, and the operation can be continued, and when the data sent by the processor to the output branch is inconsistent with the data in the input data register, the data conflict is judged to occur with the equipment B (an example of external equipment), the external equipment needs to send information at the moment, the processor stops sending the data to the output branch, and the data in the input data register is read in real time (or the data is solved according to other collision solutions, and particularly, the detection and the solution of the collision are described in detail later). For example, when the data sent by the processor of the device a to the output branch is1 and the data in the real-time read input data register is also 1, normal operation is continued, and when the data sent by the processor of the device a to the output branch is1 and the data in the real-time read input data register is 0, if the data is inconsistent, it is indicated that the device B sends a low level signal at this time, and there may be a data output requirement, the processor of the device a may stop sending data to the output branch and be switched from the sender to the receiver, and the data in the input data register is read in real time.

It can be understood that, correspondingly, when the device a is a sender, the device B is a receiver, the monitoring module 118 monitors the status of the device a (an instance of an external device) at the IO pin 103 in real time, in the device B, after the current status of the IO pin is stored, the data in the input data register is read, and the processor monitors the data of the IO pin accordingly, where the monitored result is commonly determined by the current status of the IO pin stored by the data combination of the IO pins, for example, if the data of the IO pin is 0 and the stored current status of the IO pin is 1, the monitored result is that the device a makes a sending request, and if the data of the IO pin is 1 and the stored current status of the IO pin is 0, the monitored result is that the device B makes a sending request by itself. The main function of storing the current state of the IO pin is to store the existing output state and restore the existing output state after monitoring, which comprises the following steps of: storing the current pin output state of the IO pin, controlling the output branch to output a high-resistance state, reading the actual level of the external equipment in the IO pin and storing the actual level into an input data register, and recovering the state of the IO pin to the current pin output state. When the device B has a data transmission requirement and needs to be converted into a sender by a receiver, a continuous low-level requirement signal can be sent out by an output branch to remind the device A of being converted into the receiver.

It can be understood that when the device a and the device B do not establish connection, the IO pins of the device a and the device B are in an idle state, that is, the idle state indicates a state in which no link is established and no link is established, a monitoring module in the device a is used for monitoring the state of the device B at the IO pin in real time, a monitoring module in the device B is used for monitoring the state of the device a at the IO pin in real time, so that communication connection can be successfully completed when any party initiates a connection establishment task, and when the device a and the device B have established connection, for example, the device a is a sender, and the device B is a receiver, the monitoring module in the device a is used for monitoring whether output data of the processor through the output branch is correct in real time, and the monitoring module in the device B is used for receiving information sent by the device a in real time.

Similarly, when device B needs to output data and device a does not output data, the communication process is similar to that described above.

When the device a outputs data first and the device B outputs data later, that is, the device B has a need to transmit data, the device a needs to be converted from the receiving side to the transmitting side. For example, when the device a outputs the data 1 first, the device a stores the data 1 into the output data register 311, the output controller 312 outputs a high level to the gate of the NMOS transistor 313 according to the data 1 in the output data register 311, and at this time, the NMOS transistor 313 is not turned on, and the IO pin 301 is at a high level determined by the pull-up resistor R3. At this time, the device B outputs the data 0, the device B stores the data 0 into the output data register 321, the output controller 322 outputs a low level to the gate of the NMOS transistor 323 according to the data 0 in the output data register 321, at this time, the NMOS transistor 323 is turned on, and the IO pin 301 level is a low level determined by VSS. At this time, when the data sent by the processor of the device a to the output branch is 1 and the data in the real-time read input data register is 0, and the data is inconsistent, it is indicated that the device B sends a low-level signal at this time, and there may be a data output request, and the processor of the device a may stop sending data to the output branch and turn from the sender to the receiver, and read the data in the input data register in real time, or other solutions such as a mechanism of collision detection and a solution of collision are described in detail below.

Similarly, when the device B outputs data first and the device a outputs data later, the communication process is similar to that described above.

Fig. 4 is a single-wire communication handshake flow chart of the dual-device GPIO, and fig. 5 and 6 are a main flow chart of the single-wire communication of the dual-device GPIO and a timer interrupt function flow chart. As shown in fig. 4, 5 and 6, the steps of establishing connection by two-way handshake of the dual device are as follows:

and (1) establishing an idle link state, wherein when the equipment A and the equipment B do not send data, the setting pin outputs a high-resistance state, the output data register of the GPIO output circuit is set to be data 1, and the two NMOS transistors are not conducted. At this time, the GPIO pin for single line communication is subjected to the action of a weak pull-up resistor, outputting a high level. The handshake state is set to 0. The handshake state is used to determine the extent to which the handshake connection is being made. At this time, after the system is initialized, the device A and the device B processors are respectively provided with a circulation timer with fixed intervals, the fixed intervals of the two devices can be inconsistent, the timers repeatedly trigger interruption, and the interruption program is executed to execute a process comprising the steps of reading an input data register and judging whether an IO pin is low level (namely, the device A and the device B respectively monitor the state of an external device at the IO pin in real time). The periodic inquiry process has extremely short duration, and the duration is the level which can be correctly read to pull-down of the B machine, so that the execution time of a processor is basically not consumed. The fixed time between the two inquiry intervals is long, and is usually set to be in the order of milliseconds or seconds, depending on the demands for transmission delay. As shown in fig. 6, the interrupt routine in the idle connection state is as follows.

It can be understood that the current state flow of saving the IO pin may be specifically a method, as shown in fig. 7, of saving the pin state at this time, then setting the output data register value to 1, the nmos transistor is not turned on, the GPIO pin floats to be in a high-resistance state, at this time, the pin state is read in, and after the reading is completed, the pin is restored to the state saved before the interrupt triggering. At this time, judging the pin level read in the current state flow of the IO pin, if the state at the IO pin is monitored to be high level, indicating that no hand-extending signal of the opposite side is received (the opposite side does not want to send data), then judging whether the IO pin is in the handshake state 2, if the IO pin is not in the handshake state 2, exiting the interrupt program, returning to the interrupted original other programs, and continuing to run downwards. At this time, when the device a or the device B has not only the arrival interval time, but also other non-GPIO communication programs are still executed at other times except for the signal of monitoring the other party by triggering the interrupt execution once, and the interrupt program does not consume the execution time of the processor basically.

As shown in fig. 8, in the GPIO open drain output mode of both communication parties, the output state of the NMOS transistor drain of the output circuit and the actual level relationship between the two IO pins and the metal connection therebetween are as follows.

If one output data register is set to 1, the drain of the NMOS transistor of the output circuit floats, and the output is not necessarily 1 in the high-resistance state, depending on the external weak pull-up and the other side. If the opposite NMOS transistor is conducted, the drain electrode is grounded, the pull-up resistor bears all voltage difference between a power supply and the ground, and the metal pins and the metal wires between the two metal pins are both in low level.

If one output data register is set to 0, the NMOS transistor of the output circuit is conducted, the drain electrode is grounded, the pull-up resistor bears all the voltage difference between the power supply and the ground, and the metal pins of the two parties and the metal connection wire between the two parties are low level no matter the output state of the drain electrode of the NMOS transistor of the other party is conducted or high resistance.

In step (2), the sender stretches his hand, as shown in fig. 4 and fig. 5, when the device a is about to send data, the pin outputs a specific level, and it can be understood that the specific level may be a low level or a high level, so long as the information informing the external device to initiate stretching can be realized. Specifically, the output data register value of the device a is set to 0, the output controller of the device a outputs a high level to the gate of the NMOS transistor of the device a according to the data 0 in the output data register of the device a, at this time, the NMOS transistor of the device a is turned on, the drain is grounded, the pin outputs a low level, and a signal is sent to the device B, and meanwhile, the handshake state is changed to 1.

In step (3), the receiver handshakes, as shown in fig. 4 and 6, when the device B cycles the timer to reach the interval time, an interrupt is triggered, and the cycle timer interrupt program is executed. After the device B performs the current state flow of the IO pin, the data in the input data register is read, if the data is 0, namely, when the device B monitors that the state of the device A at the IO pin is at a low level, the device A monitors that a first hand-extending signal sent by the device A is detected, the device A needs to send data, the handshake state is changed to 2, and the combined state of the handshake of the receiving party and the hand-extending of the receiving party is indicated.

And (4) the receiver stretches the hand, as shown in fig. 4 and 6, after the handshake state of the equipment B is changed to 2, setting the output data register value of the equipment B to 0, and outputting a high level to the grid electrode of the NMOS transistor in the equipment B by the output controller of the equipment B according to the data 0 in the output data register of the equipment B, wherein the NMOS transistor in the equipment B is conducted at the moment, the drain electrode is grounded, the pin outputs a low level, and a hand stretching signal is sent to the equipment A. Then, the device B newly establishes a single timer, and the time interval is slightly longer than the time of the timer set by the device A in the step (1) (specifically, the time interval is longer, and the device A can accurately receive a second hand-extending signal after responding to the interrupt program). Before the single timer time arrives, the device B processor runs other programs, and the interrupt program does not consume processor execution time.

In step (5), the sender handshakes, as shown in fig. 4 and 6, when the device a cycles the timer to reach the interval time, an interrupt is triggered, and a cycle timer interrupt program is executed. After the device a performs the current state flow of saving the IO pin, the data in the input data register is read, and if the data is 0, it is monitored that the state of the device B at the IO pin is low level (at this time, the device B outputs the data register to be set to 0). At this time, the device a receives the hand-extension signal responded by the device B, that is, the handshake of the sender is successful, and the device a changes the handshake state to 3.

And (6) the sender pulls the hand, as shown in fig. 4 and 6, after the device A changes the hand holding state to 3, the output data register is set to 1, the drain of the NMOS transistor is opened, the IO pin is in a high-resistance state and floats, and the low level is not output any more. At this point device a withdraws the reach, i.e., the sender drawer. And closing the circulation timer, starting uninterrupted polling of whether the input data register is 1, and waiting for the hand of the receiver. When the device A polls the input high level, the handshake state is changed to 5, which means that the receiver takes out the handshake, and the data is sequentially sent according to the start bit, the data bit, the check bit and the stop bit of the serial communication protocol. When each bit of data is sent, the data in the input data register is read in real time, the data is the output data of the output branch, the processor compares the data sent to the output branch with the output data of the output branch, and judges whether the data input by the processor is consistent with the output data of the output branch. After the transmission is completed, the pin state is changed into a high-resistance state, and the handshake state returns to the initial state 0.

Step (7) has two different designs, hereinafter referred to as a first design and a second design, respectively.

In the first design scheme, the receiver pulls the hand, as shown in fig. 4 and fig. 6, when the single timer time interval of the device B arrives, the device B triggers the interrupt, and executes the cycle timing interrupt program. And after the device B performs the current state flow of the IO pin, reading the data in the input data register. At this time, the monitored data is 1, that is, the state of the device A at the IO pin is monitored to be high level, and if the handshake state is judged to be 2, the output data register is set to be 1, the drain of the NMOS transistor is opened, the IO pin is in a high-resistance state and floats, and the low level is not output any more. At this time, the device B withdraws the extension hand, changes the hand holding state to 4, and changes the pin output high resistance state, namely the receiving party draws the hand. And then the processor of the equipment B stops running other programs and is focused on repeatedly reading and processing the values of the input data registers, namely, the state of the equipment A at the IO pin is monitored in real time, and at the moment, the single-wire communication program is exclusively executed by the processor to read and store data. When the continuous high level is received, the opposite side is indicated to be sent completely, and the state of the change handshake returns to the initial state 0.

In the second design scheme, the receiver pulls the hand, as shown in fig. 4 and fig. 9, when the single timer time interval of the device B arrives, the device B triggers the interrupt, and executes the cycle timing interrupt program. And after the device B performs the current state flow of the IO pin, reading the data in the input data register. At this time, the monitored data is 1, that is, the state of the device A at the IO pin is monitored to be high level, and if the handshake state is judged to be 2, the output data register is set to be 1, the drain of the NMOS transistor is opened, the IO pin is in a high-resistance state and floats, and the low level is not output any more. At this time, the device B withdraws the extension hand, changes the hand holding state to 4, and changes the pin output high resistance state, namely the receiving party draws the hand. Then, the device B creates a data receiving thread, as shown in fig. 10, for repeatedly reading and processing the value of the input data register, where the data receiving thread and other threads execute in a multithreaded manner, and when reading and storing data, the data receiving thread may also perform a data transmission process or other non-GPIO communication programs. When the continuous high level is received, the opposite side is indicated to be sent completely, and the state of the change handshake returns to the initial state 0.

In the second scheme, the receiver performs multi-threaded operation when receiving data, so that the receiving is not completed but data needs to be transmitted. At this time, the original receiver and the original sender send data at the same time, which causes confusion of communication, and a mechanism for collision detection and a solution for collision need to be formulated. The solution to the collision is as follows.

Firstly, whether collision occurs in the communication process or not needs to be detected. In the data receiving and transmitting stage of the equipment A and the equipment B, the data received by the input branch circuit at the moment is monitored and compared with the data to be output, and if the data are inconsistent, the collision is judged.

After collision and detection of the collision, the solution of the collision should be performed. For example, the device a and the device B may generate random numbers as delay durations, so that the delay durations of the two parties are inconsistent, thereby avoiding data from being simultaneously transmitted again.

After the collision detection and the collision resolution are performed, in the normal data transceiving process, when the receiving party needs to send high-priority data, for example, when the receiving party needs to send information related to communication control. The information related to the communication control comprises an ACK frame (acknowledgement frame, representing that the receiving party has received the data) returned to the sending party, confirming the received data, and releasing the memory for the space occupied by the confirmed received data in the buffer zone of the retransmission mechanism according to the ACK frame and the acknowledgement frame, wherein when the buffer zone of the receiving party is full or the data processing capacity of the receiving party is insufficient, the receiving party sends a request to request the sending party to reduce the speed or when the pressure of the receiving party is relieved, the sending party is requested to increase the speed. At this time, the following two solutions are set.

The first solution is that the receiving party and the sending party multiplex a single signal wire in a time-sharing way, and the receiving party uses one as two wires by utilizing the sending gap of the sending party and by means of a seam insertion needle, thereby maximizing the utilization of resources. The receiving side, by monitoring the input data register, if a continuous high level is read, indicates that the transmitting side is in a pause period, and at this time, transmits an ACK frame. If the data continuously transmitted by the sender is read, a timeout timer is set at the moment and the sender waits for transmission suspension, and the sender waits for suspension and transmits an ACK frame after the timeout trigger. The sender monitors the input data register for reception of the data being sent and itself is in a pause phase, at which time it begins to receive the data sent by the receiver. If the sender needs to send data when the sender receives the data sent by the receiver, the action of the sender for sending the data is suspended.

And in the second solution, when the receiving party needs to send data, the receiving party continuously outputs the low level to the pin, and starts to send the ACK packet after a period of time.

If the sender detects a continuously low level in the input data register while transmitting a high level (this duration is determined by the receiver), indicating that the peer is preempting priority, a priority collision is detected. At this point, the sender and receiver can remember the successfully sent data locations for future breakpoint transmission. And then, the sender stops sending data, starts receiving the ACK packet, and restarts the sending flow through the memorized data position which is successfully sent after the ACK packet is received, so as to carry out breakpoint continuous transmission.

Claims

1. A GPIO pin control system comprising:

An input branch circuit for intercepting and checking a value corresponding to the level on the GPIO pin as receiving input data;

the output branch circuit is used for controlling data output, wherein the output branch circuit comprises an output data register, and the output data register is used for storing data sent by the processor;

The IO pin is connected with the output end of the output branch and the input end of the input branch and is used for being connected to external equipment, and the IO pin is set to be in an open-drain output mode;

the processor is used for monitoring the data of the IO pin in real time through the input branch;

When the IO pin is monitored to be at a specific level, judging that the external equipment requests to send data, and sending a fixed value to the output data register so as to enable the IO pin to be in a receiving state;

when the processor needs to send data, the data to be output is directly sent to the output data register so that the IO pin is in an output state;

Wherein the input branch comprises:

the input driving module is used for converting the level state received by the IO pin into a numerical value;

The input data register is used for storing the value corresponding to the level state processed by the input driving module;

and, the output branch further includes:

The output controller receives and outputs the level state converted by the numerical value stored in the output data register according to the open-drain output mode;

An NMOS transistor which receives and opens and closes according to the data output by the output controller;

wherein, the monitoring the data of the IO pin in real time through the input branch includes:

storing the current state of the IO pin;

And reading the data in the input data register, and monitoring the data of the IO pins by the processor according to the data, wherein the monitoring result is combined with the current state of the stored IO pins by the data of the IO pins to make a common decision.

2. The GPIO pin control system of claim 1 wherein the external device is determined to request data to be sent when the IO pin is monitored to be at a low level.

3. The GPIO pin control system of claim 1 wherein the processor is further configured to:

when the IO pin is in an output state, the input branch is used for monitoring whether the data output by the output branch is correct or not in real time, and if the data output by the output branch is incorrect, the data conflict with the external equipment is judged.

4. The GPIO pin control system of claim 1 wherein the real-time monitoring of the output data of the output leg through the input leg comprises:

and the processor reads the data in the input data register in real time, compares the data with the data to be output which is output by the output branch, judges whether the data is consistent, if so, the data is correct, continues to be transmitted, and if not, the data is incorrect, and judges that the data conflict occurs with the external equipment.

5. The GPIO pin control system of claim 4, wherein when the transmitted data to be output from the processor to the output branch does not match the data in the input data register, the processor stops transmitting data to the output branch and reads the data in the input data register in real time.

6. The GPIO pin control system of claim 1 wherein said saving a current state of the IO pin comprises;

storing the current pin output state of the IO pin;

controlling the output branch to output a high-resistance state;

reading the actual level of the external device at the IO pin and storing the actual level into the input data register;

and restoring the state of the IO pin to the saved current state.

7. A method of monitoring based on the GPIO pin control system of any one of claims 1-6, comprising;

setting the IO pin as an open-drain output mode;

When the IO pin is in an output state, the processor reads the data of the input branch circuit in real time and compares the data with the data sent to the output branch circuit, whether the data are consistent or not is judged, if the data are consistent, the data are correctly sent continuously, and if the data are not consistent, the data are incorrectly judged to be in data conflict with external equipment.

8. A method of monitoring based on the GPIO pin control system of any one of claims 1-6, comprising;

setting the IO pin as an open-drain output mode;

When the IO pin is in an idle state, reading data in an input data register, and monitoring the data of the IO pin in real time;

when the processor needs to send data, the data to be output is directly sent to the output data register, so that the IO pin is in an output state.

9. A transmitting method for single-wire communication based on the GPIO pin control system as claimed in any one of claims 1 to 6, wherein the transmitting side and the receiving side each include the GPIO pin control system set to the open-drain output mode, and the IO pins of the transmitting side and the receiving side are connected by one wire, the transmitting method comprising:

setting a circulation timer;

When data transmission is requested, an output branch of a sender outputs a specific level for sending a signal entering an output state;

when the timing of the cyclic timer is finished and triggered, a sender enters an interrupt program, the level on an IO pin is monitored, and if the level is read to be low, the IO pin is switched to output high level;

and polling the level on the IO pin, and entering a data transmission stage if the level is read to a high level.

10. A receiving method for single-wire communication based on the GPIO pin control system as claimed in any one of claims 1 to 6, wherein the sender and the receiver each comprise a GPIO pin control system, and the IO pins of the sender and the receiver are connected by a wire, the receiving method comprising:

setting a circulation timer;

When the timing of the circulation timer is finished and triggered, the receiving side enters an interrupt program, the level on the IO pin is monitored, if the level is read to be low, the opposite side is indicated to enter a sending state, and the switching output branch circuit outputs the low level;

Setting a single timer;

when the timing of the single timer is finished and triggered, outputting a high level for sending a handshake finished signal;

a data reception phase is entered.