CN102957507A - Method for decoding S1 signal of single wire protocol (SWP) physical layer - Google Patents

Abstract

The invention provides a method for decoding an S1 signal of a single wire protocol (SWP) physical layer. The method is suitable for the field of design of an intelligent card integrated circuit with an SWP interface. By the method, the physical layer decoding of an SWP interface of an intelligent card can be completed; and the method has the advantages that the decoding speed and the decoding process are optimized, and the correctness of a decoded result can be guaranteed.

Description

A kind of SWP physical layer S1 signal decoding method

Technical field

The present invention is applied to the SWP Interface design field of smart card, can realize with integrated circuit.

Background technology

The SWP interface is mainly used in supporting the SIM card of near-field communication.Supporting the SIM card of near-field communication, realized E-Payment, authentication, ticket dealing, exchanges data, anti-counterfeit recognition, advertizing several functions, is a kind of new business of moving communicating field, industry common name " mobile payment ".Have broad application prospects.

In NFC (Near Field communication) system, NFC control chip CLF (Contactless Front) will be connected with intelligent card chip.In conventional SIM card, C1 (VCC), C2 (RST), C3 (CLK), C5 (GND), five pins of C7 (IO) are conventional ISO 7816 pins; C4 (RFU), C8 (RFU) pin are then expanded to USB interface on the sheet by ISO; C6 (SWP) pin is used for connecting smart card and CLF chip, follows the SWP agreement.

The SWP agreement is the single line connectivity scenario of the C6 pin that gives SIM card of Gemalto company proposition.As shown in Figure 4, in the SWP agreement, smart card and CLF interface comprise three line: VCC (C1), GND (C5), SWP (C6).Wherein realize full-duplex communication based on voltage and load-modulate principle on the SWP holding wire, can realize that like this smart card supports ISC7816 and two interfaces of SWP simultaneously under ISO7816 interface definition, and reserve the pin of expansion the 3rd high speed (USB) interface.Support the smart card of SWP must support simultaneously ISO 7816 and two protocol stacks of SWP, needing the smart card Chip Operating System is the operating system of multitask, and these two parts need to manage independently, and the reset signal of two interfaces is independent of one another.

The SWP agreement is point to point protocol between smart card and CLF.The principle of single-wire-protocol is based under the full-duplex mode that modulation /demodulation to voltage, electric current realizes, has wherein defined S1, two signals of S2 physical layer.

Signal S1 is low or high by Digital Modulation in voltage domain, realizes that CLF is to the transfer of data of smart card.

Signal S2 is low or high by Digital Modulation in current field, realizes that intelligence snaps into the transfer of data of CLF.

Signal S1 is the logical value that recently characterizes current transmission position by different duties, as shown in Figure 1.Stipulate in the agreement that the high level duty ratio of logical one is 70%～80%, the high level duty ratio of logical zero is 20%～30%.

The SWP interface of smart card end is characterized in that realizing physical layer in the SWP standard, MAC layer, logic link layer and HCI agreement, thereby the realization smart card is communicated by letter with the CLF end.

Summary of the invention

The technical problem that the present invention solves provides a kind of smart card to the implementation method of physical layer S1 signal decoding.Guarantee that smart card can be correctly decoded the logical data that the CLF end sends.

In order to realize said method, need to provide in the intelligent cards SWP interface decoding clock of high frequency, be used for realizing SWP physical layer S1 signal decoding.Its feature may further comprise the steps:

1) behind the system reset, counter is set to 0;

2) master controller detects the success of S1 signal rising edge in the sampling instant of SWP decode clock; Whether, be then represent S1 signal decoding after be logical zero, otherwise be logical one behind the expression S1 signal decoding if being 0 according to current counter then; Counter puts 1, then waits for next time SWP decode clock sampling;

3) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter is full 0 or complete 1, then waits for next time SWP decode clock sampling;

4) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter be full 0 or complete 1, then according to the S1 level value that samples, height then with counter from adding 1, low then counter is subtracted 1 certainly.

Master controller starts master controller and controls SWP physical layer S1 signal decoding by after the SWP interface enable, and exports the data that are synchronized with the SWP decode clock and use to logic link layer.

Description of drawings

Fig. 1 S1 signal bits coded system

Fig. 2 SWP system layer model

Fig. 3 SWP physical layer S1 signal decoding method

Fig. 4 SWP system line schematic diagram

Embodiment

Master controller starts master controller and controls SWP physical layer S1 signal decoding by after the SWP interface enable, and output is synchronized with the data of SWP decode clock to logic link layer.

As shown in Figure 1, the S1 Signal coding is followed the high-low level duty ratio difference of stipulating and is characterized the current data value in the SWP agreement.In a data bit wide, high level accounts for 3/4 characterization logic 1; Low level accounts for 1/4 characterization logic 0.

Then resolve physical layer data by the high and low level ratio of SWP decode clock sampling S1 signal.In a data bit wide, the high level that samples the then characterization logic 1 that occupies the majority, the low level then characterization logic 0 that occupies the majority.

Because physical layer encodes all begins with the high level of S1 signal, low level finishes.Think a data transmission beginning so detect S1 signal rising edge in the coding/decoding method, S1 signal rising edge is then thought the current data end of transmission next time, and the next bit transfer of data begins.

The invention is intended to finish the physical layer shown in Fig. 2 resolves, and the data after will resolving export the upper layer logic link layer to, the present invention can be when detecting the next bit transfer of data and beginning, finish the parsing of current data, and the control by counter data, accomplished SWP physical layer decoding optimization area circuit.

Describe the present invention in conjunction with Fig. 3, the present invention is by the record of counter realization to the rear S1 signal level value of sampling, and use SWP decode clock is to the S1 signal sampling; Described SWP physical layer S1 signal decoding method comprises,

1) behind the system reset, counter is set to 0;

2) master controller detects the success of S1 signal rising edge in the sampling instant of SWP decode clock; Whether, be then represent S1 signal decoding after be logical zero, otherwise be logical one behind the expression S1 signal decoding if being full 0 according to current counter then, counter puts 1; Then wait for next time SWP decode clock sampling;

3) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter is full 0 or complete 1, then waits for next time SWP decode clock sampling;

4) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter is not full 0 or complete 1, then according to the S1 level value that samples, height then with counter from adding 1, low then with counter from subtracting 1, then wait for next time SWP decode clock sampling.

By smart card SWP interface physical layer S1 signal decoding method disclosed by the invention, make smart card successfully realize the S1 signal decoding, efficiently solve the problem of SWP interface decoding.

Claims (1)

1. SWP physical layer S1 signal decoding method is characterized in that step is as follows:

1) system reset sets to 0 counter;

2) master controller detects the success of S1 signal rising edge in the sampling instant of SWP decode clock, judge then whether current counter is 0, be then to be logical zero behind the S1 signal decoding, otherwise be logical one behind the S1 signal decoding, and counter put 1, then wait for next time SWP decode clock sampling;

3) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter is full 0 or complete 1, then waits for next time SWP decode clock sampling;

4) master controller detects the failure of S1 signal rising edge in the sampling instant of SWP decode clock, and current counter is not full 0 or complete 1, then according to the S1 level value that samples, height then with counter from adding 1, low then with counter from subtracting 1, then wait for next time SWP decode clock sampling.

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