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EP1989343A2 - Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse - Google Patents

Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse

Info

Publication number
EP1989343A2
EP1989343A2 EP07703498A EP07703498A EP1989343A2 EP 1989343 A2 EP1989343 A2 EP 1989343A2 EP 07703498 A EP07703498 A EP 07703498A EP 07703498 A EP07703498 A EP 07703498A EP 1989343 A2 EP1989343 A2 EP 1989343A2
Authority
EP
European Patent Office
Prior art keywords
layer
etching solution
etching
solution according
acid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP07703498A
Other languages
German (de)
English (en)
Inventor
Frank Dietz
Klaus Kohlmann-Von Platen
Hans-Joachim Quenzer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP1989343A2 publication Critical patent/EP1989343A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/02Local etching
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/18Acidic compositions for etching copper or alloys thereof
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/44Compositions for etching metallic material from a metallic material substrate of different composition
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • UBM bump metallization
  • a UBM layer system represents a specific sequence of different conductive layers in contact with one another and is intended to achieve the best possible and lasting contact between a substrate, for example a wafer, and a contacting material, for example a solder, or the external structure associated therewith , For example, a wire or a second substrate, ensure.
  • a substrate for example a wafer
  • a contacting material for example a solder
  • the external structure associated therewith For example, a wire or a second substrate, ensure.
  • UBM coating systems are becoming increasingly important.
  • a UBM coating system should provide both optimal electrical and mechanical contact.
  • the contact in various applications must allow the dissipation of thermal energy without significantly changing its properties.
  • the materials used in a UBM layer system should usually have good adhesion to the respective substrate, usually aluminum and / or silicon nitride and / or silicon oxide on the one hand and good wettability with respect to the bonding material used a tin-containing solder, on the other hand.
  • the entire layer sequence should have a high conductivity.
  • the aluminum layer makes the connection to the usually highest metal level of the wafer, usually also aluminum.
  • the deposited on the aluminum nickel vanadium serves as a diffusion barrier and prevents metal atoms migrate from the copper layer disposed thereon and the overlying contacting material through the aluminum layer into the substrate and contaminate doped areas or influence.
  • the final copper layer ensures a low contact resistance and a good connection with the bonding material.
  • the metal layers are usually structured individually or two metal layers simultaneously.
  • nitric acid As a standard etching solution for copper, nitric acid is generally used. According to the US 6,130,141 but also iron chloride or mixtures of sulfuric acid and potassium chromate or sulfuric acid and peroxide can be used for the copper etching.
  • a commercially available solution for nickel etching contains thiourea, which is considered to be carcinogenic and thus carries a high risk potential.
  • WO 8904883 discloses.
  • a highly concentrated iron (III) chloride solution is used, but it is not cleanroom compatible and unsuitable for use in semiconductor production.
  • Nickel vanadium layer is known from US20030146191.
  • the nickel vanadium layer is etched electrochemically using sulfuric acid.
  • a concentrated phosphoric acid solution is usually used (Kirt R.
  • the etching solution used consists of phosphoric acid, deionized water, acetic acid and hydrogen peroxide.
  • This solution has the disadvantage that hydrogen peroxide is a highly reactive medium which requires a correspondingly high level of security measures in terms of storage and transport. In addition, it decays
  • Claim 21 gives a method for structuring a layer system according to the preamble of the main claim.
  • the etching solution according to the invention is suitable for etching a layer system comprising at least one layer of aluminum, at least one layer of copper and at least one third layer selected from nickel vanadium, nickel and its alloys, which is arranged between the at least one aluminum layer and the at least one copper layer , having.
  • the etching solution contains or consists of phosphoric acid, nitric acid, deionized water and at least one salt which can release halogen ions, in particular under the conditions of the etching process according to the invention.
  • An advantage of the etching solution according to the invention is that a copper / nickel vanadium / aluminum layer system can be structured in one process step.
  • the reduced number of process steps compared with 2 and 3-step etching processes reduces contamination of the layer system.
  • the etching solution according to the invention furthermore has the advantage that it is possible to dispense with possible contaminating chemical compounds, such as, for example, KOH, sodium compounds or ammonium compounds.
  • the etching solution also contains no highly reactive and carcinogenic media, which reduces the cost of required security measures.
  • the comparatively advantageous is Low material consumption, which ensures a more effective use of the etching process.
  • it should be emphasized as an advantage that the etching solution does not have to be activated even after days of disuse and therefore can be used immediately.
  • the etching solution according to the invention contains as halogen component a halogen ion-releasing salt.
  • a halogen ion-releasing salt is a metal salt whose anions are halogen ions.
  • the cations of the metal salt are particularly preferably selected from the metals contained in the layer system. As a result, it is possible to prevent additional metals, which are not contained in the layer system, from influencing the etching process and the quality of the structured layer system.
  • a particularly suitable metal salt is aluminum chloride.
  • the halogen component or the halogen ion-releasing salt should preferably ensure the release of halogen ions even under acidic conditions having a pH between about 0 and about 3, with the most preferred range being between about pH 1 and about 2.
  • the etching solution contains 30-45 vol% phosphoric acid, 5-10 vol% nitric acid, 45-55 vol% deionized water, and at least 0.1 mol / 1 halogen component.
  • the etching solution contains a complex-forming ligand which is stable at a pH of less than or equal to 3, particularly preferably at a pH of less than or equal to 1, and stable complexes with copper ions under the particular acidic conditions forms.
  • stable complexes are understood to be complexes whose complex formation constant is pK> 5.
  • a suitable complexing agent deposits of metal ions, such as, for example, copper ions, can be reduced.
  • ligands which are at least 3-dentate, preferably 6-8 dentate, and contain amine groups and / or carboxylic acid groups, the amine groups preferably being tertiary amines.
  • the etching solution contains EDTA or another ligand which complexes with copper, their
  • EDTA forms particularly strong complexes with copper and other metal ions.
  • the highest possible proportion of complex-forming ligands is sought, with no precipitation should occur.
  • the maximum concentration complex-forming ligands is therefore limited by the solubility limit and, for example, is less than 3% by volume of the total solution in the case of EDTA.
  • the etching solution may contain organic acids (such as, for example, phenol, acetoacetic ester, acetic acid), preferably carboxylic acids, particularly preferably carboxylic acids having at least two carboxylic acid groups.
  • the carboxylic acid has one or more hydroxyl groups.
  • at least one hydroxy group is vicinal or geminal arranged at least to one of the carboxylic acid groups.
  • these organic acids have the advantage of acting as an inhibitor of inhibiting crystal growth, particularly the growth of copper crystallites.
  • Particularly suitable inhibitors are citric acid and tartaric acid.
  • the maximum concentration is limited by the solubility limit and, for example, for citric acid is below 5% by volume of the total solution.
  • the inventive method for structuring a layer system which comprises at least one layer of aluminum, at least one layer of copper and at least one third layer selected from nickel vanadium, nickel and its alloys, which between the at least one aluminum layer and the At least one copper layer is arranged, comprises the following method steps:
  • etching mask Arranging or forming an etching mask on the surface of the layer system, wherein the etching mask at least partially covers the at least one copper layer etching step, wherein at least 2 layers of the layer system with an etching solution, the phosphoric acid, nitric acid, deionized water and at least one Halogenkomponente- the halogen ions may be etched or contains these components
  • Rinsing step in which the etched layer system is rinsed with water and / or a base Drying of the etched layer system Removal of the etching mask.
  • the UBM layer system to be patterned with the claimed method which is arranged or applied on a substrate, for example a wafer, has at least one layer of nickel vanadium or nickel or its alloys.
  • nickel vanadium is used, wherein the vanadium content is for example about 7%.
  • the introduction of vanadium produces a diamagnetic nickel vanadium alloy from the ferromagnetic nickel, which is particularly true for the process of layer deposition by means of magnetron sputtering Meaning is.
  • the thickness of the copper layer and the aluminum layer is usually also in the nm range or in the micron range.
  • the layer thicknesses are selected so that the mechanical stresses between the layers and the stress gradients in the layers are as small as possible in order to avoid a bending of the wafer or a spalling of layers.
  • the composition of the etching solution and thus the etching rate of the various materials must be adjusted in accordance with the ratio of the individual layer thicknesses.
  • a photoresist layer is usually applied to the surface of the copper layer, which covers the non-etching areas and protects against attack by the etching solution.
  • Other materials may be used for such an "etch mask.”
  • Materials for the etch mask should, in principle, have good adhesion to the copper layer in order to prevent penetration of the etch solution under the etch mask and associated delamination or undercutting of the etch mask.
  • the etch mask should be resistant to the etch solution to cover the covered areas for the entire duration of the etch step prior to attack to protect the etching solution.
  • the lowest possible undercutting is desirable in order to ensure the largest possible contact surface and thus a stable mechanical connection.
  • severe undercutting may result in attack of the layer below the UBM stack, which would increase the electrical resistance of the contact surface and reduce the stability of the mechanical bond of the UBM stack to the substrate.
  • the uncovered areas are structured in a subsequent etching step (etching process), the advantage of the method according to the invention being in particular that all three metal layers (copper, nickel vanadium, aluminum) are removed in one process step and the technological requirements for the etched layer system are met.
  • the etching process is preferably carried out in a commercially available wet etching, wherein up to 25 wafers can be etched simultaneously. With a coverage of the etch of at least 15 wafers per liter of etching solution, more than 300 wafers can be patterned with a wet etching tank filling of 20 liters. This is made possible by the relatively low material consumption of the etching process. Furthermore, the method according to the invention is also suitable for use in spray etching processes.
  • Optimal control of the etching process is favored by the fact that the layer system is in contact with the etching solution for at least 1 minute.
  • the etching rates of the individual metal layers depend inter alia on the temperature.
  • the etching step is carried out at temperatures between about 15 0 C and 8O 0 C, preferably between about 35 0 C and 60 0 C. Under these conditions, copper is only slightly removed in the areas covered by the etching mask, whereby the etching mask is only slightly undercut.
  • the copper layer is in turn undercut by the removal of the nickel vanadium layer. Underetching of the nickel vanadium layer by the aluminum removal does not occur.
  • the nickel vanadium layer is usually not undercut by the aluminum removal.
  • the etch rate of aluminum increases and the etch rate of copper decreases. This leads to variations in the intensity of the undercuts. Therefore, it is necessary that in addition to the mixing ratio of the etching solution and the temperature must be matched to the layer system to be etched.
  • the etching solution the phosphoric acid
  • Nitric acid, deionized water and at least one halogen component - which can liberate halogen ions or consists of these components, use in semiconductor production and / or in the manufacture of devices using semiconductor technology
  • Processes are made, in particular for etching a layer system comprising at least one layer of aluminum, at least one layer of copper and at least one third layer selected from nickel vanadium, nickel and its alloys, the between the at least one aluminum layer and the at least one copper layer is arranged, and particularly preferably represents a UBM stack.
  • FIG. 2 shows the finished structured layer system (2, 3, 1) with a photoresist layer as the etching mask (4).
  • FIG. 3 shows the finished structured layer system (2, 3, 1) after removal of the photoresist layer as an etching mask (4).
  • Fig. 3a shows the aluminum layer ( 1 ) which is excellent under the copper layer (2) and the nickel vanadium layer (3 ) .
  • Fig. 1 is a on a substrate (5) arranged unstructured layer system (2, 3, 1), consisting of an approximately 0.5 micron thick aluminum layer (1), an about 0.5 micron thick nickel vanadium layer (3) and a about 1 micron thick copper layer (2) shown.
  • Passivation layer (6) is used for electrical insulation.
  • An AZ photoresist layer (4) is applied and patterned on the copper layer (2) as an etching mask in order to obtain the not to be etched areas of the layer system (2, 3, 1) to protect against the etching attack.
  • the result of the etching step is shown in FIG. 2.
  • the layer system (2, 3, 1) is removed in the area uncovered by the etching mask (4) and the etching mask (4) is only slightly undercut.
  • the photoresist layer (4) functioning as an etching mask is removed (FIG. 3) ).
  • the quality of the etching process is checked. Particular attention is paid to the aluminum layer (1).
  • the aluminum layer (1) should visibly protrude below the copper layer (2) and the nickel vanadium layer (3) to preclude undercut or erosion of the metal layer below the UBM stack (7).

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)

Abstract

L'invention concerne une solution d'attaque permettant l'attaque d'un système de couches constitué d'au moins une couche d'aluminium, d'au moins une couche de cuivre et d'au moins une troisième couche sélectionnée parmi le nickel-vanadium, le nickel et ses alliages, laquelle couche est placée entre ladite au moins une couche d'aluminium et ladite au moins une couche de cuivre. Selon ladite invention, cette solution contient de l'acide phosphorique, de l'acide nitrique, de l'eau désionisée et au moins un sel pouvant libérer des ions halogènes ou est composée de ces derniers. La solution d'attaque selon l'invention est la base d'un procédé de structuration en une étape d'un système de couches de métallisation sous bosse utilisé lors de la fabrication de composants réalisés par des procédés issus de la technologie des semi-conducteurs.
EP07703498A 2006-02-22 2007-02-16 Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse Withdrawn EP1989343A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006008261A DE102006008261A1 (de) 2006-02-22 2006-02-22 Ätzlösung und Verfahren zur Strukturierung eines UBM-Schichtsystems
PCT/EP2007/001363 WO2007096095A2 (fr) 2006-02-22 2007-02-16 Solution d'attaque et procédé de structuration d'un système de couches de métallisation sous bosse

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EP1989343A2 true EP1989343A2 (fr) 2008-11-12

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US (1) US20090221152A1 (fr)
EP (1) EP1989343A2 (fr)
JP (1) JP2009527908A (fr)
DE (1) DE102006008261A1 (fr)
WO (1) WO2007096095A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138099B1 (en) * 2010-11-17 2012-03-20 International Business Machines Corporation Chip package solder interconnect formed by surface tension
KR102492733B1 (ko) 2017-09-29 2023-01-27 삼성디스플레이 주식회사 구리 플라즈마 식각 방법 및 디스플레이 패널 제조 방법

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2428464A (en) * 1945-02-09 1947-10-07 Westinghouse Electric Corp Method and composition for etching metal
GB1053162A (fr) * 1963-01-21
JPS5217995B2 (fr) * 1972-02-18 1977-05-19
US4092532A (en) * 1976-11-10 1978-05-30 The United Sates Of America As Represented By The Secretary Of The Navy Binary apparatus for motion control
US4230522A (en) * 1978-12-26 1980-10-28 Rockwell International Corporation PNAF Etchant for aluminum and silicon
US4297184A (en) * 1980-02-19 1981-10-27 United Chemi-Con, Inc. Method of etching aluminum
US4746369A (en) * 1982-01-11 1988-05-24 Enthone, Incorporated Peroxide selective stripping compositions and method
US5258093A (en) * 1992-12-21 1993-11-02 Motorola, Inc. Procss for fabricating a ferroelectric capacitor in a semiconductor device
US5508229A (en) * 1994-05-24 1996-04-16 National Semiconductor Corporation Method for forming solder bumps in semiconductor devices
US6209037B1 (en) * 1995-05-30 2001-03-27 Roy-G-Biv Corporation Motion control systems using communication map to facilitating communication with motion control hardware
US5898588A (en) * 1995-10-27 1999-04-27 Dainippon Screen Mfg. Co. Method and apparatus for controlling substrate processing apparatus
US5587103A (en) * 1996-01-17 1996-12-24 Harris Corporation Composition, and method for using same, for etching metallic alloys from a substrate
US5904859A (en) * 1997-04-02 1999-05-18 Lucent Technologies Inc. Flip chip metallization
AT410043B (de) * 1997-09-30 2003-01-27 Sez Ag Verfahren zum planarisieren von halbleitersubstraten
US6130141A (en) * 1998-10-14 2000-10-10 Lucent Technologies Inc. Flip chip metallization
US6117250A (en) * 1999-02-25 2000-09-12 Morton International Inc. Thiazole and thiocarbamide based chemicals for use with oxidative etchant solutions
US6791531B1 (en) * 1999-06-07 2004-09-14 Dot On, Inc. Device and method for cursor motion control calibration and object selection
US6630433B2 (en) * 1999-07-19 2003-10-07 Honeywell International Inc. Composition for chemical mechanical planarization of copper, tantalum and tantalum nitride
EP1354355A1 (fr) * 2001-01-23 2003-10-22 Honeywell International, Inc. Agents de planarisation pour planarisation par gravure centrifuge de composants electroniques et procedes d'utilisation
US7904194B2 (en) * 2001-02-09 2011-03-08 Roy-G-Biv Corporation Event management systems and methods for motion control systems
DE10302596A1 (de) * 2002-01-24 2003-08-28 Shipley Company Marlborough Behandlung von Metalloberflächen mit einer modifizierten Oxidaustauschmasse
US20030146191A1 (en) * 2002-02-07 2003-08-07 Ho-Ming Tong Etching method for nickel-vanadium alloy
KR100672933B1 (ko) * 2003-06-04 2007-01-23 삼성전자주식회사 세정 용액 및 이를 이용한 반도체 소자의 세정 방법
US7244370B2 (en) * 2003-08-05 2007-07-17 Canon Kabushiki Kaisha Method for producing circuit substrate
WO2005022592A2 (fr) * 2003-08-22 2005-03-10 Fujifilm Electronic Materials U.S.A., Inc. Nouvel agent de mordançage de metaux aqueux
KR20070017762A (ko) * 2005-08-08 2007-02-13 엘지.필립스 엘시디 주식회사 식각액 조성물, 이를 이용한 도전막의 패터닝 방법 및평판표시장치의 제조 방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007096095A2 *

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US20090221152A1 (en) 2009-09-03
WO2007096095A3 (fr) 2008-02-07
WO2007096095A2 (fr) 2007-08-30
JP2009527908A (ja) 2009-07-30
DE102006008261A1 (de) 2007-08-30

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