[go: up one dir, main page]

EP0981203B1 - Gesteuerte Stromquelle mit beschleunigtem Umschalten - Google Patents

Gesteuerte Stromquelle mit beschleunigtem Umschalten Download PDF

Info

Publication number
EP0981203B1
EP0981203B1 EP99202607A EP99202607A EP0981203B1 EP 0981203 B1 EP0981203 B1 EP 0981203B1 EP 99202607 A EP99202607 A EP 99202607A EP 99202607 A EP99202607 A EP 99202607A EP 0981203 B1 EP0981203 B1 EP 0981203B1
Authority
EP
European Patent Office
Prior art keywords
output
current
transistor
charge pump
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99202607A
Other languages
English (en)
French (fr)
Other versions
EP0981203A1 (de
Inventor
David Société Civile S.P.I.D Canard
Vincent Société Civile S.P.I.D Fillatre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP0981203A1 publication Critical patent/EP0981203A1/de
Application granted granted Critical
Publication of EP0981203B1 publication Critical patent/EP0981203B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations

Definitions

  • Such current sources are frequently used to construct charge pumps for delivering current pulses to control a charge or a discharge of capacitive elements in phase-locked strands operating a frequency control of a signal delivered by a voltage controlled oscillator.
  • Such a loop phase locked is described in particular in European patent application No. 0 670 629 A1.
  • the charge pump included in this sulk implements current sources of the type described in the introductory paragraph, in which the transistors of power are PNP type, their bases, transmitters and collectors respectively constituting polarization, reference, and transfer terminals. These power transistors are polarized by means of an emitter current permanently supplied by a positive terminal power supply, their conduction being operated by the control module by means of a adequate base voltage when the control signal instructs the module to control. The power transistors then conduct the bias current from their transmitters to their collectors, and to the output of the controlled current source.
  • the power transistors must be turned on very quickly, particularly when the frequency of the oscillator output signal is high, for example of the order GigaHertz, the so-called switching frequency with which the power transistors pass from one blocked state to a saturated state, which can then be of the order of MegaHertz.
  • the value of the current output by the controlled current source when it is in conduction, called nominal value, is often important. This leads to using, to make each controlled current source, several transistors whose dimensions are large compared to those of the other transistors included in the locking lug phase.
  • Such structures have significant parasitic capacities, particularly at the level collector-base junctions, which delay the entry into effective conduction of power transistors and cause changes in the shape of the current pulses delivered by the current source controlled, alterations which consist essentially of positive and negative peaks of current during switching of the power transistors.
  • One of the aims of the invention is to remedy to a large extent these disadvantages, by proposing a controlled current source within which the influence of parasitic capacitances of the power transistors is considerably minimized.
  • a controlled current source conforming to the introductory paragraph is characterized according to the invention in that the reference terminals of the power transistors are connected together to the output of the control module intended to deliver a current whose value depends on the value of the control signal, the bias terminals of the transistors of power being subjected permanently, when the current source is in operation, at a voltage of predetermined value making it possible to render said transistors potentially conductive power.
  • the bias voltage applied at the bias terminals of the power transistors performs a kind of pre-charging parasitic capacitances of said transistors and makes these transistors potentially conductors. It will then suffice to present a current at their reference terminals so that they become effectively conductive, almost instantly.
  • parasitic capacities being preloaded they are not subject to discontinuities of voltage, unlike what occurs in the known controlled current source. The changes in the shape of the output current of the controlled current source due to switching of the power transistors are therefore considerably attenuated in the controlled current source according to the invention.
  • a controlled current source such as described above is characterized in that the control module comprises a first and a second transistor forming a first differential pair, and intended to receive on their polarization terminals the control signal, and a third transistor whose path main current is arranged, in series with a first resistance, between a positive terminal supply and output of the control module, the transfer terminal of the first transistor being connected to the positive supply terminal, the transfer terminal of the second transistor being connected to the positive supply terminal via a second resistor, on the one hand, and to the bias terminal of the third transistor, on the other hand.
  • This embodiment is advantageous by its simplicity, using a number limited components. Furthermore, it will be demonstrated in the following presentation that the value nominal output current of such a controlled current source directly depends on the value of the first resistance, which allows easy calibration of said output current of source.
  • control module further includes a fourth and a fifth transistor, forming a second pair differential, and intended to receive on their polarization terminals a so-called selection signal, the transfer terminal of the fourth transistor being connected to the positive supply terminal, the transfer terminal of the fifth transistor being connected to the positive supply terminal via a voltage regulating element, on the one hand, and to the bias terminal of the third transistor via a third resistance, on the other hand.
  • the element voltage regulator consists of a diode.
  • the invention therefore also relates to a charge pump, provided with two control inputs intended to receive control signals, and an output intended to deliver a current output whose direction and value depend on the values of the control signals, characterized in that it comprises a first and a second controlled current source as described above, whose command inputs constitute the inputs of charge pump control, the outputs of the first and second current sources being connected to the first and second branches of a current mirror, the output of one of the current sources being further connected to the output of the charge pump.
  • such a charge pump comprises in in addition to a so-called drainage current source, intended to flow continuously, when the charge pump is operating, a current whose nominal value is negligible in front of the maximum value of the charge pump output current, the current source of drainage being arranged between that of the outputs of the first and second current sources which is not connected to the output of the charge pump, and a negative supply terminal.
  • Drainage current source allows evacuation of electrical charges stored in transistors constituting the current mirror, which prevents a current of parasitic leak does not appear in one of the branches of said current mirror to evacuate these charges to the negative supply terminal, after the conduction of the first source of current will have been interrupted. Such a leakage current would cause the persistence of a current negative at the outlet of the charge pump, a phenomenon which is all the more unacceptable as the charge pump switching frequency is high.
  • Such a charge pump can advantageously be implemented in a phase locked loop.
  • Such loops are commonly used to operate frequency conversions in radio signal receivers, such as for example televisions or radiotelephones.
  • the invention therefore also relates to an apparatus for receiving radio signals, comprising an antenna and filtering system allowing the reception of a signal whose frequency is selected within a given frequency range, and its transformation into a signal electronic said radio signal, apparatus in which a frequency conversion, from the selected frequency to a predetermined intermediate frequency, is carried out by means of a mixer intended to receive the radio signal, on the one hand, and an output signal of a local oscillator whose frequency is determined by the value of an adjustment voltage, on the other hand, apparatus further comprising a phase / frequency detector intended to compare the frequency of the output signal of the oscillator with that of a reference signal and to deliver control signals to a charge pump, the values of which depend on the result of said comparison, the s nettle of the charge pump being connected to a capacity intended to generate at its terminals the adjustment
  • the power transistors are PNP type bipolar transistors. Their reference terminals, transfer terminals and polarization terminals are respectively constituted by their transmitters, collectors and bases.
  • the transmitters of the power transistors are connected together to the output of the control module CNTi, their bases being permanently subjected, when the current source CSi is in operation, to a predetermined voltage VCC-3.Vd.
  • This voltage is generated by means of the assembly of three diodes D1i, D2i and D3i, arranged in series with a resistor Rdi, between a positive supply terminal VCC and a negative supply terminal GND, which may be materialized by the circuit mass.
  • the voltage generated by the three diodes D1i, D2i and D3i is equal to 3.Vd, where Vd is the threshold voltage of a diode.
  • the emitter-base voltage of the power transistors is equal to 3Vd-Vcnti, where Vcnti represents a voltage drop generated by the control module CNTi.
  • the components constituting the controlled current source CSi can easily be dimensioned so that 3Vd-Vcnti> Veb th, where Veb th represents the minimum value which the emitter-base voltage of the transistors must take power so that they can drive.
  • the bias voltage VCC-3.Vd applied to the bases of the power transistors then in a way preloads the stray capacitances of said transistors and makes these transistors potentially conductive. It will therefore suffice, in this configuration, to present a current Ii to their transmitters so that they become effectively conductive, and this in an almost instantaneous manner.
  • FIG. 2 is a block diagram showing a CP charge pump incorporating two current sources of the type described above.
  • This CP charge pump is provided with two control inputs intended to receive control signals V1 and V2, and an OUT output intended to deliver an output current whose direction and value depend of the values of the control signals V1 and V2.
  • the CP charge pump has a first and second controlled current source CS1 and CS2 of the predefined type, the control inputs constitute the control inputs of the charge pump CP, the outputs OUT1 and OUT2 of the first and second current sources being connected to the first and second branches of a current mirror (M1, M2), the output of the second source of current CS2 being further connected to the output OUT of the charge pump CP.
  • M1, M2 current mirror
  • the mirror of current (M1, M2) consists of two transistors, M1 and M2, whose collectors form respectively the first and second branches of the current mirror, the bases of which are connected together to the collector of the first transistor M1, and whose emitters are connected to a GND negative supply terminal.
  • the control signal V2 from the second source of controlled current CS2 orders it, said source CS2 conducts a current IO2.
  • the first one current source CS1 not conducting, the output current IO2 of the second source of current CS2 is directed to the output OUT of the charge pump CP which therefore delivers a current positive. Conversely, if the control signal V1 of the first controlled current source CS1.
  • the charge pump CP also includes a current source, known as drainage, disposed between the output of the first current source CS1 and the negative terminal. GND power supply.
  • This current source is intended to flow continuously, when the charge pump CP is in operation, a current Id whose nominal value is negligible compared to the maximum value of the output current IO1 or IO2 of the charge pump, CP.
  • the drain current source allows the evacuation of electrical charges stored in parasitic capacitances that comprise the transistors M1 and M2 constituting the current mirror (M1, M2), which prevents a parasitic leakage current from appearing in one of the branches of said current mirror to evacuate these charges towards the negative supply terminal GND, after the conduction of the first current source CS1 has been interrupted.
  • Such leakage current would cause the persistence of a negative current at the output OUT of the pump CP load, a phenomenon which is all the more unacceptable as the switching frequency of the CP charge pump is high.
  • FIG. 3 schematically represents a controlled current source CS1 according to a preferred embodiment of the invention.
  • the module CNT1 control includes first and second transistors T1 and T2 forming a first differential pair, and intended to receive on their bases the control voltage V1, and a third transistor T3 including the main current path, that is to say the collector-emitter path, is arranged in series with a first resistor R11, between a positive terminal VCC power supply and the output of the CNT1 control module, the collector of the first transistor T1 being connected to the positive supply terminal VCC, the collector of the second transistor T2 being connected to the positive supply terminal VCC via a second resistor R21, on the one hand, and at the base of the third transistor T3, on the other hand.
  • the CNT1 control module includes in addition to a fourth and a fifth transistor T4 and T5, forming a second pair differential, and intended to receive on their bases a so-called selection signal Vx1, constituted here by a voltage, the collector of the fourth transistor T4 being connected to the positive terminal VCC power supply, the collector of the fifth transistor T5 being connected to the positive terminal VCC power supply via a diode-mounted Q5 transistor, on the one hand, and at the base of the third transistor T3 via a third resistor R31, on the other hand.
  • the diodes D1i, D2i and D3i are here constituted by transistors Q1, Q2 and Q3, polarized by means of a transistor Q4 arranged in series with the aforementioned transistors, according to a technique well known to the specialist.
  • the transistors used are bipolar transistors, it is obvious that MOS type transistors, whose grids, drains and sources would respectively constitute the terminals of polarization, of transfer and of reference, can be substituted for them.
  • the current source CS1 operates as follows: When the control voltage V1 is negative, the second transistor T2 is conductive while the first transistor T1 is blocked.
  • the third transistor T3 operates as a voltage follower and copies the potential of the base of said third transistor T3 on its emitter with an offset equal to a base-emitter voltage.
  • the second resistor R21 is traversed by a significant current and generates at its terminals a sufficiently large voltage drop so that the value of the difference between the potential of the emitter of the third transistor T3 and that of the bases of the power transistors is less than a minimum value authorizing the conduction of said power transistors. The voltage drop across the second resistor R21 thus ensures that the power transistors are blocked.
  • the current I1 delivered by the control module CNT1 is therefore zero and the power module PA1 is inactive.
  • the second transistor T2 is blocked while the first transistor T1 becomes conductive.
  • the potential of the base of the third transistor T3 therefore becomes close to that of the positive supply terminal VCC, the potential of the emitter of said third transistor T3 becoming sufficiently high to make the transistors potentially conductive.
  • the third transistor T3 then delivers, via the first resistor R11, a non-zero current I1 to the output of the control module CNT1.
  • This current I1 makes the power transistors conductive as soon as it reaches their transmitters, and the controlled current source CS1 delivers a non-zero output current IO1.
  • Vbe (T3) + V11 + Veb Vbe (Q1) + Vbe (Q2) + Vbe (Q3), where Vbe (Ti) and Vbe (Qi) are the base-emitter voltages of the NPN, Ti and Qi transistors respectively, Veb the emitter-base voltage of the PNP power transistors and V11 the voltage across the first resistor R11.
  • Vbe (Ti) and Vbe (Qi) are the base-emitter voltages of the NPN, Ti and Qi transistors respectively, Veb the emitter-base voltage of the PNP power transistors and V11 the voltage across the first resistor R11.
  • the base-emitter and emitter-base voltages of the various transistors are, by construction, substantially equal to a value Vbe, which is of the order of 0.6 volts.
  • the output current IO1 of the charge pump CS1 therefore has the nominal value Vbe / R11.
  • the choice of the value of the first resistor R11 thus makes it possible to easily calibrate the output current I01.
  • the selection voltage Vx1 is negative; the reasoning developed above remains applicable, except that the first law of mesh is no longer valid. Indeed, a negative selection voltage Vx1 makes the fifth transistor T5 conductive while the fourth transistor T4 is blocked.
  • the diode constituted by the transistor Q5 therefore becomes on, and imposes a voltage Vbe across the terminals of the series assembly of the second and third resistors R21 and R31, which form a voltage divider bridge.
  • FIG 4 partially shows a signal receiving apparatus which incorporates a CP charge pump built on the basis of two sources of controlled current CS1 and CS2 of the type described above.
  • This device has a system antenna and AF filtering allowing the reception of a signal whose frequency is selected within a given frequency range, and its transformation into a signal electronic Vfr, called radio signal, having an FR frequency called radio frequency.
  • a frequency conversion from the selected FR radio frequency to a frequency intermediate predetermined FI, is carried out in this apparatus by means of a mixer MX intended to receive the radio signal Vfr, on the one hand, and an output signal Vco from a local oscillator OSC whose oscillation frequency FLO is determined by the value of an adjustment voltage Vtun, on the other hand.
  • This device also includes a PD phase / frequency detector intended to compare the frequency FLO of the output signal Vco of the oscillator OSC with the frequency FREF of a reference signal Vref, and to deliver to the charge pump CP signals of command V1, V2 and selection Vx1, Vx2, whose values depend on the result of said comparison.
  • the output of the charge pump CP is connected to a capacitor Cs intended for generate at its terminals the setting voltage Vtun.
  • the FLO oscillation frequency is controlled by means of a loop with phase lock incorporating the CP charge pump.
  • This sulk works from the as follows: when the oscillation frequency FLO is lower than the frequency of reference FREF, the phase / frequency detector PD delivers a control voltage V2 positive to the charge pump CP which then outputs a positive output current Ics to the capacity Cs. The adjustment voltage Vtun present at the terminals of said capacitor Cs increases then, causing the value of the oscillation frequency FLO to increase. This cycle is repeated until the FLO oscillation frequency becomes equal to the reference frequency FREF, the loop then reaching its locked state.
  • phase / frequency detector PD delivering a positive control voltage V1 to the charge pump CP which then controls by means of a negative output current Ics a decrease in the value of the control voltage Vtun, and therefore in the oscillation frequency FLO).
  • said phase / frequency detector PD may advantageously deliver to the charge pump CP a negative control voltage Vx2, in addition to the positive control voltage V2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Control Of Electrical Variables (AREA)
  • Dc-Dc Converters (AREA)

Claims (6)

  1. Gesteuerte Stromquelle (CS1), versehen mit einem Steuereingang für den Erhalt eines Steuersignals (V1) und einem Ausgang für die Abgabe eines Stroms (I1), dessen Wert vom Wert des Steuersignals (V1) abhängt, mit einem Steuermodul (CNT1), versehen mit einem Eingang für den Erhalt des Steuersignals (V1) und einem Ausgang für die Abgabe eines Stromsignals (I1), dessen Wert vom Wert des Steuersignals (V1) abhängt und es ermöglicht, ein Leistungsmodul (PA1) leitend zu machen, wobei in der Stromquelle:
    das besagte Leistungsmodul (PA1) eine Vielzahl sogenannter Leistungstransistoren enthält, parallel angeordnet, und jeder Transistor mit einer Bezugsklemme, einer Transferklemme und einer Polarisationsklemme versehen ist, die Transferklemmen der Leistungstransistoren zusammen mit dem Ausgang der Stromquelle (CS1) verbunden sind, Bezugsklemmen der Leistungstransistoren zusammen mit dem Ausgang des Steuermoduls (CNT1) verbunden sind und die Polarisationsklemmen der Leistungstransistoren, wenn die Stromquelle (CS 1 ) in Betrieb ist, permanent einer Spannung eines vorbestimmten Wertes ausgesetzt sind, was es ermöglicht, die besagten Leistungstransistoren potenziell leitend zu machen,
    das Steuermodul (CNT1) einen ersten Transistor (T1) und einen zweiten Transistor (T1) aufweist, die ein erstes Differenzialpaar bilden und dafür bestimmt sind, an ihren Polarisationsklemmen das Steuersignal (V1) zu erhalten, und einen dritten Transistor (T3), dessen Hauptstromweg in Serie mit einem ersten Widerstand (R11) zwischen einer positiven Versorgungsklemme (VCC) und dem Ausgang des Steuermoduls (CNT1) angeordnet ist, während die Transferklemme des ersten Transistors (T1) mit der positiven Versorgungsklemme (VCC), die Transferklemme des zweiten Transistors (T2) einerseits über einen zweiten Widerstand (R21) mit der positiven Versorgungsklemme (VCC) und andererseits mit der Polarisationsklemme des dritten Transistors (T3) verbunden ist.
  2. Gesteuerte Stromquelle nach Anspruch 1, dadurch gekennzeichnet, dass das Steuermodul (CNT1) außerdem einen vierten Transistor (T4) und einen fünften Transistor (T5) enthält, die ein zweites Differenzialpaar bilden, wobei die besagten Transistoren (t4, T5) dafür bestimmt sind, an ihren Polarisationsklemmen ein sogenanntes Auswahlsignal (Vx1) zu erhalten, die Transferklemme des vierten Transistors (T4) mit der positiven Versorgungsklemme (VCC) verbunden ist, die Transferklemme des fünften Transistors (T5) einerseits über ein Spannungsregelelement (Q5) mit der positiven Versorgungsklemme (VCC) und andererseits über einen dritten Widerstand (R31) mit der Polarisationsklemme des dritten Transistors (T3) verbunden ist.
  3. Gesteuerte Stromquelle nach Anspruch 2, dadurch gekennzeichnet, dass das Spannungsregelelement (Q5) aus einer Diode gebildet wird.
  4. Ladepumpe, versehen mit zwei Steuereingängen für den Erhalt der Steuersignale (V1, V2) und einem Ausgang zur Abgabe eines Ausgangsstroms (OUT), dessen Richtung und Wert von den Werten der Steuersignale (V1, V2) abhängen, dadurch gekennzeichnet, dass sie eine erste Stromquelle (CS1) und eine zweite gesteuerte Stromquelle (CS2) wie in den Ansprüchen 1, 2 oder 3 definiert enthält, wobei die Steuereingänge (V1, V2) dieser Stromquellen die Steuereingänge der Ladepumpe bilden, die Ausgänge (OUT1, OUT2) der ersten und zweiten Stromquelle mit dem ersten und zweiten Zweig eines Stromspiegels verbunden sind und der Ausgang einer der Stromquellen (CS1, CS2) außerdem mit dem Ausgang (OUT) der Ladepumpe verbunden ist.
  5. Ladepumpe nach Anspruch 4, dadurch gekennzeichnet, dass sie außerdem eine Drain-Stromquelle enthält, um, wenn die Ladepumpe in Betrieb ist, ständig einen Strom (Id) abzugeben, dessen Nominalwert gegenüber dem Maximalwert des Ausgangsstroms der Ladepumpe vernachlässigbar ist, während die Drain-Stromquelle (Id) zwischen demjenigen der Ausgänge der Stromquelle, die keine Verbindung mit dem Ausgang (OUT) der Ladepumpe hat, und einer negativen Versorgungsklemme (GND) angeordnet ist.
  6. Empfangsgerät von Funksignalen mit einem Antennen- und Filtersystem, (AF) um den Empfang eines Signals zu ermöglichen, dessen Frequenz (FR) innerhalb eines bestimmten Frequenzbereichs ausgewählt wird, und seine Umwandlung in ein elektronisches Signal, einem sogenannten Funksignal (Vfr), ein Gerät, in dem eine Frequenzwandlung von der ausgewählten Frequenz in eine vorbestimmte Zwischenfrequenz (FI) mit einem Mischer (MX) ausgeführt wird, der einerseits für den Erhalt des Funksignals (Vfr) und andererseits eines Ausgangssignals aus einem lokalen Oszillator (OSC) bestimmt ist, dessen Frequenz (FLO) vom Wert einer Regelspannung (Vtun) festgelegt wird, ein Gerät, das außerdem einen Phasen/Frequenz-Detektor (PD) aufweist, dafür bestimmt, die Frequenz (FLO) des Ausgangssignals des Oszillators (OSC) mit der Frequenz (FREF) eines Bezugssignals (Vref) zu vergleichen, und dafür bestimmt, einer Ladepumpe (CP) die Steuersignale (V1, V2) abzugeben, deren Werte vom Ergebnis des besagten Vergleichs abhängen, wobei der Ausgang der Ladepumpe mit einer Kapazität (Cs) verbunden ist, die zur Erzeugung der Regelspannung (Vtun) an ihren Klemmen vorgesehen ist, dadurch gekennzeichnetes Gerät, dass die Ladepumpe dem Anspruch 4 oder 5 entspricht.
EP99202607A 1998-08-18 1999-08-10 Gesteuerte Stromquelle mit beschleunigtem Umschalten Expired - Lifetime EP0981203B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9810509 1998-08-18
FR9810509 1998-08-18

Publications (2)

Publication Number Publication Date
EP0981203A1 EP0981203A1 (de) 2000-02-23
EP0981203B1 true EP0981203B1 (de) 2004-01-21

Family

ID=9529748

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99202607A Expired - Lifetime EP0981203B1 (de) 1998-08-18 1999-08-10 Gesteuerte Stromquelle mit beschleunigtem Umschalten

Country Status (5)

Country Link
US (1) US6150806A (de)
EP (1) EP0981203B1 (de)
JP (1) JP2000200111A (de)
KR (1) KR20000017372A (de)
DE (1) DE69914266T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6445170B1 (en) * 2000-10-24 2002-09-03 Intel Corporation Current source with internal variable resistance and control loop for reduced process sensitivity
US6448811B1 (en) 2001-04-02 2002-09-10 Intel Corporation Integrated circuit current reference
US6507225B2 (en) 2001-04-16 2003-01-14 Intel Corporation Current mode driver with variable equalization
US6522174B2 (en) * 2001-04-16 2003-02-18 Intel Corporation Differential cascode current mode driver
US6791356B2 (en) * 2001-06-28 2004-09-14 Intel Corporation Bidirectional port with clock channel used for synchronization
TWI435654B (zh) * 2010-12-07 2014-04-21 安恩國際公司 雙端電流控制器及相關發光二極體照明裝置
CN112953227B (zh) * 2021-05-14 2021-08-10 上海芯龙半导体技术股份有限公司 开关电源电路、芯片及系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740766A (en) * 1987-09-04 1988-04-26 Tektronix, Inc. Precision tracking current generator
SE465398B (sv) * 1990-01-15 1991-09-02 Ericsson Telefon Ab L M Foerfarande och anordning foer frekvenssyntes
FR2688905A1 (fr) * 1992-03-18 1993-09-24 Philips Composants Circuit miroir de courant a commutation acceleree.
US5412309A (en) * 1993-02-22 1995-05-02 National Semiconductor Corporation Current amplifiers
BE1007853A3 (nl) * 1993-12-03 1995-11-07 Philips Electronics Nv Bandgapreferentiestroombron met compensatie voor spreiding in saturatiestroom van bipolaire transistors.
US5453680A (en) * 1994-01-28 1995-09-26 Texas Instruments Incorporated Charge pump circuit and method
FR2717019A1 (fr) * 1994-03-02 1995-09-08 Philips Composants Dispositif oscillateur verrouillé en phase.
US5508702A (en) * 1994-06-17 1996-04-16 National Semiconductor Corp. BiCOMS digital-to-analog conversion
US5506543A (en) * 1994-12-14 1996-04-09 Texas Instruments Incorporated Circuitry for bias current generation
JP2953383B2 (ja) * 1996-07-03 1999-09-27 日本電気株式会社 電圧電流変換回路
JP3334548B2 (ja) * 1997-03-21 2002-10-15 ヤマハ株式会社 定電流駆動回路
US5883507A (en) * 1997-05-09 1999-03-16 Stmicroelectronics, Inc. Low power temperature compensated, current source and associated method

Also Published As

Publication number Publication date
US6150806A (en) 2000-11-21
EP0981203A1 (de) 2000-02-23
DE69914266D1 (de) 2004-02-26
KR20000017372A (ko) 2000-03-25
JP2000200111A (ja) 2000-07-18
DE69914266T2 (de) 2004-11-18

Similar Documents

Publication Publication Date Title
EP0905908B1 (de) Ausgangsstufe einer Ladungspumpe für geringe Ströme und Demodulator mit einer solchen Pumpe
FR2715012A1 (fr) Synthèse en fréquence par fractions N à correction d'erreur résiduelle et procédé associé.
FR2623307A1 (fr) Source de courant a deux bornes avec compensation de temperature
EP0562904A1 (de) Verfahren und Vorrichtung zur Regelung einer Verzögerung über mehrere Verzögerungsbereiche
EP0981203B1 (de) Gesteuerte Stromquelle mit beschleunigtem Umschalten
EP1925079B1 (de) Stromschalter mit durch eine niederspannung gespeisten differenztransistorpaaren
EP0851588B1 (de) Ladungspumpenschaltung für die Frequenzregelschleife eines Frequenzsynthetisierers
EP0723160A1 (de) Für Technologie und Temperatur kompensierte Spannungsdetektionsschaltung
EP0561456B1 (de) Schneller Schaltstromspiegel
EP0695035A1 (de) Mehrfachvergleichs-A/D-Wandler unter Anwendung des Interpolationsprinzips
EP4038476B1 (de) Vorrichtung zur erzeugung einer versorgungs-/polarisationsspannung und eines taktsignals für eine synchrone digitale schaltung
FR2815198A1 (fr) Circuit a verrouillage de phase
EP1081848B1 (de) Frequenzumsetzer mit unterdrücktem Lecksignal aus einem lokalen Oszillator und Verfahren
CH644231A5 (fr) Circuit a gain variable commande par une tension.
EP0928060A1 (de) Gleichspannungswandler mit verbessertem Wirkungsgrad
EP0998031A1 (de) Stromverstärker mit niedriger Eingangsimpedanz
FR2813481A1 (fr) Modulateur de frequence a faible bruit ayant une frequence porteuse variable
FR2466137A1 (fr) Convertisseur de signaux
EP0645884B1 (de) Verstärkerkette in Strommode, Operationsverstärker, Verstärkungszelle und zugehöriges Verstärkerelement
EP1352302A1 (de) Spannungsregler mit reduzierter statischen verstärkung in offenem regelkreis
FR2843250A1 (fr) Convertisseur numerique-analogique comprenant des moyens pour ameliorer la linearite de conversion.
FR2581814A1 (fr) Circuit de sortie symetrique pour un amplificateur en circuit integre
FR2754959A1 (fr) Comparateur de phase a tres faible offset
EP0772359B1 (de) Filtervorrichtung zur Verarbeitung einer Vielzahl von Kanälen in einem Kabelfernsehverteilungssystem
FR2892872A1 (fr) Filtre passe-bande complexe

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20000823

AKX Designation fees paid

Free format text: DE FR GB

17Q First examination report despatched

Effective date: 20020916

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REF Corresponds to:

Ref document number: 69914266

Country of ref document: DE

Date of ref document: 20040226

Kind code of ref document: P

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20040407

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20040826

Year of fee payment: 6

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20040830

Year of fee payment: 6

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20041015

Year of fee payment: 6

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20041022

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050810

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060301

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20050810

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060428

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20060428