[go: up one dir, main page]

EP0927415A1 - Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit - Google Patents

Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit

Info

Publication number
EP0927415A1
EP0927415A1 EP97912402A EP97912402A EP0927415A1 EP 0927415 A1 EP0927415 A1 EP 0927415A1 EP 97912402 A EP97912402 A EP 97912402A EP 97912402 A EP97912402 A EP 97912402A EP 0927415 A1 EP0927415 A1 EP 0927415A1
Authority
EP
European Patent Office
Prior art keywords
electrodes
display
period
groups
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97912402A
Other languages
German (de)
English (en)
Inventor
Roy Van Dijk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP97912402A priority Critical patent/EP0927415A1/fr
Publication of EP0927415A1 publication Critical patent/EP0927415A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/2029—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having non-binary weights
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0266—Reduction of sub-frame artefacts
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/2803—Display of gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/298—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using surface discharge panels

Definitions

  • the invention relates to a circuit for driving a flat panel display as defined in the precharacterizing part of claim 1.
  • the invention also relates to a flat panel display apparatus with a flat panel display and such a circuit for driving the flat panel display, and to a method of driving a flat panel display.
  • a PDP comprises a plurality of cells formed at cross points of scan electrodes and data electrodes which are arranged orthogonal to the scan electrodes.
  • a picture to be displayed has a frame rate of 60 Hz. Each frame of the picture to be displayed is divided in a plurality of sub frames. Each sub field comprises an address period and a display period. In each address period, the cells to be lit during the subsequent display period are addressed by sequentially selecting the scan electrodes and supplying appropriate data to the data electrodes for each selected scan electrode. In this way a desired charge is stored in the cells to be lit.
  • each display period sustain pulses are supplied to all the cells to lit the cells in which the desired charge is stored.
  • the brightness of a lit cell is determined by the number or the frequency of the sustain pulses.
  • each display period has a different number of sustain pulses, and the frequency of the sustain pulses is equal for every display period.
  • the number of sustain pulses of the display periods essentially have a ratio of 1:2:4:8: .... Therefore, the duration of the display periods have also said ratio.
  • the picture to be displayed is represented by binary coded data words of which each bit corresponds to one of the sub frames such that the length of the display period of that sub field is in accordance with the weight of the data bit in the data word.
  • the cell is lit during the display period of a certain sub field if the bit of the data word associated with this certain sub field indicates such. So, the bits of the data word determine during which sub frames of a frame the cell produces light.
  • the visual brightness of each cell is determined by the number of sustain pulses accumulated during the entire frame period.
  • a first aspect of the invention provides a circuit for driving a flat panel display as defined in claim 1.
  • a second aspect of the invention provides a flat panel display apparatus with a flat panel display and a circuit for driving the flat panel display as defined in claim 10.
  • a third aspect of the invention provides a method of driving a flat panel display as defined in claim 11.
  • An AC plasma display is a bilevel display with a memory function, i.e. it can only turn pixels on or off.
  • a prime sequence (addressing period) is necessary.
  • a pixel that should turn on is conditioned, in such a way, that it turns on when a voltage is put across the scan and sustain electrodes (during the display period). This is done for all pixels in a display that should turn on.
  • the grayscale itself is now generated in such a way that the luminance value is divided into several subfields with various weights.
  • the scan and sustain voltage is put on the display (the sustain period) and all primed pixels turn on.
  • the weight of a subfield determines how long the pixels are turned on.
  • the luminance value of a pixel is determined by the input byte of Red. Green or Blue (RGB) .
  • RGB Red. Green or Blue
  • the weight of a bit corresponding to the subfield weight determines whether this pixel is primed, i.e. whether this pixel is turned on during the sustain period.
  • the above described sub field order is a preferred embodiment of the invention. It is also possible to reduce the flicker if groups of two or more consecutive rows each with a same first sub field order alternate with groups of two or more consecutive rows each with a same second sub field order. It is also possible to repeat a group of rows each having a different sub field order. For example, a group of four successive rows is repeated, each of the rows out of the group of four has a different sub field order. Although an optimal reduction of the flicker is obtained if the position of the sub fields with the highest bit weights is selected to be in anti-phase, any different position of these sub fields reduces the flicker.
  • JP-A-07271325 discloses a circuit for selecting different sub field orders during successive fields. Due to the different position of the sub fields in subsequent fields, the distance in time between corresponding sub fields varies, thereby deteriorating the flicker reduction. As in one field the same sub field order is supplied to every scan electrode, the scan electrodes need not be connected in groups, and the data bit order need not be changed within a field.
  • This SID publication is concerned with signal processing which decodes the binary coded data words into drive signals which randomly select the right sub fields in successive frames to obtain the light output corresponding to the data word. In this way, the light pulse occurrence is randomised in moment of occurrence. It is disclosed that a certain data value can be generated by the sub fields belonging to A, or by selecting one of the four sub fields D. It is further disclosed that from horizontal line to line in subsequent fields the order of the four sub fields D and the sub field A may be changed. There is no disclosure of any hardware measure enabling a different sub field order for different lines within one and the same field.
  • this publication discloses that the visibility of dynamic false contours is minimized by selecting a different sub field order in successive field periods. This is not an effective measure to reduce flicker.
  • different sub field orders are applied to different groups of rows in a same field period thereby reducing the flicker. It has to be noticed that it is additionally possible to select different sub field orders in successive field periods for one or each of the groups of rows. In this way, the invention provides a solution to decrease the amount of flicker as well the visibility of the false contours.
  • a display element is formed by the crossing of a scan electrode and a data electrode. In the prior art, this type of display is referred to as opposed-discharge type.
  • a plasma panel sub-pixel (also referred to as cell or display element) is formed by the crossing of two row electrodes and a column electrode.
  • the two row electrodes extend in the row direction, they are referred to as scan electrodes and sustain electrodes.
  • Plasma channels may be aligned with the row or the column electrodes. Plasma cells may be used instead of plasma channels. In the prior art, this type of display is referred to as surface-discharge type.
  • the flicker is reduced with a large amount because the different sub field orders occur in consecutive lines and thus are optimally integrated by the eye.
  • the flicker is reduced with a large amount because sub fields which have a same bit weight are applied to one of the groups of the scan electrodes shifted over about a half field period in time with respect to the other group of scan electrodes. So, the eye sees the light pulses associated with these sub fields with double field frequency.
  • An embodiment as defined in claim 7 has the advantage that common circuitry can be used to address the whole PDP for every sub field, independent on the length of the display period of a sub field.
  • An embodiment as defined in claim 8 has the same advantage as the embodiment defined in claim 7. Further, let us assume that the sub field order of two consecutive rows is different. This implies that after the common addressing period of a certain sub field in the field, the duration of the subsequent display period differs for the two rows. To be able to again have a common addressing period for the next sub field, an idle period occurs for the row with the shortest display period. This lost idle time is minimal if the duration of the display periods corresponding to a same addressing period differ minimally. This is the case if the weights associated with the corresponding display periods differ minimally. In an embodiment of the invention as claimed in claim 9, the weight of the sub fields corresponds to the weight of the bits of the data word, such that a minimal amount of sub fields occurs.
  • Fig. 1 schematically illustrates a circuit for driving a PDP of a opposed- discharge type in a sub field mode as known from the prior art
  • Fig. 2 schematically illustrates a circuit for driving a PDP of a surface- discharge type in a sub field mode as known from the prior art
  • Fig. 3 schematically illustrates a basic sub-pixel structure of a surface- discharge type PDP
  • Fig. 4 shows voltage waveforms between a scan electrode and a sustain electrode of the prior art surface-discharge type PDP
  • Figs. 5 A and 5B show the moments of occurrence of the light pulses in subsequent fields if the least and the most significant bit are on
  • Fig.5 A the sub field order is changed in subsequent fields according to the prior art
  • Fig 5B the sub field order is changed in subsequent rows according to an embodiment of the invention
  • Figs. 6 A and 6B show a schematic representation of the address periods and the display periods of the sub fields of rows with a different sub field order, whereby the address periods coincident and the sub field period has a fixed duration
  • Figs. 7 A and 7B show a schematic representation of the address periods and the display periods of the sub fields of rows with a different sub field order, whereby the address periods coincident and the sub field periods differ,
  • Fig. 8 shows a block diagram of a circuit for implementing the sub field bit shifts
  • Fig. 9 shows the interconnection of the scan electrodes and the sustain electrodes enabling a different sub field order for even and odd rows according an embodiment of the invention.
  • Fig. 1 schematically illustrates a circuit for driving a PDP of a opposed- discharge type in a sub field mode as known from the prior art.
  • Two glass panels (not shown) are arranged opposite to each other.
  • Data electrodes D are arranged on one of the glass panels.
  • Scan electrodes Sc are arranged on the other glass panel such that the scan electrodes Sc and the data electrodes D are perpendicular.
  • Display elements (for example plasma cells) C are formed at the cross points of the data electrodes D and the scan electrodes Sc.
  • a timing generator 1 receives display information Pi to be displayed on the PDP.
  • the timing generator 1 divides a field period Tf of the display information Pi into a predetermined number of consecutive sub field periods Tsf (see Fig. 4).
  • a sub field period Tsf comprises an address period Tp and a display period Ts.
  • a scan driver 2 supplies pulses to the scan electrodes Sc for successively selecting the scan electrodes one by one
  • a data driver 3 supplies data di to the data electrodes D to write the data di to the display elements C associated with the selected scan electrode Sc.
  • the display elements C associated with the selected scan electrode Sc are preconditioned.
  • a sustain generator 5 generates sustain pulses Sp which are supplied to the display elements C via the scan driver 2. It is also possible to supply the sustain pulses Sp to the data driver 3 or both to the scan driver 2 and the data driver 3.
  • the display elements C which are preconditioned during the address period Tp to produce light during the display period Ts will produce an amount of light depending on a number or a frequency of the sustain pulses Sp.
  • the timing generator 1 further associates a fixed order of weight factors Wf to the sub field periods Sf in every field period Tf .
  • the sustain pulse generator 5 is coupled to the timing generator 1 to supply a number or a frequency of the sustain pulses Sp in conformance with the weight factors Wf such that an amount of light generated by a preconditioned display element C corresponds to the weight factor Wf.
  • a sub field data generator 4 performs an operation on the display information Pi such that the data di is in conformance with the weight factors Wf.
  • Fig. 2 schematically illustrates a drive circuit for driving a PDP of a surface-discharge type in a sub field mode as known from the prior art.
  • the surface- discharge PDP differs from the opposed-discharge PDP in that an extra scan electrode Su (referred to as sustain electrode) is arranged in parallel with each scan electrode Sc.
  • the circuit of Fig. 2 differs from the circuit shown in Fig. 1 in that a sustain driver 6 is added to drive the sustain electrodes Su.
  • the sustain pulse generator 5 also supplies the sustain pulses Sp to the sustain driver 6. Same elements in Fig. 2 and Fig. 1 are indicated by the same references.
  • the scan driver selects the scan electrodes Sc one by one.
  • the data driver 3 supplies for each selected scan electrode Sc the data di to precondition the display elements C associated with the selected scan electrode Sc.
  • the sustain driver 6 together with the scan driver 2 generates sustain pulses Sp between the sustain electrodes Su and the scan electrodes Sc.
  • the picture elements C which are preconditioned to produce light will do so. It is also possible to supply the sustain pulses Sp to either the scan driver 2 or the sustain driver 6.
  • Fig. 3 schematically illustrates a basic AC plasma sub-pixel of the surface-discharge type PDP.
  • the plasma sub-pixel or display element C is formed by the crossing of two row electrodes Sc, Su and a column electrode Co.
  • the two row electrodes Sc, Su are situated at the bottom of the sub-pixel and are referred to as scan electrode Sc and sustain electrode Su.
  • the column electrode Co is situated on top of the sub pixel and is referred to as data electrode D.
  • Plasma P is arranged between the column electrode Co and the two row electrodes Sc, Su via respective dielectric layers Di.
  • the plasma P is insulated from the dielectric layers Di by MgO layers Mg.
  • the sustain electrodes Su are interconnected for all rows of the PDP panel.
  • the scan electrodes Sc are connected to row IC's and scanned during the addressing or priming phase.
  • the column electrodes Co are operated by column IC's.
  • the plasma cells C are operated in three modes:
  • Plasma cells C are conditioned such that they will be in an on or off state during sustain mode. Since a plasma cell C can only be fully on or off, several prime phases are required to write all bits of a luminance value. Plasma cells C are selected on a row-at-a-time basis and the voltage levels on the columns Co will determine the on/off condition of the cells. If a luminance value is represented in 6 bits, then also 6 subfields are defined within a field.
  • Fig. 4 shows voltage waveforms between scan electrodes Sc and sustain electrodes Su of the known surface-discharge type PDP. Since there are three modes, the corresponding time sequence is indicated as Te,bx (erase mode for bit-x subfield SFi), Tp,bx (prime mode for bit-x subfield SFi) and Ts,bx (sustain mode for bit-x subfield SFi). The number of sustain pulses will vary in time to limit the power dissipation so a residual time Tr is taken into account to match the field frequency again.
  • Fig. 4 shows the result of a measurement of the differential voltage between a scan and the common sustain electrodes Sc, Su when this voltage is measured over a field.
  • Fig. 4 only gives a rough indication of what happens in a field period Tf.
  • Prime and erase sequences in each subfield SFi are the same.
  • the duration of the sustain sequence Ts.bx depends on the weight of the individual bits and contains a number alternating pulses with the same frequency. When the power dissipation of the panel is too high, the number of alternating pulses during sustain time Ts.bx will be less. This results in shorter sustain periods Ts,bx in the subfields SFi and the residual time Tr will increase to match the field frequency.
  • Table 1 gives an overview of the panel's timing when an over-all black (level 0) or white (level 63) picture is displayed. As can be seen from the table, the prime and erase modes are not changed when the power dissipation is limited by the electronics. The number of sustain pulses is roughly halved when a complete white picture is displayed. The number of sustain pulses is also given in the table (pulse count can be found between brackets in the Ts-rows) . Equation 1 can be used to calculate the sustain time Ts,bx in a subfield SFi.
  • variable ⁇ stands for pulse count, printed in the table. Each pulse takes 9.6 ⁇ s and ⁇ pulses are always preceded by a specified sequence of 19 ⁇ s.
  • Figs. 5 A and 5B show the moments of occurrence of light pulses Lpi,n in subsequent field periods Tf,n if the least and the most significant bit are on.
  • three subsequent field periods are denoted with Tf,n-1, Tf,n, and Tf,n+ 1.
  • the three to this field periods corresponding fields are referred to as fields n-1, n, and n+ 1.
  • the sub field periods Tsf.bi are referred to by the numerals 0 to 5.
  • These numerals indicate the bit weight of the sub fields Sfi: The least significant bit is associated with sub field 0, the most significant bit is associated with sub field 5.
  • Flicker will be reduced between the fields n and n-f- 1 as the time gap between the moments of occurrence of the sub fields 5 of the most significant bits is shorter than a field period Tf .
  • the time gap between the sub fields 5 of the most significant bits in the fields n-1 and n is still a field period Tf. This gives rise to flicker.
  • Fig. 5B the sub field order in two consecutive rows rn and rn-1 is shown, each for 3 consecutive fields n-1, n, n+ 1.
  • the sub field order of the rows rn and rn- 1 is selected different such that the sub field 5 of the most significant bit occurs at different instants within each of the fields n-1, n, n+ 1.
  • the eye detects a double repetition frequency of the light pulses associated with the most significant bits. The flicker is reduced drastically.
  • Figs. 6 A and 6B show a schematically representation of the address periods Tp,bx and the display periods Ts,bx of the sub fields 0 to 5 of rows rn-1 and rn with a different sub field order, whereby the address periods Tp,bx coincident and all sub field periods Tsf,n have a fixed duration.
  • Both Figs. 6 A and 6B show the sub field order during a same field for two consecutive rows rn-1 and rn.
  • the erase periods Te,bx are shown as small shaded bars
  • the address or prime periods Tp,bx are represented by the triangle shaped shaded areas
  • the display or sustain periods Ts,bx are shown as black areas.
  • the addressing (prime) and erase period are Tp,bx; Te,bx are common for the entire display.
  • the duration of the sustain period Ts,bx is determined by the weight of the specific subfield ⁇ .
  • the weight of a subfield ⁇ determines the number of sustain pulses SP that are given for that sustain period Ts,bx. This is important to notice since it, therefore, means that time is lost when the sustain period Ts,bx of the odd rows rn-1 is shorter than for the even rows rn or vice versa.
  • the sustain period Ts,bx is over for the odd or even rows rn-1, rn, no sustain pulses are given for the specific odd or even rows rn-1, rn.
  • the addressing (prime) period Tp,bx and the erase period Te,bx are done in the conventional manner, i.e. for the entire display.
  • a sustain period Ts,bx can only start after an erase and addressing period Tp,bx; Te,bx has been completed.
  • the start of the sustain period Ts,bx of a subfield ⁇ with a specific weight of the odd rows rn-1 should be positioned with a half row offset compared to the even rows r,n (or vice versa).
  • the flicker frequency is doubled from 50/60 to 100/120Hz and this frequency is not visible for the eye.
  • this condition is not met, a non optimal flicker reduction can be expected. As long as the lowest flicker component is higher than about 80Hz, it is still above the flicker fusion frequency (the frequency which makes flicker just noticeable).
  • 80Hz results in a time period of 12.5ms. It is attempted to reduce the flicker for all subfield weights, thus the 12.5ms distance is required for all subfield weights. It is questionable whether this is necessary for the lowest subfield weights. This must be found out by experimenting. It is also attempted to reduce the flicker for an object which changes slightly in luminance. Suppose an object has a luminance of bit weight 7 (128) and changes to 127. It is now also attempted that the time gap between switching on the new highest bit weight (bit 6) of that object and the former highest bit weight (b7) is smaller than 12.5ms, but also that the highest subfield has a time gap between two sustain periods of the same bit weight smaller than 12,5ms. This time gap also take place in two successive frames Tf. This object must be at least larger than the height of two rows rn.
  • rn-1 When this is not the case the change in subfield order between two rows rn, rn-1 does not result in a reduction of the large area flicker, but probably the flicker is not noticeable since the area is too small.
  • One solution for distributing the sub fields 0 to 5 with the various weights for the odd and even rows rn-1, rn is to reserve the most significant bit (MSB) sub field length Tf,5 for all sub fields 0 to 5. This implies that any desired sub field order can be implemented. It is possible to reach the optimum flicker frequency of 100 or 120 Hz for all bit weights.
  • a disadvantage is that in all sub fields x other than that with the highest weight a lot of time is wasted. Consequently, the maximum number of sustain pulses in each sustain period Ts,bx is reduced and therefore the peak white level becomes lower.
  • FIG. 7 A and 7B Another solution for distributing the sub fields x over the odd and even rows rn-1, rn is shown in Figs. 7 A and 7B.
  • Figs. 7 A and 7B show a schematic representation of the address periods
  • a next sub field SFx is started after the sustain period Ts,bx with the longest duration in the preceding sub field SFx-1. So, in two consecutive rows rn-1, rn, two corresponding sub fields SFx have a same duration which is determined by the sub field SFx with the longest duration.
  • the corresponding sustain periods Ts,bx in the odd and even rows rn-1, rn differ minimally in weight (the MSB corresponds to the MSB-1, and so on). In this situation a minimal amount of time is wasted.
  • Fig. 8 shows a block diagram of a circuit for implementing the sub field bit shifts. This is a possible implementation of the sub field SFx order change by only three bit shifts. It is implemented from a parallel-in to a parallel out method. This is only one implementation, other implementations are possible.
  • An input register Rin stores the six data bits bi of a data word of the received display information Pi. The data bits bi in the input register Rin are transferred to a shift register Sr. Every row rn, the shift register Sr is clocked three times to shift the data bits bi over three positions. The shifted data bits bi are transferred to an output register Rout to be used during one row rn.
  • Fig. 9 shows the interconnection of the scan electrodes See, Sco and the sustain electrodes Sue, Suo enabling a different sub field order for even and odd rows rn, rn- 1 according an embodiment of the invention.
  • both the scan and sustain electrodes Sc,Su are divided into two groups with the odd scan and sustain electrodes Sco, Suo into one group and the even scan and sustain electrodes See, Sue in the other group.
  • the entire screen PD is primed with the odd rows rn-1 primed for a subfield SF ⁇ with a bit weight of subfield order ⁇
  • the even rows rn are primed for a subfield SF ⁇ with a bit weight of subfield order y.
  • the subfield order ⁇ and y may only differ by three bit shifts.
  • the two groups of rows rn, rn-1 are sustained according to the weight of the subfield SF ⁇ where they were primed for.
  • Subfield order ⁇ gives for example a sustain pulses whereas subfield order y results in b sustain pulses.
  • the subfield order for the current field is ⁇ for the odd rows rn-1 and y for the even rows rn
  • the number of sustain pulses at each bit weight is according to Table 2.
  • the number of sustain pulses in the first subfield SFI is 43 for the odd rows rn-1 and 4 for the even rows rn.
  • the odd rows rn-1 generates 87 sustain pulses whereas the even rows rn generates 10 sustain pulses and so on.
  • the sustain pulses Sp for the even rows rn are supplied by a voltage source Vse arranged between a first group of interconnected even scan electrodes See on the one hand and a first group of interconnected associated even sustain electrodes Sue on the other hand.
  • the sustain pulses Sp for the odd rows rn-1 are supplied by a voltage source Vso arranged between a second group of interconnected odd scan electrodes See on the one hand and a second group of interconnected associated odd sustain electrodes Sue on the other hand. It is also possible to supply each of the groups of scan electrodes See, Sco and sustain electrodes Sue, Suo with a separate voltage.
  • the prime phase and erase phase are performed in common for all rows in a well known matter. The sustaining during a series of sub fields Sfi for all rows is well known in the art.
  • the amount of light produced during a sustain period may also be adapted by controlling the amplitude of the sustain pulses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

On décrit un panneau d'affichage plat qui comprend une pluralité d'éléments d'affichage (C) disposés en rangées et en colonnes dans une matrice, et des électrodes (Sc, D, Su) associées aux éléments d'affichage (C) dans une rangée ou une colonne. Le panneau d'affichage plat (PD) est attaqué en mode sous-champ, dans lequel une période de champ (Tf) d'une information graphique (Pi) est divisée (1) en périodes consécutives de sous-champ (Tsf) qui comportent des périodes d'adresse (Tp) précédant une période d'affichage (Ts). A l'intérieur d'une période de champ (Tf), un ordre préétabli de facteurs de pondération (Wf) associés chacun à une période d'affichage (Ts) correspondante est généré (1). Les électrodes (Sc, D, Su) sont interconnectées dans au moins deux groupes (Sce, Sco; Sue, Suo). Des signaux d'attaque correspondant aux facteurs de pondération (Wf) sont transmis (2, 3, 4, 5; 2, 3, 4, 5, 6) à chacun desdits deux groupes. A l'intérieur d'une même période de champ (Tf), l'ordre préétabli de facteurs de pondération (Wf) est adapté pour associer un ordre différent de facteurs de pondération (Wf) aux périodes d'affichage (Ts) desdits deux groupes d'électrodes (Sce, Sco, Sue, Suo).
EP97912402A 1997-03-07 1997-12-01 Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit Withdrawn EP0927415A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP97912402A EP0927415A1 (fr) 1997-03-07 1997-12-01 Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP97200691 1997-03-07
EP97200691 1997-03-07
PCT/IB1997/001488 WO1998039762A1 (fr) 1997-03-07 1997-12-01 Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit
EP97912402A EP0927415A1 (fr) 1997-03-07 1997-12-01 Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit

Publications (1)

Publication Number Publication Date
EP0927415A1 true EP0927415A1 (fr) 1999-07-07

Family

ID=26146217

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97912402A Withdrawn EP0927415A1 (fr) 1997-03-07 1997-12-01 Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit

Country Status (2)

Country Link
EP (1) EP0927415A1 (fr)
WO (1) WO1998039762A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4703892B2 (ja) * 2001-06-15 2011-06-15 パナソニック株式会社 ディスプレイパネルの駆動方法
EP1359749A1 (fr) * 2002-05-04 2003-11-05 Deutsche Thomson-Brandt Gmbh Mode d'affichage à balayage multiple pour un panneau d'affichage à plasma
EP1359564B1 (fr) * 2002-05-04 2005-11-09 Thomson Licensing Affichage à balayage multiple sur un panneau d'affichage à plasma
KR100911006B1 (ko) * 2006-09-14 2009-08-05 삼성에스디아이 주식회사 소음을 줄이기 위한 방전 디스플레이 패널의 구동 방법
KR100844769B1 (ko) * 2006-11-09 2008-07-07 삼성에스디아이 주식회사 유기전계발광 표시장치의 구동방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475448A (en) * 1993-03-25 1995-12-12 Pioneer Electronic Corporation Driving method for a gas-discharge display panel
JPH0854852A (ja) * 1994-08-10 1996-02-27 Fujitsu General Ltd ディスプレイパネルの中間調画像表示方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3259253B2 (ja) * 1990-11-28 2002-02-25 富士通株式会社 フラット型表示装置の階調駆動方法及び階調駆動装置
JP3489884B2 (ja) * 1994-02-08 2004-01-26 富士通株式会社 フレーム内時分割型表示装置及びフレーム内時分割型表示装置における中間調表示方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475448A (en) * 1993-03-25 1995-12-12 Pioneer Electronic Corporation Driving method for a gas-discharge display panel
JPH0854852A (ja) * 1994-08-10 1996-02-27 Fujitsu General Ltd ディスプレイパネルの中間調画像表示方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO9839762A1 *

Also Published As

Publication number Publication date
WO1998039762A1 (fr) 1998-09-11

Similar Documents

Publication Publication Date Title
US6424325B1 (en) Circuit for and method of driving a flat panel display in a sub field mode and a flat panel display with such a circuit
KR100256003B1 (ko) 화상의 중간 계조 표시 방법 및 표시 장치
US6297788B1 (en) Half tone display method of display panel
US7375702B2 (en) Method for driving plasma display panel
KR100318647B1 (ko) 계조표시시스템
US6323880B1 (en) Gray scale expression method and gray scale display device
US20010040536A1 (en) Display and method of driving the display capable of reducing current and power consumption without deteriorating quality of displayed images
KR100799746B1 (ko) 디스플레이 디바이스 상에 디스플레이하기 위한 비디오화상 처리 방법 및 비디오 화상 처리 장치
JP4162434B2 (ja) プラズマディスプレイパネルの駆動方法
KR100225902B1 (ko) 불규칙 어드레싱에 의한 표시 시스템의 계조 조정 방법
JP4126577B2 (ja) 表示装置及び表示装置の駆動方法
EP1283514B1 (fr) Appareil d'affichage à plasma
JP2002297090A (ja) Ａｃ型ｐｄｐの駆動方法および駆動装置
US20010017612A1 (en) Method of displaying images on a matrix display device
KR20000028597A (ko) 디스플레이구동방법및그장치
KR100465547B1 (ko) 플라즈마 디스플레이패널의 구동방법 및 플라즈마디스플레이 장치
US20010054992A1 (en) Plasma display panel and method of driving the same capable of increasing gradation display performance
US6400342B2 (en) Method of driving a plasma display panel before erase addressing
WO1998039762A1 (fr) Circuit et procede d'attaque d'un panneau d'affichage plat en mode sous-champ, et panneau d'affichage plat equipe d'un tel circuit
JP2006146159A (ja) プラズマ表示装置及びその駆動方法
US6809707B1 (en) Displaying interlaced video on a matrix display
JPH09305142A (ja) ディスプレイ装置
US20070216609A1 (en) Apparatus and method of driving plasma display panel
KR20080065525A (ko) 플라즈마 디스플레이 패널 구동 방법 및 플라즈마디스플레이 장치
JPH11282402A (ja) プラズマディスプレイ駆動方法及びその装置

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19990311

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060104