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EP0462708A2 - Mémoire vidéo à accès aléatoire - Google Patents

Mémoire vidéo à accès aléatoire Download PDF

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Publication number
EP0462708A2
EP0462708A2 EP91304736A EP91304736A EP0462708A2 EP 0462708 A2 EP0462708 A2 EP 0462708A2 EP 91304736 A EP91304736 A EP 91304736A EP 91304736 A EP91304736 A EP 91304736A EP 0462708 A2 EP0462708 A2 EP 0462708A2
Authority
EP
European Patent Office
Prior art keywords
access memory
memory portion
data transfer
columns
serial access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91304736A
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German (de)
English (en)
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EP0462708B1 (fr
EP0462708A3 (en
Inventor
Roderick Michael Peters West
Todd Williams
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of EP0462708A3 publication Critical patent/EP0462708A3/en
Application granted granted Critical
Publication of EP0462708B1 publication Critical patent/EP0462708B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM

Definitions

  • the present invention relates to memory devices capable of high speed data transfer to a peripheral device, such as a raster display.
  • VRAMs Video Random Access Memories
  • a VRAM is essentially a conventional dynamic random access memory (DRAM) with the addition of a second port where data may be accessed serially.
  • a VRAM consists of a random access memory (RAM) portion and a serial access memory (SAM) portion with transfer gates which allow data to pass between the RAM and the SAM.
  • the SAM array usually has the memory capacity of one row of the RAM array. A full row of memory data may be passed between RAM and SAM in a single data transfer access.
  • the RAM port and the SAM port may be operated asynchronously and independently except when the data transfer between the RAM and the SAM is taking place.
  • This independent and asynchronous operation of the two ports finds application in the video displays of computer systems where the RAM port is used to update the contents of display memory and the serial port is used to provide data to be rastered onto the display.
  • the RAM port may be operated at the frequency of the computer system and the SAM port at a frequency dictated by the requirements of the raster display. Since the SAM array usually has the capacity of a single row of display data, it must be continually reloaded with new rows of display data during the time of the display frame. In general, each new row of display data is obtained from a row whose index is one greater than that of the previous row. The reloading of the SAM array with new rows of display data from the RAM array is achieved by performing data transfer cycles at the RAM port.
  • a "Real Time Data Transfer” is a critically timed real-time access, requiring synchronisation between the RAM and the SAM ports, and can be very wasteful of RAM port bandwidth, a crucial aspect in many display memory subsystems. Additionally such critically timed real time accesses may require potentially complex and high-speed circuitry to synchronise and control them. The avoidance of such events is therefore highly desirable.
  • the conventional method of avoiding mid-line reloads involves a number of restrictions upon how the contents of display memory are mapped onto the display screen. These restrictions are usually first, to use a fixed start address for the display data on the first horizontal scan line of the display frame, secondly to use a fixed address increment to generate the start address of each subsequent horizontal scan-line and thirdly to use a horizontal scan-line length which requires an amount of display data not greater than the capacity of the SAM arrays of the VRAMs in the display memory subsystem. All these restrictions must be satisfied to avoid a mid-line reload. For a general purpose graphics adapter or display memory subsystem these restrictions cannot be applied.
  • Second generation VRAMs were enhanced with the ability to transfer half a row of random access memory into half of the SAM while the other half of the SAM is being scanned out to the display.
  • This means of avoiding real-time data transfers is found on some modern 1 Mb VRAMS, for example a 1 Mbit multiport DRAM manufactured by the Toshiba Corporation and the memories described in the US patents 4,825,411 and 4,855,959 incorporate the so-called "Split Register” feature.
  • These VRAMS have the SAM array divided into two halves, which can be loaded independently by so-called “Split Register Data Transfers” whereby one half of the SAM is loaded while the other half is active.
  • an output status pin is provided to indicate the half of the SAM being scanned out.
  • This feature goes some way to alleviating the problem, but, however, it does not make full and efficient use of the SAM array capacity and can potentially result in twice as many data transfer accesses than would be required by a VRAM without the feature.
  • the invention provides a means of eliminating their real-time nature and thus the need for such critical timing. By removing the need for real-time VRAM data transfers, the invention eliminates the need for the potentially complex and high-speed circuitry required to synchronise and control such data transfers, and eliminates the potentially wasteful use of RAM port bandwidth in the synchronisation of such data transfers.
  • a memory device comprising: a random access memory portion arranged with the memory locations in rows and columns; a serial access memory portion; a serial access means allowing external access to the serial access memory portion; transfer gates connecting the random access memory portion and the serial access memory portion for carrying out data transfer therebetween; control logic for controlling the data transfer between the random access memory portion and the serial access memory portion; characterised in that the control logic is adapted to activate transfer gates corresponding to at a least a first selected set of columns for data transfer between memory locations in the selected set of columns of at least one row of the random access memory portion and the serial access memory portion.
  • the control logic can be adapted to activate transfer gates corresponding to a first selected set of columns for data transfer between memory locations in the first selected set of columns of a first row of the random access memory portion and the serial access memory portion, and transfer gates corresponding to a second selected set of columns for data transfer between memory locations in a second selected set of columns of a second row of the random access memory portion and the serial access memory portion, the data transfers being simultaneous.
  • the random access memory portion is divided into at least two segments in such a way that logically adjacent rows are located in different segments and further characterised in that said first row is located in a first segment and that said second row is logically adjacent the first row and located in a different segment.
  • the selected sets of columns can comprise integer multiples of n columns, where n is 2, 4, 8 or higher powers of 2. This reduces the demand on the decoding of tie column address in the transfer gate selection.
  • the invention has beneficial application even when the granularity is extremely coarse. If only the most significant 3 bits of the column address are decoded the transfer gates are divided into 8 separate blocks along the row length. In the most extreme form, only the most significant bit of the column address is used to select transfer gates divided into 2 separate blocks.
  • said first selected set of columns are the columns located between one end of the row and a selected column, including the selected column
  • said second selected set of columns are the columns located between said selected column and the other end of the another row, not including the selected column, the selected column being selectable by the control logic.
  • the memory device can include a pointer capable of being loaded with an initial address indicating the location in the serial access memory portion that is currently available at the serial access means the pointer being updated, simultaneously with the data transfer between the random access memory portion and the serial access memory portion, with the value of said selected column.
  • This aspect of the invention is advantageous when the data transfer occurs with the serial clock inactive.
  • the memory device can include a pointer capable of being loaded with an initial address indicating the location in the serial access memory portion that is currently available at the serial access means, the pointer not being updated simultaneously with the data transfer between the random access memory portion and the serial access memory portion.
  • This aspect of the invention is advantageous when the data transfer occurs with the serial clock active.
  • the memory device can also include a pointer capable of being loaded with an initial address indicating the cell in the serial access memory portion that is currently available at the serial access means and the pointer being updated, simultaneously with the data transfer between the random access memory portion and the serial access memory portion, with a value different from that of the selected column.
  • a memory device finds particular, though not exclusive, application as a display memory for storing data representative of an image to be displayed in a display system, which may be incorporated in a data processing system. Accordingly, therefore the invention also relates to a display system including such a memory device and a display device.
  • FIG. 1 The structure of a conventional VRAM is shown by Figure 1. It comprises a RAM array 1, a SAM array 2, address/control logic 3, and transfer gates 4.
  • the RAM array is connected to the primary (RAM) port 5 of the VRAM and behaves in a manner identical to that of a DRAM, under the control of the address/control logic.
  • the SAM array is connected to the secondary (SAM or Serial) port 6 of the VRAM and may be accessed serially under the control of an external asynchronous clock 7, the Serial Clock.
  • the serial access to the SAM is controlled by the Tap Pointer (TAP) 8, which generates an address into the SAM from a counter which increments on each cycle of the Serial Clock.
  • TAP Tap Pointer
  • the Tap Pointer (TAP) is capable of being loaded with an initial address, under the control of the address/control logic.
  • the address/control logic 3 supervises the address multiplexing and the data flow on the RAM port 5 and provides all the control and global timing functions of the VRAM.
  • the transfer gates 4 allow memory data to pass between the RAM array 1 and the SAM array 2, under the control of the address/control logic 3.
  • a Read Data Transfer cycle is indicated by DT/OE set to a low level at the falling edge of the Row Address Strobe (RAS).
  • RAS Row Address Strobe
  • RAS Row Address Strobe
  • C Column Address Strobe
  • the actual RAM to SAM data transfer occurs at the rising edge of DT/OE.
  • the SAM is loaded with the contents of RAM array row R and the Tap Pointer (TAP) is loaded with the column address C.
  • the first item of serial data is ⁇ R;C ⁇ .
  • ⁇ R;C ⁇ refers to the data item at row R and column C.
  • ⁇ R;C:C + 4 ⁇ refers to 5 data items at row R and columns C through C+4. This notation will be used throughout the description.
  • Each subsequent rising edge of the Serial Clock causes the Tap Pointer to increment and present the contents of the SAM serially at the SAM port: ⁇ R;C ⁇ is followed by ⁇ R;C+ 1 ⁇ , then by ⁇ R;C + 2 ⁇ and so on.
  • the row address (R) is obtained from the address input and two rows (R and R + 1) are activated.
  • the column address (C) is obtained from the address input.
  • data is transferred between the two RAM array rows (R and R + 1) and the SAM.
  • Data is transferred between RAM array row R, column locations C to the row end, and SAM locations C to the end of the SAM. Additionally, data is transferred between RAM array row R + 1, column locations 0 to C-1, and SAM locations 0 to C-1.
  • the parameter END is used for the last column address of a row and the last address of the SAM.
  • the dyadic operator ! indicates concatenation.
  • This form of data transfer we shall designate Column Wrapped Data Transfer (CWDT).
  • the column address (C) forms the boundary of the CWDT.
  • the SAM contains a full row of continuous data from address ⁇ R;C ⁇ to ⁇ R+1;C-1 ⁇ , starting at SAM(C).
  • the data is continuous in RAM address space starting at the CWDT boundary with ⁇ R;C ⁇ at SAM(C) and wrapping around the end of the SAM through to ⁇ R+1;C-1 ⁇ at SAM(C-1). This is shown diagrammatically as the map of the SAM and its contents shown by Figure 4.
  • the CWDT function may be used as an alternative to, or in addition to the conventional data transfer accesses available in current VRAMs.
  • VRAM providing CWDT and conventional data transfers, these may be distinguished through the use of a function pin or by another suitable means. In the embodiment described here it is assumed that the CWDT function is used in place of conventional VRAM data transfers.
  • the RAM array be segmented into at least two segments such that at least one row address bit (including the least significant bit) is used to select a segment and the remainder of the row address bits are used to select a row within each segment.
  • Such memory segmentation is employed in large memories in order to reduce the loading on individual rows and columns. This decreases signal generation and propagation delays while reducing both variation in data rates and power consumption.
  • the segmentation of the memory also enables the simplification of the simultaneous activation of a plurality of rows by placing logically sequential rows in physically separate segments.
  • FIG. 5 is a block diagram of a VRAM with the RAM array segmented into two physically separate segments. One segment contains all even rows and the other contains all odd rows. Each segment has a separate set of transfer gates 9,10 to allow memory data to pass between the RAM array segments 11,12 and the SAM array 13, under the control of the address/control logic 14.
  • the RAM Port 15 operation of the VRAM is unchanged, and its SAM port operation, 16 is only changed by the use of the CWDT function.
  • the CWDT data transfer is achieved by the address/control logic 14 activating two rows (R and R + 1 in separate segments) and selecting which transfer gates to open, allowing selective data transfer between the two rows and the SAM.
  • the address/control logic selects transfer gates (C:END) for the segment containing row R and transfer gates (0:C-1) for the segment containing row R + 1.
  • C:END transfer gates
  • the CWDT boundary is quantised at single column granularity and this requires that the column address (C) he fully decoded for the selection of transfer gates. In many cases however, it would be sufficient to quantise the CWDT boundary at higher granularity (e.g. at 2,4,8,16,32... column boundaries).
  • the invention has beneficial application even when the CWDT boundary granularity is extremely coarse. If only the most significant 3 bits of C are decoded the transfer gates are divided into 8 separate blocks along the row length. In the most extreme form, only the most significant bit of C is used to select transfer gates divided into 2 separate blocks.
  • CWDT may be used as an alternative to, or in addition to the conventional data transfer cycles available in current VRAMs. Although CWDT will be discussed in relation to Read Data Transfers (RAM to SAM), as used in a display memory subsystem, it also finds application in relation to Write Data Transfers (SAM to RAM) found in some current VRAMs. The application of CWDT to Write Data Transfers will not be discussed but is within the scope of the present invention, as will be apparent to those skilled in the art.
  • the present invention provides for two forms of CWDT.
  • the two forms differ only in whether or not the Tap Pointer 17 is updated.
  • the first form of CWDT designated CWDT#1
  • CWDT#2 is similar to a conventional Read Data Transfer in that, at the data transfer, the Tap Pointer is loaded with the column address (C) obtained at the falling edge of CAS.
  • the second form of CWDT designated CWDT#2
  • Both forms of CWDT may be used with the Serial Clock either inactive or running. It is considered that CWDT#1 is more likely to be used with the Serial Clock inactive and CWDT#2 is more likely to be used with the Serial Clock running.
  • CWDT#1 updates both the contents of the SAM and the Tap Pointer, therefore, if it is used with the Serial Clock running, the data transfer must be accurately timed with respect to the Serial Clock cycles.
  • CWDT#2 updates only the contents of the SAM. When CWDT#2 is used with the Serial Clock running, provided the data transferred is the same as and overlaps the previous SAM data in the region of the Tap Pointer, the data transfer need not be accurately timed with respect to the Serial Clock cycles.
  • Figures 6 and 7 are timing diagrams illustrating the two forms of CWDT data transfer.
  • Figure 6 illustrates the first type of CWDT, CWDT#1, by a Read Data Transfer with the Serial Clock inactive.
  • Figure 7 illustrates the second type of CWDT, CWDT#2, by a Read Data Transfer with the Serial Clock active.
  • the two forms of CWDT data transfer are distinguished by the level of CAS at the rising edge of DT/OE. If CAS is at a low active level at the rising edge of DT/OE then the Tap Pointer is updated. This is the CWDT#1 read data transfer as shown by Figure 6. If CAS is at a high inactive level at the rising edge of DT/OE then the Tap Pointer is not updated. This is the CWDT#2 read data transfer as shown by Figure 7.
  • a Read Data Transfer cycle is indicated by DT/OE set to a low level at the falling edge of RAS.
  • the row address (R) is obtained from the address input and two rows (R and R + 1 in separate segments) are activated.
  • the column address (C) is obtained from the address input.
  • the column address (C) forms the boundary of the CWDT.
  • the actual RAM to SAM data transfer occurs at the rising edge of DT/OE.
  • the level of the CAS at the rising edge of DT/OE determines whether the Tap Pointer (TAP) is to be loaded with the column address C, hence whether the CWDT is a CWDT#1 or a CWDT#2.
  • TAP Tap Pointer
  • the SAM is loaded with ⁇ R+1;0:C-1 ⁇ ⁇ ⁇ R;C:END ⁇ , the contents of RAM array rows R and R + divided at the CWDT boundary (C), and the Tap Pointer (TAP) is loaded with the column address C if the CWDT access is a CWDT#1.
  • the new contents of the SAM are available at the SAM port, starting at the SAM location given by the Tap Pointer value at the time of the first Serial Clock rising edge.
  • serial data sequence around the time of the Tap Pointer wrapping back is ⁇ R;END-1 ⁇ , ⁇ R;END ⁇ , ⁇ R+1;0 ⁇ , ⁇ R+1;1 ⁇ , ⁇ R+1;2 ⁇ and so on.
  • the serial data sequence moves across the row boundary in a seamless and continuous manner in RAM address space.
  • the SAM is loaded with ⁇ R+1;0:C-1 ⁇ ⁇ R;C:END ⁇ .
  • the data in SAM locations SAM(C:C+8) is unchanged by the data transfer and remains as ⁇ R;C:C+8 ⁇ . This region of unchanged data is termed the "Overlap Region".
  • the serial data sequence can proceed in a seamless manner and continuously from ⁇ R-1;C + 9) through to ⁇ R + 1;C-1 ⁇ , nearly two full rows linked by a single CWDT#2 access; a sequence which can be extended by further CWDT#2 accesses. This is achieved without any real-time data transfers.
  • a Mid-Line Reload using a conventional real-time read data transfer has a "Transfer Window" confined to a single Serial Clock cycle
  • a CWDT#2 read data transfer has a Transfer Window as wide as the Overlap Region.
  • the size of the Overlap Region may be chosen, based on system constraints, to avoid any critical timing of the data transfer and is definable by the system designer.
  • the CWDT boundary is obtained from the address input.
  • CAS is at an active low level (i.e. CWDT#1)
  • the value used to update the Tap Pointer is obtained from the address input at the rising edge of DT/OE.
  • the CWDT boundary and the Tap Pointer can be set at different values. This has a certain synergy with conventional data transfers, in that they always have a CWDT boundary of 0 and the Tap Pointer can be updated with a value obtained from the address input.
  • FIG. 9 is a block diagram of a display system employing a memory according to the invention. It shows a workstation consisting of a Central Processing Unit (CPU) 20, a Read Only Store (ROS) 22, a Random Access Memory 24, a disk drive for data storage 26, a user interface 28 which may be a keyboard and/or a mouse, a display device 30 connected via a display adapter 32. These units are connected together by a system bus 34.
  • the display adapter 32 contains a display memory which employs a VRAM, according to the invention, wherein the RAM portion is updated via the RAM port, and the serial access port is used to provide data to be rastered onto the display, 30. It should be noted that this is only one possible embodiment of a display system according to the invention. Many other types are possible, including mainframe data processing systems with a number of users wherein there is a display device and display adapter for each user.
  • Every CWDT read data transfer loads the SAM with data that is continuous in RAM address space starting at the CWDT boundary and of a length equal to the full capacity of the SAM.
  • the serial data sequence can move in a seamless manner across a row address boundary, providing sequential data up to the full capacity of the SAM before a further data transfer is required.
  • a conventional read data transfer does not permit the serial data sequence to move across row address boundaries without a real-time data transfer.
  • a conventional read data transfer can only utilise the full capacity of the SAM, in a manner appropriate to a display memory subsystem, when the column address is 0.
  • the invention may, in certain circumstances, eliminate the need for "Mid-Line Reloads" in a display memory subsystem, by utilising the full capacity of the SAM. Additionally, in certain circumstances, the invention may reduce the number of VRAM data transfers required for each display frame. Where system constraints prevent the total avoidance of "Mid-Line Reloads", or where it is advantageous to use "Mid-Line Reloads", the CWDT#2 data transfer provides a means of eliminating the real-time nature of the "Mid-Line Reload".
  • CWDT By removing the need for real-time VRAM data transfers, CWDT eliminates the need for the potentially complex and high speed circuitry required to synchronise and control such data transfers, and eliminates the potentially wasteful use of RAM port bandwidth in the synchronisation of such data transfers. It is an advantage of the invention that CWDT may be used as an alternative to, or in addition to the conventional data transfer accesses available in current VRAMs. Although CWDT has been discussed in relation to Read Data Transfers (RAM to SAM), as used in a display memory subsystem, it also finds application in relation to the Write Data Transfers (SAM to RAM) found in some current VRAMs. The application of CWDT to Write Data Transfers is within the scope of the invention, as will be apparent to those skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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EP19910304736 1990-06-19 1991-05-24 Mémoire vidéo à accès aléatoire Expired - Lifetime EP0462708B1 (fr)

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US54054690A 1990-06-19 1990-06-19
US540546 1990-06-19

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EP0462708A2 true EP0462708A2 (fr) 1991-12-27
EP0462708A3 EP0462708A3 (en) 1992-04-22
EP0462708B1 EP0462708B1 (fr) 1996-11-27

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Citations (5)

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US4688032A (en) * 1982-06-28 1987-08-18 Tokyo Shibaura Denki Kabushiki Kaisha Image display control apparatus
US4825411A (en) * 1986-06-24 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Dual-port memory with asynchronous control of serial data memory transfer
US4855959A (en) * 1986-07-04 1989-08-08 Nec Corporation Dual port memory circuit
EP0398510A2 (fr) * 1989-05-16 1990-11-22 International Business Machines Corporation Mémoire à accès aléatoire pour vidéo
EP0427114A2 (fr) * 1989-11-07 1991-05-15 Micron Technology, Inc. Architecture de registre de masquage de bits à grande vitesse

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JPS60162287A (ja) * 1984-01-23 1985-08-24 三菱電機株式会社 画像メモリのアクセス処理装置
JPH01112592A (ja) * 1987-10-26 1989-05-01 Matsushita Electric Ind Co Ltd 半導体記憶装置
JPH0281397A (ja) * 1988-09-19 1990-03-22 Hitachi Ltd 画像メモリ装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688032A (en) * 1982-06-28 1987-08-18 Tokyo Shibaura Denki Kabushiki Kaisha Image display control apparatus
US4825411A (en) * 1986-06-24 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Dual-port memory with asynchronous control of serial data memory transfer
US4855959A (en) * 1986-07-04 1989-08-08 Nec Corporation Dual port memory circuit
EP0398510A2 (fr) * 1989-05-16 1990-11-22 International Business Machines Corporation Mémoire à accès aléatoire pour vidéo
EP0427114A2 (fr) * 1989-11-07 1991-05-15 Micron Technology, Inc. Architecture de registre de masquage de bits à grande vitesse

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
WORLD PATENTS INDEX LATEST Week 8942, Derwent Publications Ltd., London, GB; AN 89-308294 ANONYMOUS: "Continuous read row addressable random access memory- has data divided into segments that can be independently loaded into read-out shift register to provide long continuous data stream". EP 91304736030 *
WORLD PATENTS INDEX LATEST Week 8942, Derwent Publications Ltd., London, GB; AN 89-308298 ANONYMOUS: "Row addressable random access memory for video monitor storage, allows serial read-out to begin at arbitrary column location, while retaining column redundancy". *

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EP0462708B1 (fr) 1996-11-27
JP2744854B2 (ja) 1998-04-28
DE69123291D1 (de) 1997-01-09
JPH04229485A (ja) 1992-08-18
EP0462708A3 (en) 1992-04-22

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