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EP0371742A3 - Image memory control apparatus - Google Patents

Image memory control apparatus Download PDF

Info

Publication number
EP0371742A3
EP0371742A3 EP19890312312 EP89312312A EP0371742A3 EP 0371742 A3 EP0371742 A3 EP 0371742A3 EP 19890312312 EP19890312312 EP 19890312312 EP 89312312 A EP89312312 A EP 89312312A EP 0371742 A3 EP0371742 A3 EP 0371742A3
Authority
EP
European Patent Office
Prior art keywords
control
access
image data
selector
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890312312
Other languages
German (de)
French (fr)
Other versions
EP0371742A2 (en
Inventor
Hisashi Intellectual Property Division Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0371742A2 publication Critical patent/EP0371742A2/en
Publication of EP0371742A3 publication Critical patent/EP0371742A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Television Systems (AREA)

Abstract

An image memory control apparatus containing a memory device (220) for storing image data and control data. The apparatus includes a display address generator (210) for generating addresses of the stored image data, a display address selector (211) for selecting desired image data addresses sequentially in a fixed order, a control address generator (100) for generating addresses of the stored control data, an access selector (220) for combining the image data addresses and the control data address and a controller (214) for controlling the access selector (220), wherein the controller (214) includes a circuit (214) for shifting the control of the access selector (220) to immediately access the stored control data in response to an access requesting signal.
EP19890312312 1988-11-28 1989-11-28 Image memory control apparatus Withdrawn EP0371742A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP300090/88 1988-11-28
JP63300090A JPH02146088A (en) 1988-11-28 1988-11-28 Display memory controller

Publications (2)

Publication Number Publication Date
EP0371742A2 EP0371742A2 (en) 1990-06-06
EP0371742A3 true EP0371742A3 (en) 1991-08-14

Family

ID=17880588

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890312312 Withdrawn EP0371742A3 (en) 1988-11-28 1989-11-28 Image memory control apparatus

Country Status (2)

Country Link
EP (1) EP0371742A3 (en)
JP (1) JPH02146088A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104624A (en) * 1975-12-29 1978-08-01 Hitachi, Ltd. Microprocessor controlled CRT display system
EP0254293A2 (en) * 1986-07-25 1988-01-27 Fujitsu Limited Cathode ray tube controller
US4802118A (en) * 1983-11-25 1989-01-31 Hitachi, Ltd. Computer memory refresh circuit
US4845661A (en) * 1985-08-19 1989-07-04 Nec Corporation Display information processing apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104624A (en) * 1975-12-29 1978-08-01 Hitachi, Ltd. Microprocessor controlled CRT display system
US4802118A (en) * 1983-11-25 1989-01-31 Hitachi, Ltd. Computer memory refresh circuit
US4845661A (en) * 1985-08-19 1989-07-04 Nec Corporation Display information processing apparatus
EP0254293A2 (en) * 1986-07-25 1988-01-27 Fujitsu Limited Cathode ray tube controller

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 28, no. 2, July 1985, pages 571-572, New York, US; "DMA cycle steal function in a general-purpose signal processor" *

Also Published As

Publication number Publication date
EP0371742A2 (en) 1990-06-06
JPH02146088A (en) 1990-06-05

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